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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id t11-20020aa7d4cb000000b0044e8774914esm917640edr.35.2022.09.09.13.18.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 13:18:46 -0700 (PDT) Message-ID: <93a444c4-33bc-ddaa-c6a9-e4d28df2b815@gmail.com> Date: Fri, 9 Sep 2022 22:18:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 From: Johan Jonker Subject: [PATCH v3 1/5] rockchip: rk3128-cru: sync the clock dt-binding header from Linux To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de Content-Language: en-US X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean In order to update the DT for rk3128 sync the clock dt-binding header. This is the state as of v6.0 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3128.dtsi | 6 +- drivers/clk/rockchip/clk_rk3128.c | 8 +- include/dt-bindings/clock/rk3128-cru.h | 222 +++++++++++++++++-------- 3 files changed, 160 insertions(+), 76 deletions(-) diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5d2499c1..3c5f54f6 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -172,7 +172,7 @@ interrupts = , ; #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; + clocks = <&cru ACLK_DMAC>; clock-names = "apb_pclk"; }; }; @@ -530,8 +530,8 @@ pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; rockchip,spi-src-clk = <0>; num-cs = <2>; - clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>; - clock-names = "spi","pclk_spi0"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; dmas = <&pdma 8>, <&pdma 9>; #dma-cells = <2>; dma-names = "tx", "rx"; diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index d5b2b63d..13e176cd 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -438,7 +438,7 @@ static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) VIO1_SEL_GPLL << VIO1_PLL_SHIFT | (src_clk_div - 1) << VIO1_DIV_SHIFT); break; - case DCLK_LCDC: + case DCLK_VOP: if (pll_para_config(hz, &cpll_config)) return -1; rkclk_set_pll(cru, CLK_CODEC, &cpll_config); @@ -471,7 +471,7 @@ static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id) div = (con >> 8) & 0x1f; parent = GPLL_HZ; break; - case DCLK_LCDC: + case DCLK_VOP: con = readl(&cru->cru_clksel_con[27]); div = (con >> 8) & 0xfff; parent = rkclk_pll_get_rate(cru, CLK_CODEC); @@ -497,7 +497,7 @@ static ulong rk3128_clk_get_rate(struct clk *clk) return rk3128_peri_get_pclk(priv->cru, clk->id); case SCLK_SARADC: return rk3128_saradc_get_clk(priv->cru); - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: return rk3128_vop_get_rate(priv->cru, clk->id); @@ -515,7 +515,7 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0 ... 63: return 0; - case DCLK_LCDC: + case DCLK_VOP: case ACLK_VIO0: case ACLK_VIO1: new_rate = rk3128_vop_set_clk(priv->cru, diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index cfb3afbb..6a47825d 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Elaine */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H @@ -9,30 +10,31 @@ /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 +#define PLL_GPLL_DIV2 6 +#define PLL_GPLL_DIV3 7 /* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 #define SCLK_SDMMC 68 #define SCLK_SDIO 69 #define SCLK_EMMC 71 -#define SCLK_NANDC 76 #define SCLK_UART0 77 #define SCLK_UART1 78 #define SCLK_UART2 79 -#define SCLK_I2S 82 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 #define SCLK_SPDIF 83 #define SCLK_TIMER0 85 #define SCLK_TIMER1 86 #define SCLK_TIMER2 87 #define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 #define SCLK_SARADC 91 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 #define SCLK_I2S_OUT 113 #define SCLK_SDMMC_DRV 114 #define SCLK_SDIO_DRV 115 @@ -40,115 +42,173 @@ #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 +#define SCLK_VOP 122 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_HEVC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_DDRC 144 +#define SCLK_PVTM_FUNC 145 +#define SCLK_PVTM_CORE 146 +#define SCLK_PVTM_GPU 147 +#define SCLK_MIPI_24M 148 +#define SCLK_PVTM 149 +#define SCLK_CIF_SRC 150 +#define SCLK_CIF_OUT_SRC 151 +#define SCLK_CIF_OUT 152 +#define SCLK_SFC 153 +#define SCLK_USB480M 154 -#define DCLK_LCDC 190 +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_EBC 191 /* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_VIO0 197 -#define ACLK_VIO1 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 +#define ACLK_VIO0 192 +#define ACLK_VIO1 193 +#define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VEPU 196 +#define ACLK_VDPU 197 +#define ACLK_CIF 198 +#define ACLK_IEP 199 +#define ACLK_LCDC0 204 +#define ACLK_RGA 205 #define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_SARADC 318 +#define PCLK_WDT 319 #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_MIPI 325 +#define PCLK_EFUSE 326 +#define PCLK_HDMI 327 +#define PCLK_ACODEC 328 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 #define PCLK_I2C2 334 #define PCLK_I2C3 335 -#define PCLK_SPI 338 +#define PCLK_SPI0 338 #define PCLK_UART0 341 #define PCLK_UART1 342 #define PCLK_UART2 343 +#define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 +#define PCLK_CPU 354 #define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 +#define PCLK_GMAC 367 +#define PCLK_PMU_PRE 368 +#define PCLK_SIM_CARD 369 /* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 +#define HCLK_SPDIF 440 +#define HCLK_GPS 441 +#define HCLK_USBHOST 442 +#define HCLK_I2S_8CH 443 +#define HCLK_I2S_2CH 444 +#define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 +#define HCLK_CPU 460 +#define HCLK_VEPU 461 +#define HCLK_VDPU 462 +#define HCLK_LCDC0 463 +#define HCLK_EBC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_CIF 470 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_CRYPTO 476 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) /* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 #define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 +#define SRST_L2C 15 -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 +#define SRST_CPUSYS_H 18 +#define SRST_AHB2APBSYS_H 19 +#define SRST_SPDIF 20 #define SRST_INTMEM 21 #define SRST_ROM 22 #define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 +#define SRST_I2S_2CH 24 +#define SRST_I2S_8CH 25 +#define SRST_GPU_PVTM 26 +#define SRST_FUNC_PVTM 27 +#define SRST_CORE_PVTM 29 #define SRST_EFUSE_P 30 #define SRST_ACODEC_P 31 #define SRST_GPIO0 32 #define SRST_GPIO1 33 #define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_MIPIPHY_P 36 #define SRST_UART0 39 #define SRST_UART1 40 #define SRST_UART2 41 #define SRST_I2C0 43 #define SRST_I2C1 44 #define SRST_I2C2 45 +#define SRST_I2C3 46 #define SRST_SFC 47 -#define SRST_PWM0 48 +#define SRST_PWM 48 +#define SRST_DAP_PO 50 #define SRST_DAP 51 #define SRST_DAP_SYS 52 +#define SRST_CRYPTO 53 #define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 +#define SRST_GMAC 56 +#define SRST_PERIPH_SYS_A 57 +#define SRST_PERIPH_SYS_H 58 +#define SRST_PERIPH_SYS_P 59 +#define SRST_SMART_CARD 60 #define SRST_CPU_PERI 61 #define SRST_EMEM_PERI 62 #define SRST_USB_PERI 63 -#define SRST_DMA2 64 -#define SRST_MAC 66 +#define SRST_DMA 64 +#define SRST_GPS 67 #define SRST_NANDC 68 #define SRST_USBOTG0 69 #define SRST_OTGC0 71 @@ -156,34 +216,58 @@ #define SRST_OTGC1 74 #define SRST_DDRMSCH 79 -#define SRST_MMC0 81 +#define SRST_SDMMC 81 #define SRST_SDIO 82 #define SRST_EMMC 83 -#define SRST_SPI0 84 +#define SRST_SPI 84 #define SRST_WDT 86 #define SRST_SARADC 87 #define SRST_DDRPHY 88 #define SRST_DDRPHY_P 89 #define SRST_DDRCTRL 90 #define SRST_DDRCTRL_P 91 +#define SRST_TSP 92 +#define SRST_TSP_CLKIN 93 +#define SRST_HOST0_ECHI 94 #define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_VIO0_A 98 #define SRST_VIO_BUS_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 #define SRST_UTMI0 103 #define SRST_UTMI1 104 #define SRST_USBPOR 105 +#define SRST_IEP_A 106 +#define SRST_IEP_H 107 +#define SRST_RGA_A 108 +#define SRST_RGA_H 109 +#define SRST_CIF0 110 +#define SRST_PMU 111 #define SRST_VCODEC_A 112 #define SRST_VCODEC_H 113 #define SRST_VIO1_A 114 -#define SRST_HEVC 115 +#define SRST_HEVC_CORE 115 #define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 +#define SRST_PMU_NIU_P 117 +#define SRST_LCDC0_S 119 #define SRST_GPU 120 #define SRST_GPU_NIU_A 122 +#define SRST_EBC_A 123 +#define SRST_EBC_H 124 -#define SRST_DBG_P 131 +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_VIO_MIPI_DSI 137 #endif From patchwork Fri Sep 9 20:18:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 1676229 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id 7-20020a170906308700b0072b1bc9b37fsm709832ejv.22.2022.09.09.13.18.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 13:18:56 -0700 (PDT) Message-ID: <574a83a7-72e6-a787-c680-24b30335b035@gmail.com> Date: Fri, 9 Sep 2022 22:18:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 From: Johan Jonker Subject: [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de References: <20220909200256.15981-1-jbx6244@gmail.com> Content-Language: en-US In-Reply-To: <20220909200256.15981-1-jbx6244@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Bulk convert rk3128 DT gpios to their constant counterparts. sed -i -f script.sed rk3128.dtsi sed -i -f script.sed rk3128-evb.dts ================================ /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/ Reviewed-by: Kever Yang --- arch/arm/dts/rk3128-evb.dts | 4 +- arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index 2fb2b0da..a407ac2d 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -82,13 +82,13 @@ &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 3c5f54f6..5a1c1547 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -618,85 +618,85 @@ */ emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_pwren: emmc-pwren { - rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; nandc{ nandc_ale:nandc-ale { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cle:nandc-cle { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_wrn:nandc-wrn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdn:nandc-rdn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdy:nandc-rdy { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cs0:nandc-cs0 { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_data: nandc-data { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>; }; }; @@ -727,75 +727,75 @@ pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 3 &pcfg_pull_none>, - <2 21 3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; spi0 { spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; }; From patchwork Fri Sep 9 20:19:06 2022 Content-Type: text/plain; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id r7-20020a056402018700b0044e96f11359sm952903edv.3.2022.09.09.13.19.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 13:19:07 -0700 (PDT) Message-ID: <35c3e6de-189a-f0df-b790-17191ed2313b@gmail.com> Date: Fri, 9 Sep 2022 22:19:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 From: Johan Jonker Subject: [PATCH v3 3/5] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de References: <20220909200256.15981-1-jbx6244@gmail.com> Content-Language: en-US In-Reply-To: <20220909200256.15981-1-jbx6244@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Move all rk3128 u-boot specific properties in separate dtsi files. Sort emmc node. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- Changed V2: Keep max-frequency property in dtsi --- arch/arm/dts/rk3128-evb-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3128-evb.dts | 10 +++++----- arch/arm/dts/rk3128-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/rk3128.dtsi | 9 --------- 4 files changed, 31 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/rk3128-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3128-u-boot.dtsi diff --git a/arch/arm/dts/rk3128-evb-u-boot.dtsi b/arch/arm/dts/rk3128-evb-u-boot.dtsi new file mode 100644 index 00000000..8b16bbe4 --- /dev/null +++ b/arch/arm/dts/rk3128-evb-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3128-u-boot.dtsi" + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index a407ac2d..e7d8f7c9 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -37,6 +37,11 @@ }; }; +&emmc { + fifo-mode; + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -74,11 +79,6 @@ status = "okay"; }; -&emmc { - fifo-mode; - status = "okay"; -}; - &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi new file mode 100644 index 00000000..4a98e249 --- /dev/null +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc: dmc@20004000 { + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 5a1c1547..b58804b6 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -237,14 +237,7 @@ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; }; - dmc: dmc@20004000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3128-dmc", "syscon"; - reg = <0x0 0x20004000 0x0 0x1000>; - }; - cru: clock-controller@20000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; rockchip,grf = <&grf>; @@ -453,7 +446,6 @@ }; emmc: dwmmc@1021c000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -538,7 +530,6 @@ }; grf: syscon@20008000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-grf", "syscon"; reg = <0x20008000 0x1000>; }; From patchwork Fri Sep 9 20:19:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 1676231 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id l18-20020a1709060cd200b0077934671cb6sm708740ejh.56.2022.09.09.13.19.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 13:19:25 -0700 (PDT) Message-ID: Date: Fri, 9 Sep 2022 22:19:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 From: Johan Jonker Subject: [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de References: <20220909200256.15981-1-jbx6244@gmail.com> Content-Language: en-US In-Reply-To: <20220909200256.15981-1-jbx6244@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean The rk3128 DT node names should be generic. Rename them to the pattern defined in the DT bindings. Signed-off-by: Johan Jonker --- arch/arm/dts/rk3128-evb.dts | 5 +++ arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index e7d8f7c9..93291d78 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -15,6 +15,11 @@ stdout-path = &uart2; }; + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + vcc5v0_otg: vcc5v0-otg-drv { compatible = "regulator-fixed"; regulator-name = "vcc5v0_otg"; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index b58804b6..48833bff 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -8,7 +8,6 @@ #include #include #include -#include "skeleton.dtsi" / { compatible = "rockchip,rk3128"; @@ -34,11 +33,6 @@ mmc1 = &sdmmc; }; - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - arm-pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -52,10 +46,10 @@ #size-cells = <0>; enable-method = "rockchip,rk3128-smp"; - cpu0:cpu@0x000 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x000>; + reg = <0x0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -65,22 +59,22 @@ clocks = <&cru ARMCLK>; }; - cpu1:cpu@0x001 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x001>; + reg = <0x1>; }; - cpu2:cpu@0x002 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x002>; + reg = <0x2>; }; - cpu3:cpu@0x003 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x003>; + reg = <0x3>; }; }; @@ -165,7 +159,7 @@ interrupt-parent = <&gic>; ranges; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; arm,pl330-broken-no-flushp;//2 @@ -207,7 +201,7 @@ rockchip,broadcast = <1>; }; - watchdog: wdt@2004c000 { + watchdog: watchdog@2004c000 { compatible = "rockchip,watch dog"; reg = <0x2004c000 0x100>; clock-names = "pclk_wdt"; @@ -224,7 +218,7 @@ #reset-cells = <1>; }; - nandc: nandc@10500000 { + nandc: nand-controller@10500000 { compatible = "rockchip,rk-nandc"; reg = <0x10500000 0x4000>; interrupts = ; @@ -247,7 +241,7 @@ assigned-clock-rates = <594000000>; }; - uart0: serial0@20060000 { + uart0: serial@20060000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20060000 0x100>; interrupts = ; @@ -262,7 +256,7 @@ #dma-cells = <2>; }; - uart1: serial1@20064000 { + uart1: serial@20064000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20064000 0x100>; interrupts = ; @@ -277,7 +271,7 @@ #dma-cells = <2>; }; - uart2: serial2@20068000 { + uart2: serial@20068000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20068000 0x100>; interrupts = ; @@ -304,7 +298,7 @@ status = "disabled"; }; - pwm0: pwm0@20050000 { + pwm0: pwm@20050000 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050000 0x10>; #pwm-cells = <3>; @@ -314,7 +308,7 @@ clock-names = "pwm"; }; - pwm1: pwm1@20050010 { + pwm1: pwm@20050010 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050010 0x10>; #pwm-cells = <3>; @@ -324,7 +318,7 @@ clock-names = "pwm"; }; - pwm2: pwm2@20050020 { + pwm2: pwm@20050020 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050020 0x10>; #pwm-cells = <3>; @@ -334,7 +328,7 @@ clock-names = "pwm"; }; - pwm3: pwm3@20050030 { + pwm3: pwm@20050030 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050030 0x10>; #pwm-cells = <3>; @@ -430,7 +424,7 @@ status = "disabled"; }; - sdmmc: dwmmc@10214000 { + sdmmc: mmc@10214000 { compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; max-frequency = <150000000>; @@ -445,7 +439,7 @@ status = "disabled"; }; - emmc: dwmmc@1021c000 { + emmc: mmc@1021c000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -464,7 +458,7 @@ status = "disabled"; }; - i2c0: i2c0@20072000 { + i2c0: i2c@20072000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <20072000 0x1000>; interrupts = ; @@ -476,7 +470,7 @@ pinctrl-0 = <&i2c0_xfer>; }; - i2c1: i2c1@20056000 { + i2c1: i2c@20056000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x20056000 0x1000>; interrupts = ; @@ -488,7 +482,7 @@ pinctrl-0 = <&i2c1_xfer>; }; - i2c2: i2c2@2005a000 { + i2c2: i2c@2005a000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005a000 0x1000>; interrupts = ; @@ -500,7 +494,7 @@ pinctrl-0 = <&i2c2_xfer>; }; - i2c3: i2c3@2005e000 { + i2c3: i2c@2005e000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005e000 0x1000>; interrupts = ; @@ -546,7 +540,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2007c000 { + gpio0: gpio@2007c000 { compatible = "rockchip,gpio-bank"; reg = <0x2007c000 0x100>; interrupts = ; @@ -557,7 +551,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@20080000 { + gpio1: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = ; @@ -568,7 +562,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@20084000 { + gpio2: gpio@20084000 { compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = ; @@ -579,7 +573,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio2@20088000 { + gpio3: gpio@20088000 { compatible = "rockchip,gpio-bank"; reg = <0x20088000 0x100>; interrupts = ; From patchwork Fri Sep 9 20:20:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 1676232 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id v18-20020a170906293200b0076f1d939128sm728811ejd.54.2022.09.09.13.20.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Sep 2022 13:20:08 -0700 (PDT) Message-ID: <421195e1-472c-f337-e87a-b0b6d520b808@gmail.com> Date: Fri, 9 Sep 2022 22:20:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 From: Johan Jonker Subject: [PATCH v3 5/5] arm: dts: rockchip: rk3128: fix clocks, compatible and phys To: kever.yang@rock-chips.com Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, u-boot@lists.denx.de References: <20220909200256.15981-1-jbx6244@gmail.com> Content-Language: en-US In-Reply-To: <20220909200256.15981-1-jbx6244@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Fix rk3128 clocks, compatible and phys, so that they match the bindings. Signed-off-by: Johan Jonker --- arch/arm/dts/rk3128.dtsi | 46 +++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 48833bff..3253c640 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -180,7 +180,6 @@ xin12m: xin12m { compatible = "fixed-clock"; - clocks = <&xin24m>; clock-frequency = <12000000>; clock-output-names = "xin12m"; #clock-cells = <0>; @@ -202,9 +201,9 @@ }; watchdog: watchdog@2004c000 { - compatible = "rockchip,watch dog"; + compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; reg = <0x2004c000 0x100>; - clock-names = "pclk_wdt"; + clocks = <&cru PCLK_WDT>; interrupts = ; rockchip,irq = <1>; rockchip,timeout = <60>; @@ -219,21 +218,20 @@ }; nandc: nand-controller@10500000 { - compatible = "rockchip,rk-nandc"; + compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; reg = <0x10500000 0x4000>; interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; - nandc_id = <0>; - clocks = <&cru SCLK_NANDC>, - <&cru HCLK_NANDC>, - <&cru SRST_NANDC>; - clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; }; cru: clock-controller@20000000 { compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -305,7 +303,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm0_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm1: pwm@20050010 { @@ -315,7 +312,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm1_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm2: pwm@20050020 { @@ -325,7 +321,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; pwm3: pwm@20050030 { @@ -335,7 +330,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pwm3_pin>; clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; }; sram: sram@10080400 { @@ -364,7 +358,7 @@ interrupts = ; }; - u2phy: usb2-phy { + u2phy: usb2phy { compatible = "rockchip,rk3128-usb2phy"; reg = <0x017c 0x0c>; rockchip,grf = <&grf>; @@ -372,7 +366,6 @@ clock-names = "phyclk"; #clock-cells = <0>; clock-output-names = "usb480m_phy"; - #phy-cells = <1>; status = "disabled"; u2phy_otg: otg-port { @@ -394,15 +387,14 @@ }; usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb", - "snps,dwc2"; + compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x10180000 0x40000>; interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; dr_mode = "otg"; - g-use-dma; - hnp-srp-disable; - phys = <&u2phy 0>; - phy-names = "usb"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -410,7 +402,7 @@ compatible = "generic-ehci"; reg = <0x101c0000 0x20000>; interrupts = ; - phys = <&u2phy 1>; + phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; }; @@ -419,19 +411,19 @@ compatible = "generic-ohci"; reg = <0x101e0000 0x20000>; interrupts = ; - phys = <&u2phy 1>; + phys = <&u2phy_host>; phy-names = "usb"; status = "disabled"; }; sdmmc: mmc@10214000 { - compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; max-frequency = <150000000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; @@ -446,7 +438,7 @@ interrupts = ; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; bus-width = <8>; default-sample-phase = <158>; num-slots = <1>; @@ -507,7 +499,7 @@ }; spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi"; + compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; reg = <0x20074000 0x1000>; interrupts = ; #address-cells = <1>;