From patchwork Sat Mar 3 08:59:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 880996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LMHoL5BL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztg9t2dZnz9sXK for ; Sat, 3 Mar 2018 20:00:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EEB6FC2208C; Sat, 3 Mar 2018 08:59:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 64E72C21FEC; Sat, 3 Mar 2018 08:59:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D49A7C21F18; Sat, 3 Mar 2018 08:59:27 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id 4C937C21F18 for ; Sat, 3 Mar 2018 08:59:27 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id q83so7200423wme.5 for ; Sat, 03 Mar 2018 00:59:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DJRg4IakHgzTYt5JmOV67Edt2abi7xlPERYJgCyVPCY=; b=LMHoL5BLA83X4AHHGQ8rARm0kFZ2HZ26sl2/u7PAwyjoRl4bPjkSczRKZCH4Hu5LjN JZJg2NEc51Qq7GnAbzcEBUvytktMgOtSW62pJLvgsuk9k+lGr0u1jzDiUzOX5cY6t2np xcbIx16D7eDSiDuJj8WjqEr9Roq919BjWuoUkLpijoza+bq2Culj5jASPtnsocb2xF3z nIfWfy+l18pr4CRQVXBB+AQNXUouKL4A2wYW1cUgNS5nYpLh4ApKo7gNT5f7eZQ+vK65 elFXXJBVBvDtKdO0tGaLgvuLTH93QfiLn8d/7K789MF3MSJkDe4CfwCVs+MxBcj/5s8d jPIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DJRg4IakHgzTYt5JmOV67Edt2abi7xlPERYJgCyVPCY=; b=saFoBfxjZEirWWtGcjX3WhY474JInNGGUcUVvgvnX1t9z2MFJzzqMrdvO/W4fX44Ey t1Yji4aNuzsl8m5rXfyETpCTCjB5TZL4HUY2YVx49F08DVPu+9uO1a2MMPZmDix2W+N7 TRunG1Zfa9Ep4eTvTJgZ9u0KIxjSu2mGX8+v+hHwSVA5nMSDaFwdLy1mTszFPuFDI33L 0SVgBpLN8dQeq4DQXXhgPUZetN7zKdY7e0SJgsyn8vNd/Tw2NmfPizyMEhbV1zK/9ud1 sn3Oxhw46G3FogmyDwf1MyJIN+I0vOroTbtkIDwE9siQPLIAi55bzgT2Foa6T8dYRLHR TCYQ== X-Gm-Message-State: AElRT7HeOhvWGe1AVPS6s6YMdiM497s0wjMvqvdO95OMepCHvRwPS9/T greyjbc668pB5IvgYaG+cdApH3O6 X-Google-Smtp-Source: AG47ELu/NMzIX6tuP3HV3tGcXN3qK0RbLCGh7GljRkrYy5oPO6oH7xgnw0gnhZdPSo915GtDOMUJlA== X-Received: by 10.28.150.138 with SMTP id y132mr3628607wmd.104.1520067566715; Sat, 03 Mar 2018 00:59:26 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:25 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:03 +0100 Message-Id: <20180303085917.8293-2-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 01/15] dma: move dma_ops to dma-uclass.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move dma_ops to a separate header file, following other uclass implementations. While doing so, this patch also improves dma_ops documentation. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- v4: no changes v3: Introduce changes reported by Simon Glass: - Improve dma-uclass.h documentation. - Switch to live tree API. drivers/dma/dma-uclass.c | 3 ++- include/dma-uclass.h | 39 +++++++++++++++++++++++++++++++++++++++ include/dma.h | 22 ---------------------- 3 files changed, 41 insertions(+), 23 deletions(-) create mode 100644 include/dma-uclass.h diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 3d0ce22fbc..6fd4e1b35d 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -10,10 +10,11 @@ */ #include -#include #include #include #include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/include/dma-uclass.h b/include/dma-uclass.h new file mode 100644 index 0000000000..3429f65ec4 --- /dev/null +++ b/include/dma-uclass.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 Texas Instruments Incorporated + * Written by Mugunthan V N + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DMA_UCLASS_H +#define _DMA_UCLASS_H + +/* See dma.h for background documentation. */ + +#include + +/* + * struct dma_ops - Driver model DMA operations + * + * The uclass interface is implemented by all DMA devices which use + * driver model. + */ +struct dma_ops { + /** + * transfer() - Issue a DMA transfer. The implementation must + * wait until the transfer is done. + * + * @dev: The DMA device + * @direction: direction of data transfer (should be one from + * enum dma_direction) + * @dst: The destination pointer. + * @src: The source pointer. + * @len: Length of the data to be copied (number of bytes). + * @return zero on success, or -ve error code. + */ + int (*transfer)(struct udevice *dev, int direction, void *dst, + void *src, size_t len); +}; + +#endif /* _DMA_UCLASS_H */ diff --git a/include/dma.h b/include/dma.h index 71fa77f2ea..89320f10d9 100644 --- a/include/dma.h +++ b/include/dma.h @@ -28,28 +28,6 @@ enum dma_direction { #define DMA_SUPPORTS_DEV_TO_DEV BIT(3) /* - * struct dma_ops - Driver model DMA operations - * - * The uclass interface is implemented by all DMA devices which use - * driver model. - */ -struct dma_ops { - /* - * Get the current timer count - * - * @dev: The DMA device - * @direction: direction of data transfer should be one from - enum dma_direction - * @dst: Destination pointer - * @src: Source pointer - * @len: Length of the data to be copied. - * @return: 0 if OK, -ve on error - */ - int (*transfer)(struct udevice *dev, int direction, void *dst, - void *src, size_t len); -}; - -/* * struct dma_dev_priv - information about a device used by the uclass * * @supported: mode of transfers that DMA can support, should be From patchwork Sat Mar 3 08:59:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881002 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OTss3vzM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgGM6nPyz9sWS for ; Sat, 3 Mar 2018 20:04:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8E824C21FD4; Sat, 3 Mar 2018 09:01:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6F6ECC21F71; Sat, 3 Mar 2018 08:59:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0EEDDC21F67; Sat, 3 Mar 2018 08:59:32 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id EA7B6C21FC5 for ; Sat, 3 Mar 2018 08:59:28 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id t6so6994741wmt.5 for ; Sat, 03 Mar 2018 00:59:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aVksPvwmKRydlLTiveyhbffd8ERKNF8IHFje7hsWWt0=; b=OTss3vzMBPF04GwtUnBKbF5unpwohywYsQh4lLdaHhBY/jUuMiEi61RFNbXVswjKKu mW2sz/WLBLtU72U++8a5YtufNjUts/KKAX5kXtOrIZA/ydhBctbiLJ3KOzEfcmHv61+w FZQOnfzofJQVoMW4BmUEjJSAPAgOwaUtDIkHd/GlfD+DJbHLn9cUjxEMIn4sVb54HDnQ DDguX+92ZtJqtkmMpXI6DXBAxQHQ/Ed+3ZytmpdG4f60Y7CpPQ6wx7+B+DJEVCQ7mnCa /l/ubSgfKyk77NPP5F6VjDKbn4sh3LGUgVMa1gm2DqFA6T+P/97eT8ahpS61KBLhMQx/ 1GzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aVksPvwmKRydlLTiveyhbffd8ERKNF8IHFje7hsWWt0=; b=pcxvJLglUevHkYu3WR2NyamsEGSMNuTQSiwZWg0XTtiNSi0Ti7g3YRpy149jF5dwtX +x754CYaeqBVzTav51oLLoft54D8UffofAdqijcibZxf2MAWRfICvugOK4WaZk8Apyx8 o8VFjByP9dsuuXK2hu4X6SeaE+wDmvqTOaxfpKu73qwF+XxB3rWkRuErdC7MMTjkU/B8 +9zCbed0ZAah/bnC3TMe+47pHu+oWuOu6Aj8pAtZjrLJKCYDsY59Sf65huHhSSzr55E3 dJM8WTz5MEHRKNjT0oMuvm3Lbiy0dua+3UTnFchvdHtBnyhjz9kQQsVqFg+XcH/dQc6h iufw== X-Gm-Message-State: AElRT7HO76yQuEgTKFbq/6UsyVI4pVmHmSyRhbMF3dDl17DGh1dI8MP9 roHb2uYD33QMrnBHHrOowyMJtv+2 X-Google-Smtp-Source: AG47ELsHflc515mh7g7m9kC9MVEm/S9xdmN+VAFtPtzppxKPiW94Nrq2vTA8dDGFlHvn7jjPCOeFVg== X-Received: by 10.28.174.80 with SMTP id x77mr3581354wme.130.1520067567978; Sat, 03 Mar 2018 00:59:27 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:27 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:04 +0100 Message-Id: <20180303085917.8293-3-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 02/15] dma: add channels support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds channels support for dma controllers that have multiple channels which can transfer data to/from different devices (enet, usb...). Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Simon Glass --- v4: no changes v3: Introduce changes reported by Simon Glass: - Improve dma-uclass.h documentation. - Switch to live tree API. drivers/dma/Kconfig | 7 ++ drivers/dma/dma-uclass.c | 188 +++++++++++++++++++++++++++++++++++++++++++++-- include/dma-uclass.h | 78 ++++++++++++++++++++ include/dma.h | 174 ++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 439 insertions(+), 8 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1b92c7789d..21b2c0dcaa 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -12,6 +12,13 @@ config DMA buses that is used to transfer data to and from memory. The uclass interface is defined in include/dma.h. +config DMA_CHANNELS + bool "Enable DMA channels support" + depends on DMA + help + Enable channels support for DMA. Some DMA controllers have multiple + channels which can either transfer data to/from different devices. + config TI_EDMA3 bool "TI EDMA3 driver" help diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c index 6fd4e1b35d..f4ba883b12 100644 --- a/drivers/dma/dma-uclass.c +++ b/drivers/dma/dma-uclass.c @@ -1,24 +1,200 @@ /* * Direct Memory Access U-Class driver * - * (C) Copyright 2015 - * Texas Instruments Incorporated, - * - * Author: Mugunthan V N + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 Texas Instruments Incorporated + * Written by Mugunthan V N * * SPDX-License-Identifier: GPL-2.0+ */ #include #include -#include -#include +#include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_DMA_CHANNELS +static inline struct dma_ops *dma_dev_ops(struct udevice *dev) +{ + return (struct dma_ops *)dev->driver->ops; +} + +# if CONFIG_IS_ENABLED(OF_CONTROL) +# if CONFIG_IS_ENABLED(OF_PLATDATA) +int dma_get_by_index_platdata(struct udevice *dev, int index, + struct phandle_1_arg *cells, struct dma *dma) +{ + int ret; + + if (index != 0) + return -ENOSYS; + ret = uclass_get_device(UCLASS_DMA, 0, &dma->dev); + if (ret) + return ret; + dma->id = cells[0].id; + + return 0; +} +# else +static int dma_of_xlate_default(struct dma *dma, + struct ofnode_phandle_args *args) +{ + debug("%s(dma=%p)\n", __func__, dma); + + if (args->args_count > 1) { + pr_err("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + dma->id = args->args[0]; + else + dma->id = 0; + + return 0; +} + +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *dev_dma; + const struct dma_ops *ops; + + debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma); + + assert(dma); + dma->dev = NULL; + + ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index, + &args); + if (ret) { + pr_err("%s: dev_read_phandle_with_args failed: err=%d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, &dev_dma); + if (ret) { + pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n", + __func__, ret); + return ret; + } + + dma->dev = dev_dma; + + ops = dma_dev_ops(dev_dma); + + if (ops->of_xlate) + ret = ops->of_xlate(dma, &args); + else + ret = dma_of_xlate_default(dma, &args); + if (ret) { + pr_err("of_xlate() failed: %d\n", ret); + return ret; + } + + return dma_request(dev_dma, dma); +} +# endif /* OF_PLATDATA */ + +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma) +{ + int index; + + debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma); + dma->dev = NULL; + + index = dev_read_stringlist_search(dev, "dma-names", name); + if (index < 0) { + pr_err("dev_read_stringlist_search() failed: %d\n", index); + return index; + } + + return dma_get_by_index(dev, index, dma); +} +# endif /* OF_CONTROL */ + +int dma_request(struct udevice *dev, struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dev); + + debug("%s(dev=%p, dma=%p)\n", __func__, dev, dma); + + dma->dev = dev; + + if (!ops->request) + return 0; + + return ops->request(dma); +} + +int dma_free(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->free) + return 0; + + return ops->free(dma); +} + +int dma_enable(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->enable) + return -ENOSYS; + + return ops->enable(dma); +} + +int dma_disable(struct dma *dma) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->disable) + return -ENOSYS; + + return ops->disable(dma); +} + +int dma_receive(struct dma *dma, void **dst) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->receive) + return -1; + + return ops->receive(dma, dst); +} + +int dma_send(struct dma *dma, void *src, size_t len) +{ + struct dma_ops *ops = dma_dev_ops(dma->dev); + + debug("%s(dma=%p)\n", __func__, dma); + + if (!ops->send) + return -1; + + return ops->send(dma, src, len); +} +#endif /* CONFIG_DMA_CHANNELS */ + int dma_get_device(u32 transfer_type, struct udevice **devp) { struct udevice *dev; diff --git a/include/dma-uclass.h b/include/dma-uclass.h index 3429f65ec4..b334adb68b 100644 --- a/include/dma-uclass.h +++ b/include/dma-uclass.h @@ -13,6 +13,8 @@ #include +struct ofnode_phandle_args; + /* * struct dma_ops - Driver model DMA operations * @@ -20,6 +22,82 @@ * driver model. */ struct dma_ops { +#ifdef CONFIG_DMA_CHANNELS + /** + * of_xlate - Translate a client's device-tree (OF) DMA specifier. + * + * The DMA core calls this function as the first step in implementing + * a client's dma_get_by_*() call. + * + * If this function pointer is set to NULL, the DMA core will use a + * default implementation, which assumes #dma-cells = <1>, and that + * the DT cell contains a simple integer DMA Channel. + * + * At present, the DMA API solely supports device-tree. If this + * changes, other xxx_xlate() functions may be added to support those + * other mechanisms. + * + * @dma: The dma struct to hold the translation result. + * @args: The dma specifier values from device tree. + * @return 0 if OK, or a negative error code. + */ + int (*of_xlate)(struct dma *dma, + struct ofnode_phandle_args *args); + /** + * request - Request a translated DMA. + * + * The DMA core calls this function as the second step in + * implementing a client's dma_get_by_*() call, following a successful + * xxx_xlate() call, or as the only step in implementing a client's + * dma_request() call. + * + * @dma: The DMA struct to request; this has been filled in by + * a previoux xxx_xlate() function call, or by the caller of + * dma_request(). + * @return 0 if OK, or a negative error code. + */ + int (*request)(struct dma *dma); + /** + * free - Free a previously requested dma. + * + * This is the implementation of the client dma_free() API. + * + * @dma: The DMA to free. + * @return 0 if OK, or a negative error code. + */ + int (*free)(struct dma *dma); + /** + * enable() - Enable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*enable)(struct dma *dma); + /** + * disable() - Disable a DMA Channel. + * + * @dma: The DMA Channel to manipulate. + * @return zero on success, or -ve error code. + */ + int (*disable)(struct dma *dma); + /** + * receive() - Receive a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @dst: The destination pointer. + * @return zero on success, or -ve error code. + */ + int (*receive)(struct dma *dma, void **dst); + /** + * send() - Send a DMA transfer. + * + * @dma: The DMA Channel to manipulate. + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @return zero on success, or -ve error code. + */ + int (*send)(struct dma *dma, void *src, size_t len); +#endif /* CONFIG_DMA_CHANNELS */ /** * transfer() - Issue a DMA transfer. The implementation must * wait until the transfer is done. diff --git a/include/dma.h b/include/dma.h index 89320f10d9..bf8123fa9e 100644 --- a/include/dma.h +++ b/include/dma.h @@ -1,6 +1,7 @@ /* - * (C) Copyright 2015 - * Texas Instruments Incorporated, + * Copyright (C) 2018 Álvaro Fernández Rojas + * Copyright (C) 2015 Texas Instruments Incorporated + * Written by Mugunthan V N * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,6 +9,9 @@ #ifndef _DMA_H_ #define _DMA_H_ +#include +#include + /* * enum dma_direction - dma transfer direction indicator * @DMA_MEM_TO_MEM: Memcpy mode @@ -37,6 +41,172 @@ struct dma_dev_priv { u32 supported; }; +#ifdef CONFIG_DMA_CHANNELS +/** + * A DMA is a feature of computer systems that allows certain hardware + * subsystems to access main system memory, independent of the CPU. + * DMA channels are typically generated externally to the HW module + * consuming them, by an entity this API calls a DMA provider. This API + * provides a standard means for drivers to enable and disable DMAs, and to + * copy, send and receive data using DMA. + * + * A driver that implements UCLASS_DMA is a DMA provider. A provider will + * often implement multiple separate DMAs, since the hardware it manages + * often has this capability. dma_uclass.h describes the interface which + * DMA providers must implement. + * + * DMA consumers/clients are the HW modules driven by the DMA channels. This + * header file describes the API used by drivers for those HW modules. + */ + +struct udevice; + +/** + * struct dma - A handle to (allowing control of) a single DMA. + * + * Clients provide storage for DMA handles. The content of the structure is + * managed solely by the DMA API and DMA drivers. A DMA struct is + * initialized by "get"ing the DMA struct. The DMA struct is passed to all + * other DMA APIs to identify which DMA channel to operate upon. + * + * @dev: The device which implements the DMA channel. + * @id: The DMA channel ID within the provider. + * + * Currently, the DMA API assumes that a single integer ID is enough to + * identify and configure any DMA channel for any DMA provider. If this + * assumption becomes invalid in the future, the struct could be expanded to + * either (a) add more fields to allow DMA providers to store additional + * information, or (b) replace the id field with an opaque pointer, which the + * provider would dynamically allocated during its .of_xlate op, and process + * during is .request op. This may require the addition of an extra op to clean + * up the allocation. + */ +struct dma { + struct udevice *dev; + /* + * Written by of_xlate. We assume a single id is enough for now. In the + * future, we might add more fields here. + */ + unsigned long id; +}; + +# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA) +struct phandle_1_arg; +int dma_get_by_index_platdata(struct udevice *dev, int index, + struct phandle_1_arg *cells, struct dma *dma); + +/** + * dma_get_by_index - Get/request a DMA by integer index. + * + * This looks up and requests a DMA. The index is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA indices to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @index: The index of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_index(struct udevice *dev, int index, struct dma *dma); + +/** + * dma_get_by_name - Get/request a DMA by name. + * + * This looks up and requests a DMA. The name is relative to the client + * device; each device is assumed to have n DMAs associated with it somehow, + * and this function finds and requests one of them. The mapping of client + * device DMA names to provider DMAs may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @name: The name of the DMA to request, within the client's list of + * DMA channels. + * @dma: A pointer to a DMA struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma); +# else +static inline int dma_get_by_index(struct udevice *dev, int index, + struct dma *dma) +{ + return -ENOSYS; +} + +static inline int dma_get_by_name(struct udevice *dev, const char *name, + struct dma *dma) +{ + return -ENOSYS; +} +# endif + +/** + * dma_request - Request a DMA by provider-specific ID. + * + * This requests a DMA using a provider-specific ID. Generally, this function + * should not be used, since dma_get_by_index/name() provide an interface that + * better separates clients from intimate knowledge of DMA providers. + * However, this function may be useful in core SoC-specific code. + * + * @dev: The DMA provider device. + * @dma: A pointer to a DMA struct to initialize. The caller must + * have already initialized any field in this struct which the + * DMA provider uses to identify the DMA channel. + * @return 0 if OK, or a negative error code. + */ +int dma_request(struct udevice *dev, struct dma *dma); + +/** + * dma_free - Free a previously requested DMA. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return 0 if OK, or a negative error code. + */ +int dma_free(struct dma *dma); + +/** + * dma_enable() - Enable (turn on) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_enable(struct dma *dma); + +/** + * dma_disable() - Disable (turn off) a DMA channel. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @return zero on success, or -ve error code. + */ +int dma_disable(struct dma *dma); + +/** + * dma_receive() - Receive a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @dst: The destination pointer. + * @return zero on success, or -ve error code. + */ +int dma_receive(struct dma *dma, void **dst); + +/** + * dma_send() - Send a DMA transfer. + * + * @dma: A DMA struct that was previously successfully requested by + * dma_request/get_by_*(). + * @src: The source pointer. + * @len: Length of the data to be sent (number of bytes). + * @return zero on success, or -ve error code. + */ +int dma_send(struct dma *dma, void *src, size_t len); +#endif /* CONFIG_DMA_CHANNELS */ + /* * dma_get_device - get a DMA device which supports transfer * type of transfer_type From patchwork Sat Mar 3 08:59:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 880998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Da7UZqqE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgC719mwz9sWS for ; Sat, 3 Mar 2018 20:01:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C4749C2205F; Sat, 3 Mar 2018 09:00:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6601FC22043; Sat, 3 Mar 2018 08:59:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BA7E3C21FB9; Sat, 3 Mar 2018 08:59:34 +0000 (UTC) Received: from mail-wr0-f194.google.com (mail-wr0-f194.google.com [209.85.128.194]) by lists.denx.de (Postfix) with ESMTPS id 1A2AAC21FCC for ; Sat, 3 Mar 2018 08:59:30 +0000 (UTC) Received: by mail-wr0-f194.google.com with SMTP id o76so12334230wrb.7 for ; Sat, 03 Mar 2018 00:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M7jGGflEB0o7L3C+Bd5L330SAhQ9j+ncPqjEtBtSNwc=; b=Da7UZqqE/WdjNt912Rf/XunxXf69jsT31YFIjt4hVxzfZ7LuRXUH1OVu0HyGeuLwZo fKfpe/2RZUf3FTRWjrfrvcwT64Nb5Q4lRABvXTtYMc9Nx6WiiDDzMn9oTFZztMBHcFiF dCiywxlnAU5oJhtK6RM1kKg4mjIqJXKyvn1L9ANXWQZxxHQZWhObl4jrotJUdl+JmaZv 6AO7wFwr/qNSgvI4hIQ4Cu72VlaT0LdFEF4vLEeeQp9nK0WPwIblvm9r9t0zQ2jYVkqY xeh9UI0IcMFdD1/+1jdWRlVcHy96YGmDl7tvCxLT9prh4ZTyL9q8IhLQANuA82ErlFIq maVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M7jGGflEB0o7L3C+Bd5L330SAhQ9j+ncPqjEtBtSNwc=; b=flUyoPH+zvE8HbWQLHsqI8fO4uSXHpjHIMUVPN1f1QlApTPn1yTdcn4ioOkSwCetyF EFiXbrXRUFifvBZCeFB2ESD/9Znl74tfcslW2QXM/wscIBUJAuCEzNin1TbiFIbdQH3j IxIe+yT2OPzMGlay7JElWnmln7CVqnThsOr+E/AcKFvg1WjG2F2Rh8iWscQgKEaPVGVA yHiWizFXvoXvxgNzxasyTcVDv1lQNtou/8SjIlZnusEpZH7agpDqRdp4seK0J2a8HwMo KcSEs8B7WtlnmCclH84Tqry77jC8F9DvNAu8xFekiYYRvPgFk71w/Kh8gmgYyamBHSAI jgaw== X-Gm-Message-State: AElRT7G55trAMIQWisz4wi9k0SJlIKMdlT3FZ4B0u3xfKDE+0xHEVmE4 uxuUgALGfV0cVBui1xzUiyk3Ppbd X-Google-Smtp-Source: AG47ELuCAyvSjpTIR9xddQXcAOJa9XswO0AqziIx4L4TP+nM0NVWSSpRdb+tqaCpFJEiBlCePngEAQ== X-Received: by 10.223.225.3 with SMTP id d3mr3026712wri.56.1520067569102; Sat, 03 Mar 2018 00:59:29 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:28 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:05 +0100 Message-Id: <20180303085917.8293-4-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 03/15] dma: add bcm6348-iudma support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs. Signed-off-by: Álvaro Fernández Rojas --- v4: Fix issues reported by Grygorii Strashko and other fixes: - Remove usage of net_rx_packets as buffer. - Allocate dynamic rx buffer. - Check dma errors and discard invalid packets. v3: no changes v2: Fix dma rx burst config and select DMA_CHANNELS. drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/bcm6348-iudma.c | 545 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 555 insertions(+) create mode 100644 drivers/dma/bcm6348-iudma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 21b2c0dcaa..9afa158b51 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -19,6 +19,15 @@ config DMA_CHANNELS Enable channels support for DMA. Some DMA controllers have multiple channels which can either transfer data to/from different devices. +config BCM6348_IUDMA + bool "BCM6348 IUDMA driver" + depends on ARCH_BMIPS + select DMA_CHANNELS + help + Enable the BCM6348 IUDMA driver. + This driver support data transfer from devices to + memory and from memory to devices. + config TI_EDMA3 bool "TI EDMA3 driver" help diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 39b78b2a3d..b2b4147349 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DMA) += dma-uclass.o obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o +obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o obj-$(CONFIG_TI_EDMA3) += ti-edma3.o diff --git a/drivers/dma/bcm6348-iudma.c b/drivers/dma/bcm6348-iudma.c new file mode 100644 index 0000000000..d88345e45c --- /dev/null +++ b/drivers/dma/bcm6348-iudma.c @@ -0,0 +1,545 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/dma/bcm63xx-iudma.c: + * Copyright (C) 2015 Simon Arlott + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon + * + * Derived from bcm963xx_4.12L.06B_consumer/shared/opensource/include/bcm963xx/63268_map_part.h: + * Copyright (C) 2000-2010 Broadcom Corporation + * + * Derived from bcm963xx_4.12L.06B_consumer/bcmdrivers/opensource/net/enet/impl4/bcmenet.c: + * Copyright (C) 2010 Broadcom Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DMA_RX_DESC 4 +#define DMA_TX_DESC 1 + +DECLARE_GLOBAL_DATA_PTR; + +#define ALIGN_END_ADDR(type, ptr, size) \ + ((unsigned long)(ptr) + roundup((size) * sizeof(type), \ + ARCH_DMA_MINALIGN)) + +/* DMA Channels */ +#define DMA_CHAN_FLOWC(x) ((x) >> 1) +#define DMA_CHAN_FLOWC_MAX 8 +#define DMA_CHAN_MAX 16 +#define DMA_CHAN_SIZE 0x10 +#define DMA_CHAN_TOUT 500 + +/* DMA Global Configuration register */ +#define DMA_CFG_REG 0x00 +#define DMA_CFG_ENABLE_SHIFT 0 +#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT) +#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1) +#define DMA_CFG_NCHANS_SHIFT 24 +#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT) + +/* DMA Global Flow Control Threshold registers */ +#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_THR_LO_SHIFT 0 +#define DMA_FLOWC_THR_LO_MASK (5 << DMA_FLOWC_THR_LO_SHIFT) + +#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_THR_HI_SHIFT 0 +#define DMA_FLOWC_THR_HI_MASK (10 << DMA_FLOWC_THR_HI_SHIFT) + +/* DMA Global Flow Control Buffer Allocation registers */ +#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c) +#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31 +#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT) + +/* DMA Global Reset register */ +#define DMA_RST_REG 0x34 +#define DMA_RST_CHAN_SHIFT 0 +#define DMA_RST_CHAN_MASK(x) (1 << x) + +/* DMA Channel Configuration register */ +#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) +#define DMAC_CFG_ENABLE_SHIFT 0 +#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT) +#define DMAC_CFG_PKT_HALT_SHIFT 1 +#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT) +#define DMAC_CFG_BRST_HALT_SHIFT 2 +#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT) + +/* DMA Channel Interrupts registers */ +#define DMAC_IR_ST_REG(x) (DMA_CHAN_SIZE * (x) + 0x04) +#define DMAC_IR_EN_REG(x) (DMA_CHAN_SIZE * (x) + 0x08) + +#define DMAC_IR_DONE_SHIFT 2 +#define DMAC_IR_DONE_MASK (1 << DMAC_IR_DONE_SHIFT) + +/* DMA Channel Max Burst Length register */ +#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) +#define DMAC_BURST_MAX_SHIFT 0 +#define DMAC_BURST_MAX_MASK (16 << DMAC_BURST_MAX_SHIFT) + +/* DMA SRAM Descriptor Ring Start register */ +#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00) + +/* DMA SRAM State/Bytes done/ring offset register */ +#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08) + +/* DMA SRAM Buffer Descriptor status and length register */ +#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c) + +struct bcm6348_dma_desc { + uint16_t length; + + uint16_t status; +#define DMAD_ST_OV_ERR_SHIFT 0 +#define DMAD_ST_OV_ERR_MASK (1 << DMAD_ST_OV_ERR_SHIFT) +#define DMAD_ST_CRC_ERR_SHIFT 1 +#define DMAD_ST_CRC_ERR_MASK (1 << DMAD_ST_CRC_ERR_SHIFT) +#define DMAD_ST_RX_ERR_SHIFT 2 +#define DMAD_ST_RX_ERR_MASK (1 << DMAD_ST_RX_ERR_SHIFT) +#define DMAD_ST_OS_ERR_SHIFT 4 +#define DMAD_ST_OS_ERR_MASK (1 << DMAD_ST_OS_ERR_SHIFT) +#define DMAD_ST_CRC_SHIFT 8 +#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT) +#define DMAD_ST_UN_ERR_SHIFT 9 +#define DMAD_ST_UN_ERR_MASK (1 << DMAD_ST_UN_ERR_SHIFT) +#define DMAD_ST_WRAP_SHIFT 12 +#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT) +#define DMAD_ST_SOP_SHIFT 13 +#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT) +#define DMAD_ST_EOP_SHIFT 14 +#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT) +#define DMAD_ST_OWN_SHIFT 15 +#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT) + +#define DMAD_ST_ERR_MASK (DMAD_ST_OV_ERR_MASK | \ + DMAD_ST_CRC_ERR_MASK | \ + DMAD_ST_RX_ERR_MASK | \ + DMAD_ST_OS_ERR_MASK | \ + DMAD_ST_UN_ERR_MASK) + + uint32_t address; +} __attribute__((aligned(1))); + +struct bcm6348_chan_priv { + void __iomem *dma_buff; + void __iomem *dma_ring; + uint8_t dma_ring_size; + uint8_t desc_id; +}; + +struct bcm6348_iudma_priv { + void __iomem *base; + void __iomem *chan; + void __iomem *sram; + struct bcm6348_chan_priv **ch_priv; + uint8_t n_channels; +}; + +static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch) +{ + return !(ch & 1); +} + +static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv, + uint8_t ch) +{ + unsigned int timeout = DMA_CHAN_TOUT; + + /* disable dma channel interrupts */ + writel_be(0, priv->chan + DMAC_IR_EN_REG(ch)); + + do { + uint32_t cfg, halt; + + if (timeout > DMA_CHAN_TOUT / 2) + halt = DMAC_CFG_PKT_HALT_MASK; + else + halt = DMAC_CFG_BRST_HALT_MASK; + + /* try to stop dma channel */ + writel_be(halt, priv->chan + DMAC_CFG_REG(ch)); + mb(); + + /* check if channel was stopped */ + cfg = readl_be(priv->chan + DMAC_CFG_REG(ch)); + if (!(cfg & DMAC_CFG_ENABLE_MASK)) + break; + + udelay(1); + } while (--timeout); + + if (!timeout) + pr_err("unable to stop channel %u\n", ch); + + /* reset dma channel */ + setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); + mb(); + clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch)); +} + +static int bcm6348_iudma_disable(struct dma *dma) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + + bcm6348_iudma_chan_stop(priv, dma->id); + + if (bcm6348_iudma_chan_is_rx(dma->id)) + writel_be(DMA_FLOWC_ALLOC_FORCE_MASK, + DMA_FLOWC_ALLOC_REG(dma->id)); + + return 0; +} + +static int bcm6348_iudma_enable(struct dma *dma) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc; + void __iomem *dma_buff = ch_priv->dma_buff; + uint8_t i; + + /* init dma rings */ + dma_desc = ch_priv->dma_ring; + for (i = 0; i < ch_priv->dma_ring_size; i++) { + if (bcm6348_iudma_chan_is_rx(dma->id)) { + dma_desc->status = DMAD_ST_OWN_MASK; + dma_desc->length = PKTSIZE_ALIGN; + dma_desc->address = virt_to_phys(dma_buff); + dma_buff += PKTSIZE_ALIGN; + } else { + dma_desc->status = 0; + dma_desc->length = 0; + dma_desc->address = 0; + } + + if (i == ch_priv->dma_ring_size - 1) + dma_desc->status |= DMAD_ST_WRAP_MASK; + + if (bcm6348_iudma_chan_is_rx(dma->id)) + writel_be(1, + priv->base + DMA_FLOWC_ALLOC_REG(dma->id)); + + dma_desc++; + } + + /* init to first descriptor */ + ch_priv->desc_id = 0; + + /* force cache writeback */ + flush_dcache_range((ulong)ch_priv->dma_ring, + ALIGN_END_ADDR(struct bcm6348_dma_desc, ch_priv->dma_ring, + ch_priv->dma_ring_size)); + + /* clear sram */ + writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id)); + writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id)); + + /* set dma ring start */ + writel_be(virt_to_phys(ch_priv->dma_ring), + priv->sram + DMAS_RSTART_REG(dma->id)); + + /* set flow control */ + if (bcm6348_iudma_chan_is_rx(dma->id)) { + u32 val; + + setbits_be32(priv->base + DMA_CFG_REG, + DMA_CFG_FLOWC_ENABLE(dma->id)); + + val = ch_priv->dma_ring_size / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id)); + + val = (ch_priv->dma_ring_size * 2) / 3; + writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id)); + } + + /* set dma max burst */ + writel_be(ch_priv->dma_ring_size, + priv->chan + DMAC_BURST_REG(dma->id)); + + /* clear interrupts */ + writel_be(DMAC_IR_DONE_MASK, priv->chan + DMAC_IR_ST_REG(dma->id)); + writel_be(0, priv->chan + DMAC_IR_EN_REG(dma->id)); + + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK); + + return 0; +} + +static int bcm6348_iudma_request(struct dma *dma) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv; + + /* check if channel is valid */ + if (dma->id >= priv->n_channels) + return -ENODEV; + + /* alloc channel private data */ + priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv)); + if (!priv->ch_priv[dma->id]) + return -ENOMEM; + ch_priv = priv->ch_priv[dma->id]; + + /* alloc dma ring */ + if (bcm6348_iudma_chan_is_rx(dma->id)) + ch_priv->dma_ring_size = DMA_RX_DESC; + else + ch_priv->dma_ring_size = DMA_TX_DESC; + + ch_priv->dma_ring = + malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) * + ch_priv->dma_ring_size); + if (!ch_priv->dma_ring) + return -ENOMEM; + + if (bcm6348_iudma_chan_is_rx(dma->id)) { + ch_priv->dma_buff = + malloc_cache_aligned(PKTSIZE_ALIGN * + ch_priv->dma_ring_size); + if (!ch_priv->dma_buff) + return -ENOMEM; + } else { + ch_priv->dma_buff = NULL; + } + + return 0; +} + +static int bcm6348_iudma_receive(struct dma *dma, void **dst) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc; + void __iomem *dma_buff; + int ret; + + /* get dma ring descriptor address */ + dma_desc = ch_priv->dma_ring; + dma_desc += ch_priv->desc_id; + + /* invalidate cache data */ + invalidate_dcache_range((ulong)dma_desc, + ALIGN_END_ADDR(struct bcm6348_dma_desc, dma_desc, 1)); + + /* check dma own */ + if (dma_desc->status & DMAD_ST_OWN_MASK) + return -EAGAIN; + + /* check pkt */ + if (!(dma_desc->status & DMAD_ST_EOP_MASK) || + !(dma_desc->status & DMAD_ST_SOP_MASK) || + (dma_desc->status & DMAD_ST_ERR_MASK)) { + pr_err("invalid pkt received (ch=%ld)\n", dma->id); + ret = -EAGAIN; + } else { + uint16_t length; + + /* get dma buff descriptor address */ + dma_buff = phys_to_virt(dma_desc->address); + + /* invalidate cache data */ + invalidate_dcache_range((ulong)dma_buff, + (ulong)(dma_buff + PKTSIZE_ALIGN)); + + /* remove crc */ + length = dma_desc->length - 4; + + /* copy data */ + memcpy(*dst, dma_buff, length); + + ret = length; + } + + /* reinit dma descriptor */ + dma_desc->length = PKTSIZE_ALIGN; + dma_desc->status = (dma_desc->status & DMAD_ST_WRAP_MASK) | + DMAD_ST_OWN_MASK; + + /* flush cache */ + flush_dcache_range((ulong)dma_desc, + ALIGN_END_ADDR(struct bcm6348_dma_desc, dma_desc, 1)); + + /* set flow control buffer alloc */ + writel_be(1, priv->base + DMA_FLOWC_ALLOC_REG(dma->id)); + + /* enable dma */ + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK); + + /* set interrupt */ + writel_be(DMAC_IR_DONE_MASK, priv->chan + DMAC_IR_EN_REG(dma->id)); + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->dma_ring_size; + + return ret; +} + +static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len) +{ + struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev); + struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id]; + struct bcm6348_dma_desc *dma_desc; + uint16_t val; + + /* get dma ring descriptor address */ + dma_desc = ch_priv->dma_ring; + dma_desc += ch_priv->desc_id; + + dma_desc->address = virt_to_phys(src); + + /* config dma descriptor */ + val = (DMAD_ST_OWN_MASK | + DMAD_ST_EOP_MASK | + DMAD_ST_CRC_MASK | + DMAD_ST_SOP_MASK); + if (ch_priv->desc_id == ch_priv->dma_ring_size - 1) + val |= DMAD_ST_WRAP_MASK; + + dma_desc->length = len; + dma_desc->status = val; + + /* flush cache */ + flush_dcache_range((ulong)src, (ulong)src + PKTSIZE_ALIGN); + + /* flush cache */ + flush_dcache_range((ulong)dma_desc, + ALIGN_END_ADDR(struct bcm6348_dma_desc, dma_desc, 1)); + + /* enable dma */ + setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK); + + /* set interrupt */ + writel_be(DMAC_IR_DONE_MASK, priv->chan + DMAC_IR_EN_REG(dma->id)); + + /* poll dma status */ + do { + /* invalidate cache */ + invalidate_dcache_range((ulong)dma_desc, + ALIGN_END_ADDR(struct bcm6348_dma_desc, dma_desc, 1)); + + if (!(dma_desc->status & DMAD_ST_OWN_MASK)) + break; + } while(1); + + /* increment dma descriptor */ + ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->dma_ring_size; + + return 0; +} + +static const struct dma_ops bcm6348_iudma_ops = { + .disable = bcm6348_iudma_disable, + .enable = bcm6348_iudma_enable, + .request = bcm6348_iudma_request, + .receive = bcm6348_iudma_receive, + .send = bcm6348_iudma_send, +}; + +static const struct udevice_id bcm6348_iudma_ids[] = { + { .compatible = "brcm,bcm6348-iudma", }, + { /* sentinel */ } +}; + +static int bcm6348_iudma_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct bcm6348_iudma_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + uint8_t ch; + int i; + + uc_priv->supported = DMA_SUPPORTS_DEV_TO_MEM | + DMA_SUPPORTS_MEM_TO_DEV; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + if (clk_enable(&clk)) + pr_err("failed to enable clock %d\n", i); + clk_free(&clk); + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + if (reset_deassert(&reset)) + pr_err("failed to deassert reset %d\n", i); + reset_free(&reset); + } + + /* dma global base address */ + addr = devfdt_get_addr_name(dev, "dma"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->base = ioremap(addr, 0); + + /* dma channels base address */ + addr = devfdt_get_addr_name(dev, "dma-channels"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->chan = ioremap(addr, 0); + + /* dma sram base address */ + addr = devfdt_get_addr_name(dev, "dma-sram"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->sram = ioremap(addr, 0); + + /* disable dma controller */ + clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + /* get number of channels */ + priv->n_channels = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), + "dma-channels", 8); + if (priv->n_channels > DMA_CHAN_MAX) + return -EINVAL; + + /* alloc channel private data pointers */ + priv->ch_priv = calloc(priv->n_channels, + sizeof(struct bcm6348_chan_priv*)); + if (!priv->ch_priv) + return -ENOMEM; + + /* stop dma channels */ + for (ch = 0; ch < priv->n_channels; ch++) + bcm6348_iudma_chan_stop(priv, ch); + + /* enable dma controller */ + setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK); + + return 0; +} + +U_BOOT_DRIVER(bcm6348_iudma) = { + .name = "bcm6348_iudma", + .id = UCLASS_DMA, + .of_match = bcm6348_iudma_ids, + .ops = &bcm6348_iudma_ops, + .priv_auto_alloc_size = sizeof(struct bcm6348_iudma_priv), + .probe = bcm6348_iudma_probe, +}; From patchwork Sat Mar 3 08:59:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 880997 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cKd9mvog"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgBL1cvrz9sWS for ; Sat, 3 Mar 2018 20:00:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D4FD8C22077; Sat, 3 Mar 2018 09:00:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 44D2DC22031; Sat, 3 Mar 2018 08:59:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AAB9CC21FDF; Sat, 3 Mar 2018 08:59:34 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id B63B3C22020 for ; Sat, 3 Mar 2018 08:59:30 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id v65so12319841wrc.11 for ; Sat, 03 Mar 2018 00:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rtxpFYH5KmdONDdb+nGIJqBHF7VEnHD+Yw9izSFhgSA=; b=cKd9mvogRELmWVv1oFjEnutgK0u4qFMMhBnsAOd5N0Zwt5lnVXW761eufUIwrMzlub xBeeDcsA2/zfdRiII9asHlUMhKIkwblw7HKYu0W2GJ58V8hpWFspHH2+UZgqk0z0+dnw 0ujMBm/OC6b71gx5P59tNa6RmR7/39PUHwpMKbeArydWVsoTxji7wDp4o/SM2jKVP75n gMNyEmdgXhBjmmAWHsp8xosrYAC/y7NnpoqYtBLMI8GwTPI6L0vYu9n15pnIQegMcdpL DCiGqzeb/leJs5gsWIdQ/HnMDNVGYIJgS/k8TEPuzTdToDJEf1cVlYxM4pBEw0CgFkoP wG3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rtxpFYH5KmdONDdb+nGIJqBHF7VEnHD+Yw9izSFhgSA=; b=rFQ1PrRcmN2VJsAdHDkunLXRxLeOLfjC0RXRI+zrdM/TZb4eWLU6vQNeM/Vg0CUVbU X166+3c+Pxb3AuIuSKpsX2wlXuzh7OZWKhTcfzf6liBLE0I84J7QzZRbPaOqqQCyC1Z0 geN8Q/m7ZoFObfRsEVvJ4yuDAoGll2CDUn/oJ10f8TLmvn5Srh+s4bNLE/Hon+7KfTVH ezxDj5jmy0dLaVUXN7wVSbPNbAu+OMjrPKWd9NX2C4mRzKKA4Qyw2gvXdAkywAefYSUP xEXtpIBjKvkjPcLiD/fOoIt+bZ9noj3jW8yXFlGS3jgYi55JUgiL0HG0fLssl5THwqaT 75EQ== X-Gm-Message-State: APf1xPDHWsSYYVFlnquv+MlTiH9/jBkGFjqWPKIM1XJwNjWpUGvd9SQS 70sUEdK2uGkIaP3QpzlwuW53Xlj0 X-Google-Smtp-Source: AG47ELv9iZccCn1oFAGayE9ufuWIAOWN9Ow5Oxtzn5TY2zLgRnNVWI6jHoZOTC9hmSqCaFoncrHZVg== X-Received: by 10.223.130.194 with SMTP id 60mr7601927wrc.209.1520067570182; Sat, 03 Mar 2018 00:59:30 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:29 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:06 +0100 Message-Id: <20180303085917.8293-5-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 04/15] bmips: bcm6338: add bcm6348-iudma support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6338.dtsi | 14 ++++++++++++++ include/dt-bindings/dma/bcm6338-dma.h | 15 +++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/dt-bindings/dma/bcm6338-dma.h diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index 0cab44cb8d..4125f71d9f 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -131,5 +132,18 @@ reg = <0xfffe3100 0x38>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@fffe2400 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe2400 0x1c>, + <0xfffe2500 0x60>, + <0xfffe2600 0x60>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <6>; + resets = <&periph_rst BCM6338_RST_DMAMEM>; + }; }; }; diff --git a/include/dt-bindings/dma/bcm6338-dma.h b/include/dt-bindings/dma/bcm6338-dma.h new file mode 100644 index 0000000000..5dd66239b4 --- /dev/null +++ b/include/dt-bindings/dma/bcm6338-dma.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_DMA_BCM6338_H +#define __DT_BINDINGS_DMA_BCM6338_H + +#define BCM6338_DMA_ENET_RX 0 +#define BCM6338_DMA_ENET_TX 1 + +#endif /* __DT_BINDINGS_DMA_BCM6338_H */ From patchwork Sat Mar 3 08:59:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881005 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GOxRZ1qR"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgJR1Sj9z9s8f for ; Sat, 3 Mar 2018 20:06:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C05B8C22040; Sat, 3 Mar 2018 09:03:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AA1DDC2206A; Sat, 3 Mar 2018 09:00:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 46A05C21FA4; Sat, 3 Mar 2018 08:59:35 +0000 (UTC) Received: from mail-wr0-f194.google.com (mail-wr0-f194.google.com [209.85.128.194]) by lists.denx.de (Postfix) with ESMTPS id AE181C2202A for ; Sat, 3 Mar 2018 08:59:31 +0000 (UTC) Received: by mail-wr0-f194.google.com with SMTP id u49so12318428wrc.10 for ; Sat, 03 Mar 2018 00:59:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tEqnl+bhjKay+awyeNVpsnZtCu95IBsJrSfz1m3onOA=; b=GOxRZ1qRsX7blPx7+H4PDy/zjtJ2lMyx7yNok6gMNuw1xoM79MZajfSnNPBw9Za561 jzQWFEyiOCRHkqo/cKwyqib18Uzj5h9dFRnl7n6GqxLwAifOlBmJazMWq0Ih5tdCi6KH YtagAxa8nbltTU5BxonkJpI/+U6rAh26XmCI8y55F711Nilol6ahSpUWoq0mrDj5DxsS scLmJptEeS1CgOtRxIfLXsE233VpX6vYF/0H2RIt4p1kQUO/0Jo5LEcJkv8cfnTvWgZP OjEBoxOSLW1uc7T7dhBES+vHI4UNUC0DMc2AS44nDoRRR14H9bWJz7a/cwVEbPDAyKlj yGgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tEqnl+bhjKay+awyeNVpsnZtCu95IBsJrSfz1m3onOA=; b=Su5QfizFQMdSrAq30ZoaVduhPmTxzKSZjP7Ha9qN5z+yD36IPC/fiupsvS0tS+lYdY ovNlS3/BPzFyspX9R8NtYgF/Knh6EuMEKieAB2fil3DZ/oJBoEw/5RqK6Z3vCna6NsGG vwj2HuUXQWBb8PKngX+JbxOpi4GuNvCozPWYlWJrshti7P5ZXOMKl4l+Ma1L7OTD9GQJ P1Rtlu3eRk7smIMAyni3Nx4aUy9dZPA5RqE/uvG1C66L5x9XoDLaC9foqGNzVuD2NERe C8VUIIIUQAbunV+9RLZR4pQp6FhKLUrrtsEI9MfWsWoa9icKs1+0QKcRGs+EPFGe1eaB 5ocQ== X-Gm-Message-State: APf1xPChhAHj6nSaD9sy/a7hjpoydA9w2ts/yWTkMZ6eWheXZe9cbS1r ntzEryTt0jLXJUXOcK80FfY61VdT X-Google-Smtp-Source: AG47ELsBE2apip1KUnBDFNpBVsVmzBo6z8rQJuGMyS2qXs6Uue9vG1yHVboeMZIP0/ccY0dmsEH54g== X-Received: by 10.223.192.74 with SMTP id c10mr7698628wrf.145.1520067571192; Sat, 03 Mar 2018 00:59:31 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:30 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:07 +0100 Message-Id: <20180303085917.8293-6-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 05/15] bmips: bcm6348: add bcm6348-iudma support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6348.dtsi | 16 ++++++++++++++++ include/dt-bindings/dma/bcm6348-dma.h | 17 +++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 include/dt-bindings/dma/bcm6348-dma.h diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index 92fb91afc1..d774c59665 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -160,5 +161,20 @@ reg = <0xfffe2300 0x38>; u-boot,dm-pre-reloc; }; + + iudma: dma-controller@fffe7000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe7000 0x1c>, + <0xfffe7100 0x40>, + <0xfffe7200 0x40>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&periph_clk BCM6348_CLK_ENET>; + resets = <&periph_rst BCM6348_RST_ENET>, + <&periph_rst BCM6348_RST_DMAMEM>; + }; }; }; diff --git a/include/dt-bindings/dma/bcm6348-dma.h b/include/dt-bindings/dma/bcm6348-dma.h new file mode 100644 index 0000000000..a1d3a6456d --- /dev/null +++ b/include/dt-bindings/dma/bcm6348-dma.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_DMA_BCM6348_H +#define __DT_BINDINGS_DMA_BCM6348_H + +#define BCM6348_DMA_ENET0_RX 0 +#define BCM6348_DMA_ENET0_TX 1 +#define BCM6348_DMA_ENET1_RX 2 +#define BCM6348_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6348_H */ From patchwork Sat Mar 3 08:59:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881010 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ThsVxA/8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgKz5xWFz9s8f for ; Sat, 3 Mar 2018 20:07:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7C482C21FEC; Sat, 3 Mar 2018 09:02:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7458AC22046; Sat, 3 Mar 2018 08:59:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6C430C21FBE; Sat, 3 Mar 2018 08:59:36 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id D8422C22017 for ; Sat, 3 Mar 2018 08:59:32 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id z12so12344208wrg.4 for ; Sat, 03 Mar 2018 00:59:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u2y935al9jyvzRAaDiw1mcQ7Gf+Bf5+cMfDF6t+RpNI=; b=ThsVxA/8hgpjyd8eUMW0FH+RJTpkFtbeMvmrjRdkhZRLA06ucF40QuiCAbt/6FyjL6 Gneiks9cqdHtRvG0S5altOePws2vwtfgKFnanOh8Uf3NDNKaoDp7Bbs7VnUVmzXIfDAi U9RGFx/QZiMhEhmqujkMRxnfcd0n3+b7OjWzcxfiFsF/uVhv/KzhHZKnOyB4cA6Wrgmj RmZZmJhRlXkOBfJQwEfX26fPMu4QHR2rzJlbEpkjZj9WM52/IapXXakvkZcwMqqPqUl3 5VB5L/OU+xmZQviJ3WMUWs9vnyMRQxIJt9Ua1QC/iNK1oLMx4WT97R9iu4vNhJOhHRW2 zSDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u2y935al9jyvzRAaDiw1mcQ7Gf+Bf5+cMfDF6t+RpNI=; b=gOf9Fsb45c0qoG1TLNSDDcLx7VImkw7zXYb1h713GouI6pP2OSic6hAL3WJEaRDt7M Z4X+kooyc//zONzc3WsI4ICyyrBWdo7zjvNZHGZ/TbQJ7rE/HXZB/sqJb+5wcWERsnkq gEsozF5d/yv+pD+Arsjx3XW4q+/mRwtQ1k3LC0nY+FMIWWodS9v3cothxcWiNQ2/kNiL OHpGc2Jw4pWHiFQpLPrzGAWRRVAwH8xV7lUZBvE+ffrsZoZ66sqNqWlaHT5mJABg5ow+ z4ckiiB2DQhhmKC1HGpHiETz6DPZZ49pMNiKvw/jY/6iIdgjftkLUUoeE0IWDU1cPBsQ nklA== X-Gm-Message-State: APf1xPAbWtB5JuOFbV05ZVDWZp6iJOAJ2WZk4ZAGzP8n15ne6uI5ZI7z p2bUvrJpfatSYlJ2V3i1x4eOW8Lz X-Google-Smtp-Source: AG47ELvIJf05J9M1W8kUjhzVTfsXQjBXyQzwIs3ZYmeEp1LmhrEXoXiKGeXlXK4y1bRj1ukY8pqabg== X-Received: by 10.223.195.204 with SMTP id d12mr7419096wrg.116.1520067572209; Sat, 03 Mar 2018 00:59:32 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:31 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:08 +0100 Message-Id: <20180303085917.8293-7-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 06/15] bmips: bcm6358: add bcm6348-iudma support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6358.dtsi | 18 ++++++++++++++++++ include/dt-bindings/dma/bcm6358-dma.h | 17 +++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 include/dt-bindings/dma/bcm6358-dma.h diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index b63b53baee..1468e4f63a 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include "skeleton.dtsi" @@ -191,5 +192,22 @@ status = "disabled"; }; + + iudma: dma-controller@fffe5000 { + compatible = "brcm,bcm6348-iudma"; + reg = <0xfffe5000 0x24>, + <0xfffe5100 0x80>, + <0xfffe5200 0x80>; + reg-names = "dma", + "dma-channels", + "dma-sram"; + #dma-cells = <1>; + dma-channels = <8>; + clocks = <&periph_clk BCM6358_CLK_EMUSB>, + <&periph_clk BCM6358_CLK_USBSU>, + <&periph_clk BCM6358_CLK_EPHY>; + resets = <&periph_rst BCM6358_RST_ENET>, + <&periph_rst BCM6358_RST_EPHY>; + }; }; }; diff --git a/include/dt-bindings/dma/bcm6358-dma.h b/include/dt-bindings/dma/bcm6358-dma.h new file mode 100644 index 0000000000..3b1fcf8540 --- /dev/null +++ b/include/dt-bindings/dma/bcm6358-dma.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_DMA_BCM6358_H +#define __DT_BINDINGS_DMA_BCM6358_H + +#define BCM6358_DMA_ENET0_RX 0 +#define BCM6358_DMA_ENET0_TX 1 +#define BCM6358_DMA_ENET1_RX 2 +#define BCM6358_DMA_ENET1_TX 3 + +#endif /* __DT_BINDINGS_DMA_BCM6358_H */ From patchwork Sat Mar 3 08:59:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881001 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CZlJz2uf"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgFQ03NYz9sWS for ; Sat, 3 Mar 2018 20:03:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8FFB4C21FEC; Sat, 3 Mar 2018 09:01:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8D20CC21F9F; Sat, 3 Mar 2018 08:59:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2BEACC21FF4; Sat, 3 Mar 2018 08:59:37 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id EBC19C22022 for ; Sat, 3 Mar 2018 08:59:33 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id p104so12326841wrc.12 for ; Sat, 03 Mar 2018 00:59:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7zKr6VmnwLz8gIbH4eXmptxV9ETq/sbOssBf4tHvhA0=; b=CZlJz2ufr1DCU4p+7+ZZGBj10+TWnXLL10MuHGn14EW6OsCe8n71Hkn2GK11WK8X97 fCnFIDfm2BwK33wZt4XODYL2f9hBa98ZP/XJAvPkMFqEU+meswVHqOHqQC9ZZdwDIVM2 6lNWI68hs4lpo75g/JLkVL4RgkZMThlnuFmqIsdf8GHIJD6/mTeDSOeR6HK0UeiByn6U yy+XLNLxITRHh17VL9oMZAZ8Ja3r1VfCLQOvdcAg2RwKxzANQkFxXhcvO8A2e3yRaAEL ebHKr8K4iMoIXRW8zM3sODvSv/sFRbjovOycfW/qgW84BpDk22iOTlzH3V7pjig7kt+v uuMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7zKr6VmnwLz8gIbH4eXmptxV9ETq/sbOssBf4tHvhA0=; b=RBe2voUX1/Psn+ePuBhqA87a+A6HEg6bJNcQKdo8ussJ2sHnPxjAU7lttiCN+tl3wg kxY/Fvdaed0rQ8GAjSO6IzvONkQQgP8QtH+7O5gY/YctjWmBg2QG2vTp45r1TVW0Vf3P vELwN1/HKTPukTb9cZiIOrUpxhaO6mOeVWIWHUA2oOZqNWiZrYetloaU33dP0Txzo9Xv JjCVZHHGUTMg6FJlglsRjOgfj5aJ7lZbuDwblpmCXmf4AXrGrvydrm/QyuheO1xnHA9y bqK07WaH72MQSouS+/jRXCHn3DnngM19MXYBXsZ9xCmaxMDZ+BUh43Egbh6miKAkeird UqSQ== X-Gm-Message-State: APf1xPDP0CCw++0RjXtew5F2TSGhJPQnt3vPHiVacPAwh8pyPuVcn5Ml juGV9qPj7QNPk+y4vLb8UbAhLR8v X-Google-Smtp-Source: AG47ELvyNz+iUqBN+m5vNwF1mTbvgJXyRUMeEr0wvOXiJMpjpQroCw1IajMeerEIm3qN75xuJYr4WQ== X-Received: by 10.223.177.194 with SMTP id r2mr7619952wra.89.1520067573460; Sat, 03 Mar 2018 00:59:33 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:32 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:09 +0100 Message-Id: <20180303085917.8293-8-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 07/15] phy: add support for internal phys X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes include/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/phy.h b/include/phy.h index 0543ec10c2..8f3e53db01 100644 --- a/include/phy.h +++ b/include/phy.h @@ -50,6 +50,7 @@ typedef enum { + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_SGMII, @@ -72,6 +73,7 @@ typedef enum { } phy_interface_t; static const char *phy_interface_strings[] = { + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_MII] = "mii", [PHY_INTERFACE_MODE_GMII] = "gmii", [PHY_INTERFACE_MODE_SGMII] = "sgmii", From patchwork Sat Mar 3 08:59:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Hy/kZqGL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgH52rnpz9sWS for ; Sat, 3 Mar 2018 20:05:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B620CC21FC0; Sat, 3 Mar 2018 09:03:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4782BC22088; Sat, 3 Mar 2018 09:00:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2D2FAC22059; Sat, 3 Mar 2018 08:59:39 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 6C6A8C21FE2 for ; Sat, 3 Mar 2018 08:59:35 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id l43so12364252wrc.2 for ; Sat, 03 Mar 2018 00:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o7KjFOzNAGGPn75B/3wzYR99DB1OUl5t3jKhpKKMttw=; b=Hy/kZqGLMHS/6Ojp27DBKDd/CeXP2Ysy6y94RAlILeWSt80fZCaHwIuBuV30MzcvnT Z/lYJ3IRTYp+OSTDpt59G3faood+1wmk4O/Z75U3B34mJMB7CgOwfKOXpvLb5dEHlYGP 2rHDSYMjSXl+NRWSCoKzA6cYhLiIMUL1KE3w5NhRgQDMgt+KWIlZbBVZ2pr8AxsnEXJT PxGewPslDznoCtcgvU+VXpk6uhNjgxQfHJ2H2SQm8h1HLCxg5pzzxjoW+/YzPx/7aKG/ LcdE5qKmT8c5RpLwfSJUXTbynfhsRDJEoBSW/HfC0tygCHOtOekzTBI4a/9i9cxv5aMF TOQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o7KjFOzNAGGPn75B/3wzYR99DB1OUl5t3jKhpKKMttw=; b=NgUuu5nw29xAK8V4WvbWsq/mGZnuNv1KChziugOoDYaV2dClKill9YybR3zPczg6na HQuw0UNlxujIOBttGNVjYOHNUaeXAlTDzHZPyeIy7UDZb87EBgYliRAUeBja6bbpdUUG RGME81vlZrPfdn86nxk6v7yxsjjBnzb9hp32Fp59gUsirzUx7xh+f7SQQXNO6gAVzKaI ENY95ObEyAEzkICKq9f8wu1tTssG01LNR8ttYGT2RCfYfA4rHvNxbU6s053wfP+KXOUI 0tUvyQHHG8SfaMf3INmQQsqWBn9D0YwPwBUSb3Z4Yl/xVMFJIO8/V5qP3lNeTbDJqHrS fgUw== X-Gm-Message-State: APf1xPD5CcNu3Gpop2GknNtzY0khbohYLdl1rLi1Gg5Y3ehYbUzu8336 c1t3cq6RQngZQegQ8CLsjGcNM9DW X-Google-Smtp-Source: AG47ELt2MEsDo4leEqgpJnPq/6QwXVmVKx72EsZqoCWy2HXirNe03yhz7TtdhKWQRRwk8DH6coBQUg== X-Received: by 10.223.133.214 with SMTP id 22mr7524254wru.130.1520067574514; Sat, 03 Mar 2018 00:59:34 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:33 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:10 +0100 Message-Id: <20180303085917.8293-9-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 08/15] net: add support for bcm6348-enet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: Fix issues reported by Grygorii Strashko and other fixes: - Copy received dma buffer to net_rx_packets in order to avoid possible dma overwrites. - Reset dma rx channel when sending a new packet to prevent flow control issues. - Fix packet casting on bcm6348_eth_recv/send. v3: no changes v2: select DMA_CHANNELS. drivers/net/Kconfig | 10 + drivers/net/Makefile | 1 + drivers/net/bcm6348-eth.c | 530 +++++++++++++++++++++++++++++++++++++++++ include/configs/bmips_common.h | 5 +- 4 files changed, 545 insertions(+), 1 deletion(-) create mode 100644 drivers/net/bcm6348-eth.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index de1947ccc1..e532332d78 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -71,6 +71,16 @@ config BCM_SF2_ETH_GMAC by the BCM_SF2_ETH driver. Say Y to any bcmcygnus based platforms. +config BCM6348_ETH + bool "BCM6348 EMAC support" + depends on DM_ETH && ARCH_BMIPS + select DMA + select DMA_CHANNELS + select MII + select PHYLIB + help + This driver supports the BCM6348 Ethernet MAC. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index ac5443c752..282adbc775 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o +obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o diff --git a/drivers/net/bcm6348-eth.c b/drivers/net/bcm6348-eth.c new file mode 100644 index 0000000000..4f729373ee --- /dev/null +++ b/drivers/net/bcm6348-eth.c @@ -0,0 +1,530 @@ +/* + * Copyright (C) 2018 Álvaro Fernández Rojas + * + * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c: + * Copyright (C) 2008 Maxime Bizon + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ETH_ZLEN 60 + +#define ETH_TX_WATERMARK 32 +#define ETH_MAX_MTU_SIZE 1518 + +#define ETH_TIMEOUT 100 + +/* ETH Receiver Configuration register */ +#define ETH_RXCFG_REG 0x00 +#define ETH_RXCFG_ENFLOW_SHIFT 5 +#define ETH_RXCFG_ENFLOW_MASK (1 << ETH_RXCFG_ENFLOW_SHIFT) + +/* ETH Receive Maximum Length register */ +#define ETH_RXMAXLEN_REG 0x04 +#define ETH_RXMAXLEN_SHIFT 0 +#define ETH_RXMAXLEN_MASK (0x7ff << ETH_RXMAXLEN_SHIFT) + +/* ETH Transmit Maximum Length register */ +#define ETH_TXMAXLEN_REG 0x08 +#define ETH_TXMAXLEN_SHIFT 0 +#define ETH_TXMAXLEN_MASK (0x7ff << ETH_TXMAXLEN_SHIFT) + +/* MII Status/Control register */ +#define MII_SC_REG 0x10 +#define MII_SC_MDCFREQDIV_SHIFT 0 +#define MII_SC_MDCFREQDIV_MASK (0x7f << MII_SC_MDCFREQDIV_SHIFT) +#define MII_SC_PREAMBLE_EN_SHIFT 7 +#define MII_SC_PREAMBLE_EN_MASK (1 << MII_SC_PREAMBLE_EN_SHIFT) + +/* MII Data register */ +#define MII_DAT_REG 0x14 +#define MII_DAT_DATA_SHIFT 0 +#define MII_DAT_DATA_MASK (0xffff << MII_DAT_DATA_SHIFT) +#define MII_DAT_TA_SHIFT 16 +#define MII_DAT_TA_MASK (0x3 << MII_DAT_TA_SHIFT) +#define MII_DAT_REG_SHIFT 18 +#define MII_DAT_REG_MASK (0x1f << MII_DAT_REG_SHIFT) +#define MII_DAT_PHY_SHIFT 23 +#define MII_DAT_PHY_MASK (0x1f << MII_DAT_PHY_SHIFT) +#define MII_DAT_OP_SHIFT 28 +#define MII_DAT_OP_WRITE (0x5 << MII_DAT_OP_SHIFT) +#define MII_DAT_OP_READ (0x6 << MII_DAT_OP_SHIFT) + +/* ETH Interrupts Mask register */ +#define ETH_IRMASK_REG 0x18 + +/* ETH Interrupts register */ +#define ETH_IR_REG 0x1c +#define ETH_IR_MII_SHIFT 0 +#define ETH_IR_MII_MASK (1 << ETH_IR_MII_SHIFT) + +/* ETH Control register */ +#define ETH_CTL_REG 0x2c +#define ETH_CTL_ENABLE_SHIFT 0 +#define ETH_CTL_ENABLE_MASK (1 << ETH_CTL_ENABLE_SHIFT) +#define ETH_CTL_DISABLE_SHIFT 1 +#define ETH_CTL_DISABLE_MASK (1 << ETH_CTL_DISABLE_SHIFT) +#define ETH_CTL_RESET_SHIFT 2 +#define ETH_CTL_RESET_MASK (1 << ETH_CTL_RESET_SHIFT) +#define ETH_CTL_EPHY_SHIFT 3 +#define ETH_CTL_EPHY_MASK (1 << ETH_CTL_EPHY_SHIFT) + +/* ETH Transmit Control register */ +#define ETH_TXCTL_REG 0x30 +#define ETH_TXCTL_FD_SHIFT 0 +#define ETH_TXCTL_FD_MASK (1 << ETH_TXCTL_FD_SHIFT) + +/* ETH Transmit Watermask register */ +#define ETH_TXWMARK_REG 0x34 +#define ETH_TXWMARK_WM_SHIFT 0 +#define ETH_TXWMARK_WM_MASK (0x3f << ETH_TXWMARK_WM_SHIFT) + +/* MIB Control register */ +#define MIB_CTL_REG 0x38 +#define MIB_CTL_RDCLEAR_SHIFT 0 +#define MIB_CTL_RDCLEAR_MASK (1 << MIB_CTL_RDCLEAR_SHIFT) + +/* ETH Perfect Match registers */ +#define ETH_PM_CNT 4 +#define ETH_PML_REG(x) (0x58 + (x) * 0x8) +#define ETH_PMH_REG(x) (0x5c + (x) * 0x8) +#define ETH_PMH_VALID_SHIFT 16 +#define ETH_PMH_VALID_MASK (1 << ETH_PMH_VALID_SHIFT) + +/* MIB Counters registers */ +#define MIB_REG_CNT 55 +#define MIB_REG(x) (0x200 + (x) * 4) + +/* ETH data */ +struct bcm6348_eth_priv { + void __iomem *base; + uint8_t rx_desc; + /* DMA */ + struct dma rx_dma; + struct dma tx_dma; + /* PHY */ + int phy_id; + struct phy_device *phy_dev; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static void bcm6348_eth_mac_disable(struct bcm6348_eth_priv *priv) +{ + /* disable emac */ + clrsetbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK, + ETH_CTL_DISABLE_MASK); + + /* wait until emac is disabled */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_DISABLE_MASK, false, + ETH_TIMEOUT, false)) + pr_err("error disabling emac\n"); +} + +static void bcm6348_eth_mac_enable(struct bcm6348_eth_priv *priv) +{ + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_ENABLE_MASK); +} + +static void bcm6348_eth_mac_reset(struct bcm6348_eth_priv *priv) +{ + /* reset emac */ + writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG); + wmb(); + + /* wait until emac is reset */ + if (wait_for_bit_be32(priv->base + ETH_CTL_REG, + ETH_CTL_RESET_MASK, false, + ETH_TIMEOUT, false)) + pr_err("error resetting emac\n"); +} + +static int bcm6348_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + int ret; + + *packetp = net_rx_packets[priv->rx_desc]; + ret = dma_receive(&priv->rx_dma, (void **)packetp); + if (ret > 0) + priv->rx_desc = (priv->rx_desc + 1) % PKTBUFSRX; + + return ret; +} + +static int bcm6348_eth_send(struct udevice *dev, void *packet, int length) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* reset dma rx channel */ + dma_disable(&priv->rx_dma); + dma_enable(&priv->rx_dma); + + length = max(length, ETH_ZLEN); + + return dma_send(&priv->tx_dma, (void *)packet, length); +} + +static int bcm6348_eth_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* mac duplex parameters */ + if (phydev->duplex) + setbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + else + clrbits_be32(priv->base + ETH_TXCTL_REG, ETH_TXCTL_FD_MASK); + + /* rx flow control (pause frame handling) */ + if (phydev->pause) + setbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + else + clrbits_be32(priv->base + ETH_RXCFG_REG, + ETH_RXCFG_ENFLOW_MASK); + + return 0; +} + +static int bcm6348_eth_start(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + int ret, i; + + priv->rx_desc = 0; + + /* enable dma rx channel */ + dma_enable(&priv->rx_dma); + + /* enable dma tx channel */ + dma_enable(&priv->tx_dma); + + ret = phy_startup(priv->phy_dev); + if (ret) { + pr_err("could not initialize phy\n"); + return ret; + } + + if (!priv->phy_dev->link) { + pr_err("no phy link\n"); + return -EIO; + } + + bcm6348_eth_adjust_link(dev, priv->phy_dev); + + /* zero mib counters */ + for (i = 0; i < MIB_REG_CNT; i++) + writel_be(0, MIB_REG(i)); + + /* enable rx flow control */ + setbits_be32(priv->base + ETH_RXCFG_REG, ETH_RXCFG_ENFLOW_MASK); + + /* set max rx/tx length */ + writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) & + ETH_RXMAXLEN_MASK, priv->base + ETH_RXMAXLEN_REG); + writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) & + ETH_TXMAXLEN_MASK, priv->base + ETH_TXMAXLEN_REG); + + /* set correct transmit fifo watermark */ + writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) & + ETH_TXWMARK_WM_MASK, priv->base + ETH_TXWMARK_REG); + + /* enable emac */ + bcm6348_eth_mac_enable(priv); + + /* clear interrupts */ + writel_be(0, priv->base + ETH_IRMASK_REG); + + return 0; +} + +static void bcm6348_eth_stop(struct udevice *dev) +{ + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + + /* disable dma rx channel */ + dma_disable(&priv->rx_dma); + + /* disable dma tx channel */ + dma_disable(&priv->tx_dma); + + /* disable emac */ + bcm6348_eth_mac_disable(priv); +} + +static int bcm6348_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + bool running = false; + + /* check if emac is running */ + if (readl_be(priv->base + ETH_CTL_REG) & ETH_CTL_ENABLE_MASK) + running = true; + + /* disable emac */ + if (running) + bcm6348_eth_mac_disable(priv); + + /* set mac address */ + writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 | + (pdata->enetaddr[4]) << 8 | (pdata->enetaddr[5]), + priv->base + ETH_PML_REG(0)); + writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) | + ETH_PMH_VALID_MASK, priv->base + ETH_PMH_REG(0)); + + /* enable emac */ + if (running) + bcm6348_eth_mac_enable(priv); + + return 0; +} + +static const struct eth_ops bcm6348_eth_ops = { + .recv = bcm6348_eth_recv, + .send = bcm6348_eth_send, + .start = bcm6348_eth_start, + .stop = bcm6348_eth_stop, + .write_hwaddr = bcm6348_eth_write_hwaddr, +}; + +static const struct udevice_id bcm6348_eth_ids[] = { + { .compatible = "brcm,bcm6348-enet", }, + { /* sentinel */ } +}; + +static int bcm6348_mdio_op(void __iomem *base, uint32_t data) +{ + /* make sure mii interrupt status is cleared */ + writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG); + + /* issue mii op */ + writel_be(data, base + MII_DAT_REG); + + /* wait until emac is disabled */ + return wait_for_bit_be32(base + ETH_IR_REG, + ETH_IR_MII_MASK, true, + ETH_TIMEOUT, false); +} + +static int bcm6348_mdio_read(struct mii_dev *bus, int addr, int devaddr, + int reg) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_READ; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + val = readl_be(base + MII_DAT_REG) & MII_DAT_DATA_MASK; + val >>= MII_DAT_DATA_SHIFT; + + return val; +} + +static int bcm6348_mdio_write(struct mii_dev *bus, int addr, int dev_addr, + int reg, u16 value) +{ + void __iomem *base = bus->priv; + uint32_t val; + + val = MII_DAT_OP_WRITE; + val |= (reg << MII_DAT_REG_SHIFT) & MII_DAT_REG_MASK; + val |= (0x2 << MII_DAT_TA_SHIFT) & MII_DAT_TA_MASK; + val |= (addr << MII_DAT_PHY_SHIFT) & MII_DAT_PHY_MASK; + val |= (value << MII_DAT_DATA_SHIFT) & MII_DAT_DATA_MASK; + + if (bcm6348_mdio_op(base, val)) { + pr_err("%s: timeout\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int bcm6348_mdio_init(const char *name, void __iomem *base) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + pr_err("%s: failed to allocate MDIO bus\n", __func__); + return -ENOMEM; + } + + bus->read = bcm6348_mdio_read; + bus->write = bcm6348_mdio_write; + bus->priv = base; + snprintf(bus->name, sizeof(bus->name), "%s", name); + + return mdio_register(bus); +} + +static int bcm6348_phy_init(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *bus; + + /* get mii bus */ + bus = miiphy_get_dev_by_name(dev->name); + + /* phy connect */ + priv->phy_dev = phy_connect(bus, priv->phy_id, dev, + pdata->phy_interface); + if (!priv->phy_dev) { + pr_err("%s: no phy device\n", __func__); + return -ENODEV; + } + + priv->phy_dev->supported = (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_Pause | + SUPPORTED_MII); + priv->phy_dev->advertising = priv->phy_dev->supported; + + /* phy config */ + phy_config(priv->phy_dev); + + return 0; +} + +static int bcm6348_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct bcm6348_eth_priv *priv = dev_get_priv(dev); + void *blob = (void *)gd->fdt_blob; + int node = dev_of_offset(dev); + const char *phy_mode; + fdt_addr_t addr; + int phy_node, ret, i; + + /* get base address */ + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + /* get phy mode */ + pdata->phy_interface = PHY_INTERFACE_MODE_NONE; + phy_mode = fdt_getprop(blob, node, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) + return -ENODEV; + + /* get phy */ + phy_node = fdtdec_lookup_phandle(blob, node, "phy"); + if (phy_node >= 0) + priv->phy_id = fdtdec_get_int(blob, phy_node, "reg", -1); + else + return -EINVAL; + + /* get dma channels */ + ret = dma_get_by_name(dev, "tx", &priv->tx_dma); + if (ret) + return -EINVAL; + + ret = dma_get_by_name(dev, "rx", &priv->rx_dma); + if (ret) + return -EINVAL; + + /* try to enable clocks */ + for (i = 0; ; i++) { + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, i, &clk); + if (ret < 0) + break; + if (clk_enable(&clk)) + pr_err("failed to enable clock %d\n", i); + clk_free(&clk); + } + + /* try to perform resets */ + for (i = 0; ; i++) { + struct reset_ctl reset; + int ret; + + ret = reset_get_by_index(dev, i, &reset); + if (ret < 0) + break; + if (reset_deassert(&reset)) + pr_err("failed to deassert reset %d\n", i); + reset_free(&reset); + } + + /* get base addr */ + priv->base = ioremap(addr, 0); + pdata->iobase = (phys_addr_t) priv->base; + + /* disable emac */ + bcm6348_eth_mac_disable(priv); + + /* reset emac */ + bcm6348_eth_mac_reset(priv); + + /* select correct mii interface */ + if (pdata->phy_interface == PHY_INTERFACE_MODE_INTERNAL) + clrbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + else + setbits_be32(priv->base + ETH_CTL_REG, ETH_CTL_EPHY_MASK); + + /* turn on mdc clock */ + writel_be((0x1f << MII_SC_MDCFREQDIV_SHIFT) | + MII_SC_PREAMBLE_EN_MASK, priv->base + MII_SC_REG); + + /* set mib counters to not clear when read */ + clrbits_be32(priv->base + MIB_CTL_REG, MIB_CTL_RDCLEAR_MASK); + + /* initialize perfect match registers */ + for (i = 0; i < ETH_PM_CNT; i++) { + writel_be(0, priv->base + ETH_PML_REG(i)); + writel_be(0, priv->base + ETH_PMH_REG(i)); + } + + /* init mii bus */ + ret = bcm6348_mdio_init(dev->name, priv->base); + if (ret) + return ret; + + /* init phy */ + ret = bcm6348_phy_init(dev); + if (ret) + return ret; + + return 0; +} + +U_BOOT_DRIVER(bcm6348_eth) = { + .name = "bcm6348_eth", + .id = UCLASS_ETH, + .of_match = bcm6348_eth_ids, + .ops = &bcm6348_eth_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .priv_auto_alloc_size = sizeof(struct bcm6348_eth_priv), + .probe = bcm6348_eth_probe, +}; diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 38bf7a272b..eb66512f67 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -7,6 +7,9 @@ #ifndef __CONFIG_BMIPS_COMMON_H #define __CONFIG_BMIPS_COMMON_H +/* ETH */ +#define CONFIG_PHY_RESET_DELAY 20 + /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } @@ -17,7 +20,7 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 From patchwork Sat Mar 3 08:59:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881008 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kwXj28UH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgKP1lZqz9sXK for ; Sat, 3 Mar 2018 20:07:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EE33CC22030; Sat, 3 Mar 2018 09:03:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CBDC4C22071; Sat, 3 Mar 2018 09:00:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6B153C22041; Sat, 3 Mar 2018 08:59:39 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 08954C22030 for ; Sat, 3 Mar 2018 08:59:36 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id u49so12318515wrc.10 for ; Sat, 03 Mar 2018 00:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ClV+hDXa69C87YaHIjSBFtCIarhVkfBRPSVPGiSaXmw=; b=kwXj28UHkQYOjYlGJmB4bzsbs6vcLOVkHH4fEy6lumjVIaHRk9nhtPvMsZLptcJPIg ZPmSzpIxc67vaDPYxN0avdvLpAfITaxB1vAulr4RkPExBmmQ0hlBUX3z9qQvw7jExieE CBs8Ak7OnQimUBSEhMjo59HVxjqMkxFH4prNaAWfOiUv7Ull33XFC4GvC/MXK2SY2r3k qdpDSx0grkkW50dRFX6NPl9YKMUKHy3BLsVoabphc9Rs1GX27Y+FAcWp4tRROtgk2+JN hayzAn0sIIIUP/UyOrJZ4lglr1C4hzg7bnSNZ4Bx3/EfybkhHRcAZiHIorDAfwLxOYXq ZuZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ClV+hDXa69C87YaHIjSBFtCIarhVkfBRPSVPGiSaXmw=; b=GSp+zd6Kais/gKlFX7+jpCeaIMTuJDMXZzSYCZu9FQSmzNHxkBuOREkQy2jl5/4qOR Z/nbP0WdJL5CoYpXtX541ITNnrsIiVD/ptwR/qZk+agqmIrYrG68/xAZ8yv2HLE7I2+j roBj/MtbCSBYCXEQ/SMg7PKM7skWEppdraCj6M2Hfy/EtI67ss2KLZMTUNDevtzFDmXU TCiQh3YfkAYBzDDPlMgtWexzufTJ7vqg7iinGnTOjZsGtXSSlQRjg1eX3RVb3p9Pwwkb NG399o2MbQR+hbfvaToVhSAKrhm7y+PLQ+R6Kv6dWZg5omGcUegpyhMEWaEaC5uLcjaE V8Lg== X-Gm-Message-State: APf1xPB8u06R17+kyyz7aeT/sTBNqdt9GOKldiXYggzQG0wSsV6LZ06H hb4bd04lQogIt077UqpgzsWdGLK7 X-Google-Smtp-Source: AG47ELumr6sFWhClHhJ7tugaISfAdSGrjyVGfjRoRap8vWD1znqa/4RcU8Ou0nI+ST96ODpsQGGwdA== X-Received: by 10.223.200.144 with SMTP id k16mr7654951wrh.282.1520067575540; Sat, 03 Mar 2018 00:59:35 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:34 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:11 +0100 Message-Id: <20180303085917.8293-10-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 09/15] bmips: bcm6338: add support for bcm6348-enet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6338.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi index 4125f71d9f..621278c9d1 100644 --- a/arch/mips/dts/brcm,bcm6338.dtsi +++ b/arch/mips/dts/brcm,bcm6338.dtsi @@ -145,5 +145,20 @@ dma-channels = <6>; resets = <&periph_rst BCM6338_RST_DMAMEM>; }; + + enet: ethernet@fffe2800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe2800 0x2dc>; + clocks = <&periph_clk BCM6338_CLK_ENET>; + resets = <&periph_rst BCM6338_RST_ENET>; + dmas = <&iudma BCM6338_DMA_ENET_RX>, + <&iudma BCM6338_DMA_ENET_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; }; }; From patchwork Sat Mar 3 08:59:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="f19S1uzO"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgL62ydBz9sXK for ; Sat, 3 Mar 2018 20:07:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2A36FC22052; Sat, 3 Mar 2018 09:02:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A9D1EC21FC5; Sat, 3 Mar 2018 09:00:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A86D8C22045; Sat, 3 Mar 2018 08:59:41 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id 0A417C22044 for ; Sat, 3 Mar 2018 08:59:37 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id p104so12326918wrc.12 for ; Sat, 03 Mar 2018 00:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rhBiPFphNyfJLk0FhdXTex+POxyQjgcrAFu1p6d1b68=; b=f19S1uzOGjEWic+fi/qfHB5LtOzibmRnnSHcR6G0H8SzeQyVHl9yP6cegpYPpZxTnn 8MjWoCzUFZFdUNhN8U0ue1e6q8o8XAs+y6B1l9ZAa2uR4ol9Q3iJAtp+JglLFBF+KdLI 90TCx2bVQMqG+MnZepVw3BeVOjPqUL//1ldSmcY/0G6SKkL6EPQxNMPo9MTUsJRr95z+ JkvGb7mdFYZ1whk4Ktru5zf58bxXgtg1EjDkPTo01GnW+Wpk+GMLpVOjmVCzAh13Njsc YOQyLheAjLjzeRiLtAHefSgKcERPoMOFia1rHaMbH+b1qNqHvt2xjWukoOYUoz+ypHqd opoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rhBiPFphNyfJLk0FhdXTex+POxyQjgcrAFu1p6d1b68=; b=Bw7kBibUUDqIZuPTAF7pbL85Zhihg/Un+3mlJFCNdSk4sdoC9Ujf3ZHQmnRjRkAzxP 2Ywjj1ulwOGPokGZEbaPysGTjYkhAbZCmVHTWD6qNeCdIUXJbrvASYpxeKsC3dD42QDr WOYNeGFNDyjHH0FxTnyy3iguQtndz1aSkjgzsC8a6RZkDnPB9Nok62x2/L0hLzflfIdi 4SjmLRiGlgfTuNMOWasMOGTJ4gcPAJ/+D6VI8SwrXv+Wo+P9/S36Xh7cM0Co05NtteTF BpOgqx7LLUZjYwE3e9Je4NCTOdCCBIVGgJsSwdLdVfdgCESOzahkZDUZlEQM4FUJrA/s jw4g== X-Gm-Message-State: APf1xPBl4Ohpq6E8FSLIrQfSdjQFmf11V5PPxS3jZaUYOlPeTEapcBGy AcIPJWpB5MH0vf2E/tf4nnQLCi5C X-Google-Smtp-Source: AG47ELvTOGKOgEzih3k5SisBRfQ1RLarEwtJMntaEWJi34fDpVYsmgFYZsCO5fS/0EGbYlhpQ8eGTw== X-Received: by 10.223.144.35 with SMTP id h32mr7563092wrh.2.1520067576529; Sat, 03 Mar 2018 00:59:36 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:35 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:12 +0100 Message-Id: <20180303085917.8293-11-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 10/15] bmips: enable f@st1704 enet support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/sagem,f@st1704.dts | 12 ++++++++++++ configs/sagem_f@st1704_ram_defconfig | 9 ++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/mips/dts/sagem,f@st1704.dts b/arch/mips/dts/sagem,f@st1704.dts index dd0e5b8b7c..99d031f10a 100644 --- a/arch/mips/dts/sagem,f@st1704.dts +++ b/arch/mips/dts/sagem,f@st1704.dts @@ -40,6 +40,18 @@ }; }; +&enet { + status = "okay"; + phy = <&enetphy>; + phy-mode = "mii"; + + enetphy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio { status = "okay"; }; diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index 0adcd46d51..1a640781b7 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -28,11 +28,15 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -# CONFIG_CMD_NET is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -41,6 +45,9 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set From patchwork Sat Mar 3 08:59:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 880999 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ErSkB0dZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgCt4m0Mz9sWS for ; Sat, 3 Mar 2018 20:02:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 629A5C21FD4; Sat, 3 Mar 2018 09:02:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6C9A8C21FDF; Sat, 3 Mar 2018 08:59:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 48A0DC2202F; Sat, 3 Mar 2018 08:59:42 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 213E3C21FC0 for ; Sat, 3 Mar 2018 08:59:38 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id n7so12336799wrn.5 for ; Sat, 03 Mar 2018 00:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BZLRRK29t86btP6eGKCXzoEJK4ZeABli0RGJvkFi28Y=; b=ErSkB0dZ++4kRooL4wiIKnkK/8nsksFHNkD/njn+/tTRAoub66yiR2CkG2131cFt+p zmTlsxCt2epl3Zgl3JAp5wHOoIGuUWvNpUOP5h5r5fcjzuixr7WWcLKu63lFZf4R/Yo1 k7pHLEaE82YrC7fkb41V/RVwgxGIym7omqkiuEBtak3Vxc68IXPFso3ubUVkkSXV/SX4 Db0MqPGBjv2dUUilUrKZl5tr071n0+CoCCYeE6TASm4eXZXbS8DLdN79Af5rsGYkjRlg xtHVQThy3p6EPQvte/tsHvinzsdPzXgy1E/yBz6+MNXxbEiCYJ6lJYDvZu2vjWwkGKDG ASNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BZLRRK29t86btP6eGKCXzoEJK4ZeABli0RGJvkFi28Y=; b=QV6jtD2zw1K3Pj9LcHHNbKpRxINOVCL8jSwKB1QXg+DUZ7C9ZK+0mzIxdfHO5wYwgp 4PKv6iu4jucKH4XNtCoVXgAYaAdW+QN5C7ZyPKXtQTYxvu4pfnoyJQ4By3jCerZpFA9l 0wktipTy1RkkK+4NntydoEker9/w5qmvD5xZ4fd5L/GwVwoH9ci/eHEsOHpYUiI5QB+O MBP1LdWZqrOLX0TxgJheN8Kbwm3uR1YV196D6VSpH655gEZFZ3LgJ/iZq4zCb6lH2DhK Fjk606PkIMdhmo1Oym2ZRqrjeIUEaJRNlsHKecBZtgPC0+tXWcPsbWctq7SHquGpbPZ2 aG2g== X-Gm-Message-State: APf1xPBRaZAR25KBJhNXN0BgAVSITYo3pz9o94G3JQiRYVUN6E3IUxyY bA6BKphRz+q2PVM44xGugjnA+iJd X-Google-Smtp-Source: AG47ELtIH0S9ZQJ0o2lDolN7PSYlC4h7YJDmROGhivJosX7xeyvt9rX4NdsFE690T/rUylUjpne63A== X-Received: by 10.223.171.13 with SMTP id q13mr7375297wrc.183.1520067577613; Sat, 03 Mar 2018 00:59:37 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:36 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:13 +0100 Message-Id: <20180303085917.8293-12-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 11/15] bmips: bcm6348: add support for bcm6348-enet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6348.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index d774c59665..e540865019 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -162,6 +162,32 @@ u-boot,dm-pre-reloc; }; + enet0: ethernet@fffe6000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6000 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET0_RX>, + <&iudma BCM6348_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe6800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe6800 0x2dc>; + dmas = <&iudma BCM6348_DMA_ENET1_RX>, + <&iudma BCM6348_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + iudma: dma-controller@fffe7000 { compatible = "brcm,bcm6348-iudma"; reg = <0xfffe7000 0x1c>, From patchwork Sat Mar 3 08:59:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881006 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YPRxgeWj"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgJq0WB6z9s8f for ; Sat, 3 Mar 2018 20:06:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A6DE9C2200F; Sat, 3 Mar 2018 09:04:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 52346C22020; Sat, 3 Mar 2018 09:00:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D4084C22041; Sat, 3 Mar 2018 08:59:43 +0000 (UTC) Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by lists.denx.de (Postfix) with ESMTPS id 2B15EC21F71 for ; Sat, 3 Mar 2018 08:59:39 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id q83so7200961wme.5 for ; Sat, 03 Mar 2018 00:59:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9XL3iGPn6Dd2th/gFvmz6dvvoKrX4frVdZo7bKQkTKw=; b=YPRxgeWjVz3Y1MzgEcpgAPhN7Gb31HerHPdrD5VLtx4Bco9p7bNFdyhFuLoaOdYJxi pMOD+nK+Mk12y/M7HJa0d4y9Ry7jhQARI6kiCXXA0KLQ36y9+ZLyhA/DPJStXN2WO/WL VWD/88/sZrTiq2Kuk0QDzAFmaXR0x6doHuTeIO/GKe+6nskwM+mT3AhyNOtAdS/HXqd2 2S23p0jpSx47ePNBH87thy/f/Dgq3XASEg1j/WV3CSxV/DvOWubXP3xMvb2kHltRu8os 1B4pdRaE1BGkgPbuxpk4Est+ChiqOdShN5Jvxid2NexaLDKqd0bgZVFj3XeStGp318sn MBMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9XL3iGPn6Dd2th/gFvmz6dvvoKrX4frVdZo7bKQkTKw=; b=gVO2Py5XQiOUfswrdV1SBNXTGhzvl+QLR+nC+WA7uh4YkeEHWPBBLBYJEFF+AjcpCP hZ0lINMb94G29i/rLq1LFtAxt509356UiJKDa+69yWGgRnYVX5HJ/Fnfu+X4qaO4i/Jz Ukb/yjOEjgis98ouuUYZ2R+U00Gs2UBtFR4bV/KvL8ii7QndIMLs4nR+UWAFTKDBPgvE NiTzF4b+1TDoyqlzYKF1M8KgKLsFf4VSeUePzDRl/z5L0bHot8L98u1t8yMUgx5Xp/ot ywx3EyWWeS3SExUH+nhSBWmCOIXR3jUDbTV2MKZFcmQnEJ2A1sjzaZIn50WsDUmpnaUN 1JhQ== X-Gm-Message-State: AElRT7EceggtCtodMF6+IcAU6KM0ObwJGKxZkdzOJrRVSc36h9f3yNFF m36UqeVgMO1oYZVl8rtXysitzAs1 X-Google-Smtp-Source: AG47ELscRhaRwoZm62heU9SEknVGvYkCNky+IXUuYbqk7a0Mefd6p5CwJcZOfWptJlhBqmuQNz0dPw== X-Received: by 10.28.230.147 with SMTP id e19mr3777742wmi.2.1520067578611; Sat, 03 Mar 2018 00:59:38 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:37 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:14 +0100 Message-Id: <20180303085917.8293-13-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 12/15] bmips: enable ct-5361 enet support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/comtrend,ct-5361.dts | 12 ++++++++++++ configs/comtrend_ct5361_ram_defconfig | 8 +++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts index 74dc09046c..a78aa877fc 100644 --- a/arch/mips/dts/comtrend,ct-5361.dts +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -35,6 +35,18 @@ }; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 8b842606f5..0737772dd2 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -26,11 +26,14 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y -# CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -38,6 +41,9 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6348_USBH_PHY=y CONFIG_DM_RESET=y From patchwork Sat Mar 3 08:59:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SkDmNIOI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgKY53XTz9s8f for ; Sat, 3 Mar 2018 20:07:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 68252C21F9F; Sat, 3 Mar 2018 09:05:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9AC3CC22060; Sat, 3 Mar 2018 09:00:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id ED3B7C21FBD; Sat, 3 Mar 2018 08:59:44 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id 320F6C2202F for ; Sat, 3 Mar 2018 08:59:40 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id w128so7224778wmw.0 for ; Sat, 03 Mar 2018 00:59:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZXOSywzEkvwsA+np9ocDfKqL9e9qpvV97qf3akTuwQo=; b=SkDmNIOIiP1HAhrxv/4HQ+L+vEGtXUau3IYSspivZ7QXQYU9izwLjw+KMjJ1UeHpXy oQX/bG/9Ad+uMql42CsPoJ+jXbaZIC2mKORWewxSTm7DdDdb+B6pW3m4BrR2TFk/JfiY 63gW/UKACLMBN1++DdM4RJ7D6gFwr4K4d8y40CTQBK8VBxG/Hb8ojxTJ+l+PGotkzTen A8U/KOAOVRqCEVTdXPKfK8ZUVM2nbFIheVJXuG8002RZTHX/53O62x6IxDkAhlu596k1 0x+MCYWxRP4oCa3pUHtf4VQM7S20iffK142U3DYoJfpHPdgNdUz8nMOf2SuJ0gPlCXsZ P4mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZXOSywzEkvwsA+np9ocDfKqL9e9qpvV97qf3akTuwQo=; b=Mzd3SkvEozSFvWfgE3NY3b5JltlRK7MpOiRcFBb8Oj1K4ZJVQB1McGDfuWADu2irai E/khJBxrijdUzgAF653CdaTByPVp5xzPVTJY/2CvdaoVwpwF7THn8H6I2CcDSWIEzUYE pu5cRZebewO1eoSKRfFLTDqEYq1q5Tj/kguBeHcwEGxbxltjk6mmwjmoOZhHgnAyvwHf 6RSA+nu4I0imFcT8Cy0u40gQvXFfNJkselpUYjcO8JN8dfaWXXpu1syRlZPPmR231WLM TtAdSURqmoblY1aOwzO4NVbsN/4Ju8pJKPr51CHswmnF1xfqISUDN/NXzwNe11eQ0gWN 0VUw== X-Gm-Message-State: AElRT7FMic8U8tq3qL12tTK1AmcSfiYvE8oEwb2DPI4Fuin/cwahYn+F bJFpEf3boO3oPh1AFUseWpRRsd15 X-Google-Smtp-Source: AG47ELsxzGYCmspS4ROdhmrJ1IKRcFQYyIX18DRkySZQLBZBscbk3oLVssqJGA0lrPDbonZABi2tCA== X-Received: by 10.28.29.209 with SMTP id d200mr3735724wmd.149.1520067579684; Sat, 03 Mar 2018 00:59:39 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:39 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:15 +0100 Message-Id: <20180303085917.8293-14-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 13/15] bmips: bcm6358: add support for bcm6348-enet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/brcm,bcm6358.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 1468e4f63a..04329864c2 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -193,6 +193,34 @@ status = "disabled"; }; + enet0: ethernet@fffe4000 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4000 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET0>; + dmas = <&iudma BCM6358_DMA_ENET0_RX>, + <&iudma BCM6358_DMA_ENET0_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + + enet1: ethernet@fffe4800 { + compatible = "brcm,bcm6348-enet"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe4800 0x2dc>; + clocks = <&periph_clk BCM6358_CLK_ENET1>; + dmas = <&iudma BCM6358_DMA_ENET1_RX>, + <&iudma BCM6358_DMA_ENET1_TX>; + dma-names = "rx", + "tx"; + + status = "disabled"; + }; + iudma: dma-controller@fffe5000 { compatible = "brcm,bcm6348-iudma"; reg = <0xfffe5000 0x24>, From patchwork Sat Mar 3 08:59:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881004 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="negj6ye8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgHv5hPqz9s8f for ; Sat, 3 Mar 2018 20:05:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7BA84C2202A; Sat, 3 Mar 2018 09:04:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 93FB2C2200F; Sat, 3 Mar 2018 09:00:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A6E8DC22064; Sat, 3 Mar 2018 08:59:44 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id 521B8C22017 for ; Sat, 3 Mar 2018 08:59:41 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id t6so6995222wmt.5 for ; Sat, 03 Mar 2018 00:59:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zfw3KeISHfT6UuwzbPS01huW+edE2DnVnFROQQAdSqQ=; b=negj6ye8zokiFlnfx0CAJ8xGdIrhvjE46AHsZA9d5Vkp3b2XyDhNszNTXj4z359ZYq aDxb2QS0jTsxtLSrrZImPo8x9Zpk4bS+yjqoumq68ZjWyAmUVr6RcMPexoowHd8ljYqS RCuiAyRhiJ5xoqbzT/r9OZrvQqGvM4bFLhXYEKUxAitPQehcoW7u3r/TOsQGsY2Dwwpd 4vILcMKpRjdVscOTFv/BiEG0kU0IUau2CaKt4uX8OTdSZiNBQn90IRoVStFVA+itwNPD ARkTLcjNWIPoe33sf+aKWDKaAhVJQRMun4TpVN+aMsMqWbPLqmOGCHFXglBA9MH39NRE Xc/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zfw3KeISHfT6UuwzbPS01huW+edE2DnVnFROQQAdSqQ=; b=I0DX+wiCMKg2OBooT+ARFXFVi4vmGavtP9tyink1z9RG+HY8lFZntU/S2W4RZayxFZ xKpIcQoi+Qv3ZtJLJDPleuhhTCcBj77NPRBb0CcLpJ4ZzY3KuP+In394oIcgEYlKuMR5 qmjn5fzGyjrvfMXsuPl3OfN0+N0ephBWYKacU8j6qnr/u/kmW+3172oyndV5dT67nIwc UCWzN2CqvIt/1qvgmx/56b/SUm36EQPqzCFPjXUzzQJHEy7Dh9xGJlMsZ/GLFC9TI56o 7e1WdTHMTipBsOuesdhgWJKEGCd2goP1YQxra7CWKkqT5WqsR94m2oUtLTxXWNN78RL0 rM1Q== X-Gm-Message-State: AElRT7HEADMDFo9ElSH929f824kDyDK7luCh8gKTe3aqLmP3POrAPU91 ADG3rgUZNvIrTQifdRkYcMoY/2Ue X-Google-Smtp-Source: AG47ELvXqap1uQzCPQSMXRooUJjJHdt2DlRoaLNa4rKkChfr/Mk5coaU/AyFqNKM5qPgislUuspMSQ== X-Received: by 10.28.13.136 with SMTP id 130mr3742590wmn.123.1520067580784; Sat, 03 Mar 2018 00:59:40 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:40 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:16 +0100 Message-Id: <20180303085917.8293-15-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 14/15] bmips: enable hg556a enet support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/huawei,hg556a.dts | 12 ++++++++++++ configs/huawei_hg556a_ram_defconfig | 8 +++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index a1e9c15ab9..2f99e0905c 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -94,6 +94,18 @@ status = "okay"; }; +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 7f7f34ed61..c7c7c6554f 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -26,11 +26,14 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y -# CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -38,6 +41,9 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y From patchwork Sat Mar 3 08:59:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 881007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="US7lRKJ7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ztgKN2jHMz9s8f for ; Sat, 3 Mar 2018 20:07:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 108F8C21FA4; Sat, 3 Mar 2018 09:04:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5DE01C22054; Sat, 3 Mar 2018 09:00:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 72B0DC22054; Sat, 3 Mar 2018 08:59:46 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 95508C21FCC for ; Sat, 3 Mar 2018 08:59:42 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id z12so12344390wrg.4 for ; Sat, 03 Mar 2018 00:59:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6ESXtaeBan2+GijkpsE43t3NNEljDR/FctjvZ/l3xIQ=; b=US7lRKJ7La2xGRElGeAq5fw3qhY5eL9sgo2Dm2g47hriXeNDH2uGYQcVq1mZSAqQ0W Rmanibh1G5JKSWGrtTZZM4ZXO7WG0CVnrBO1oxqJrDTMeZe76ezr8hIkLJd3j4BZLoQh GWs2Fx/gLYgW3+zzc1GGDw28WLBLQvLdSYkS9I/Mw43kj8A5YXyO1OQkXsHy45zm95uj 2fyYShcWOf4+cWe4aKAdekMOTo5KDj9Mxfa6uIz3fNJnHnVvw0tVu/MBX9O7D8cZD/8f AHSjTFlhopO0D/x7q3mvt7qb8Q/TQhHVltM2+8K2gnmXOXzcrCzNScUh7U979OZsXR5D w1LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6ESXtaeBan2+GijkpsE43t3NNEljDR/FctjvZ/l3xIQ=; b=dkrH025s3Vymh7U/u95MgQ7D1rSrw4H596YTwg9H2QE65DNqt/KK4F/wMg1bQ7wA4n GNedELTh0FRgDQbnuxkRpwy0CR4wNCL3pH4ZLvSu43rjjNXjbeLQAwovFwJ1Pxzakfqu T3jow0zjz0LbYl2iu7VH5f3kdSX71G1W8wPmax+bwEPJKCA55KqykGHOlnIxRUctyAef c/tbjNMNJ7c7CI6CwRNYtr69QJLgckLKkm7dlg2GajHbEde+OlgBvRBU4tvxcUJYahe3 DC5SHhVXdHWaMjlNzWvEJjceoSJ/I+yhLu25fxL9HLr9Uy550waDquqz12lblYgNSenC +WFg== X-Gm-Message-State: APf1xPAyC0jCzSp1f/TA0NhucKBTywemJwFi7eZFw1q7NoG/fO/QrFU1 Dmu295Y87yVHfvNwXIK0y/HRr99/ X-Google-Smtp-Source: AG47ELtdJ45dOoJ4mvOceXAC72xFD2gPy+YCBapdTVDUPPVNhjrdkbBgHn7qwKEeIPBgA9YqguuNEQ== X-Received: by 10.223.134.42 with SMTP id 39mr7591168wrv.10.1520067582089; Sat, 03 Mar 2018 00:59:42 -0800 (PST) Received: from skynet.lan (175.red-2-137-31.dynamicip.rima-tde.net. [2.137.31.175]) by smtp.gmail.com with ESMTPSA id w74sm4922292wmd.1.2018.03.03.00.59.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 00:59:41 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: u-boot@lists.denx.de, daniel.schwierzeck@gmail.com, sjg@chromium.org, jagan@openedev.com, vigneshr@ti.com, grygorii.strashko@ti.com Date: Sat, 3 Mar 2018 09:59:17 +0100 Message-Id: <20180303085917.8293-16-noltari@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180303085917.8293-1-noltari@gmail.com> References: <20180212163858.25601-1-noltari@gmail.com> <20180303085917.8293-1-noltari@gmail.com> MIME-Version: 1.0 Subject: [U-Boot] [RFC v4 15/15] bmips: enable nb4-ser enet support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Álvaro Fernández Rojas --- v4: no changes v3: no changes v2: no changes arch/mips/dts/sfr,nb4-ser.dts | 24 ++++++++++++++++++++++++ configs/sfr_nb4-ser_ram_defconfig | 8 +++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts index 473372faa1..73db45f9ea 100644 --- a/arch/mips/dts/sfr,nb4-ser.dts +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -54,6 +54,30 @@ status = "okay"; }; +&enet0 { + status = "okay"; + phy = <&enet0phy>; + phy-mode = "internal"; + + enet0phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + phy = <&enet1phy>; + phy-mode = "mii"; + + enet1phy: fixed-link { + reg = <1>; + speed = <100>; + full-duplex; + }; +}; + &gpio0 { status = "okay"; }; diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index fc323d879d..07b49a1a77 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -27,11 +27,14 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y -# CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y # CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_BCM6348_IUDMA=y CONFIG_DM_GPIO=y CONFIG_BCM6345_GPIO=y CONFIG_LED=y @@ -40,6 +43,9 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_BCM6348_ETH=y CONFIG_PHY=y CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y