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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id g194-20020a6252cb000000b00538505ff705sm6991522pfb.91.2022.08.31.23.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 23:06:08 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, pratyush@kernel.org, tudor.ambarus@microchip.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 1/4] mtd: spi-nor-core: Default to addr_width of 3 for configurable widths Date: Thu, 1 Sep 2022 15:05:30 +0900 Message-Id: <4b8388a9961cac4024647228f12a3da24b338081.1662011338.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on command." Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e3c86e080a..90d0f769f0 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2213,6 +2213,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, /* Number of address bytes. */ switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: + case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: nor->addr_width = 3; break; From patchwork Thu Sep 1 06:05:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Kuwano X-Patchwork-Id: 1672664 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=l+wFyPKA; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MJ9Xx2Ldqz1yhP for ; Thu, 1 Sep 2022 16:06:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 368F2849F2; Thu, 1 Sep 2022 08:06:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l+wFyPKA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8133D841AB; Thu, 1 Sep 2022 08:06:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CCAD4841AB for ; Thu, 1 Sep 2022 08:06:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tkuw584924@gmail.com Received: by mail-pl1-x62d.google.com with SMTP id f24so13407477plr.1 for ; Wed, 31 Aug 2022 23:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=xIoCAblP/SEXw6vSS8BwnxpOQs1LF4auaCKon0CC8X8=; b=l+wFyPKAXoNTDQicGtCsumCLvDY3HBYlUxupLhfa+AFg/VcV1lbsHDFP8ivQyc+1lS cl90ubP4l46TwBGu6OQYb0hIJ7kRBwV5jzuaJmliu1euU8xak2vKTASYc4xX+X/XbXm7 fVfLjsclZZnaqxTWmyztUO0P/YrQqwAz4Gpa7GgdPe72JjBzSswA5jgNPYshGENWNVl/ reKFPI5GvWGwEPtvLwFUPI7XJUO7X/pW5GSMzfwCX61TRL10i5mB64RbcOOz9tXPOaHS yLqW3POA18iJkqGFrjh1BeQNxJpNHqT0aAj/f4BvtzsPJQ2i9M5ARi8OjwHQijntlm22 yH9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=xIoCAblP/SEXw6vSS8BwnxpOQs1LF4auaCKon0CC8X8=; b=IRZy/ugXID/AnHYCpTWsPcKW1VbW5ar6V27yDZmKyzy5lbwSMiP0O+1kR7XmTsNqqa EuB5BDfgOB6PEf8zQ9g56ypBojPL4+xUFa+/Py2NH2PYhineYDyNbAf3iD1tkPSCcObl PDlz7+gNT5KIKvm0W+Scp9f4sXNHHUm7CBuzq4oPos7nTAF0AoJiex/4FirRUF4w5M5f LGLZVzqmbPsUVrQBQNbXfvyvbpa90ndy8AaNYnQ0n/H9G8hUU8ApBbb9QlXqbEzHUR9H xaGvCRKPzLxcPpwxeqOJldpfXnrzYGqbn0lOZXlDC+S6/IS/rS42oEliJRlvc82vq6s7 CBKA== X-Gm-Message-State: ACgBeo2OiyztOKgwvnFQ4eV/CFCKTwpebnKoZSX8246bxDmZfR5G00yO 6Qf6pPcxtordO1eBfTI3Dwl3q73sPCc= X-Google-Smtp-Source: AA6agR6MZnL5K1+DCmdV0ovUkntX8V4pii4OjZQaD3j5Ai3v2MTz9d/IDOf7mWNayS0QVqFFN+1Jzg== X-Received: by 2002:a17:902:b08b:b0:174:78b0:11cd with SMTP id p11-20020a170902b08b00b0017478b011cdmr23192058plr.124.1662012373121; Wed, 31 Aug 2022 23:06:13 -0700 (PDT) Received: from ISCNPF1JZGWX.infineon.com (KD106168128197.ppp-bb.dion.ne.jp. [106.168.128.197]) by smtp.gmail.com with ESMTPSA id g194-20020a6252cb000000b00538505ff705sm6991522pfb.91.2022.08.31.23.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 23:06:12 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, pratyush@kernel.org, tudor.ambarus@microchip.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 2/4] mtd: spi-nor-core: Track flash's internal address mode Date: Thu, 1 Sep 2022 15:05:31 +0900 Message-Id: <54c91e07a148730a6ecb34dcea2f323fa76c8975.1662011338.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano The nor->addr_width tracks number of address bytes used in read/program/erase ops and eventually set to 4 for >16MB chips, regardless of flash's internal address mode. For Infineon SEMPER flash's, we use Read/Write Any Register commands for configuration and status check. These commands take 3- or 4-byte address depending on flash's internal address mode. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 2 ++ include/linux/mtd/spi-nor.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 90d0f769f0..360fc9aff1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2215,10 +2215,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4: nor->addr_width = 3; + nor->addr_mode_nbytes = 3; break; case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: nor->addr_width = 4; + nor->addr_mode_nbytes = 4; break; default: diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2595bad9df..4422fd006d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -493,6 +493,10 @@ struct spi_flash { * @rdsr_dummy dummy cycles needed for Read Status Register command. * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register * command. + * @addr_mode_nbytes: number of address bytes of current address mode. Useful + * when the flash operates with 4B opcodes but needs the + * internal address mode for opcodes that don't have a 4B + * opcode correspondent. * @bank_read_cmd: Bank read cmd * @bank_write_cmd: Bank write cmd * @bank_curr: Current flash bank @@ -538,6 +542,7 @@ struct spi_nor { u8 program_opcode; u8 rdsr_dummy; u8 rdsr_addr_nbytes; + u8 addr_mode_nbytes; #ifdef CONFIG_SPI_FLASH_BAR u8 bank_read_cmd; u8 bank_write_cmd; From patchwork Thu Sep 1 06:05:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Kuwano X-Patchwork-Id: 1672665 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=oYlvzVsu; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MJ9Y52RgGz1yhP for ; Thu, 1 Sep 2022 16:06:49 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E5B9C8482E; Thu, 1 Sep 2022 08:06:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oYlvzVsu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 762B384223; Thu, 1 Sep 2022 08:06:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4B8BF849EE for ; Thu, 1 Sep 2022 08:06:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tkuw584924@gmail.com Received: by mail-pf1-x42a.google.com with SMTP id t129so16552647pfb.6 for ; Wed, 31 Aug 2022 23:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=QJC2+/m6RiNi+eWvnZPamoHfSyfzKAeUxkLp7X65Z/g=; b=oYlvzVsu8x7sFxVQos97EpXm+hqiJ9MPfGpLPS81bNmkBkK0xKMsV5+j5/6bSkKbYP YH9Pff0/jolrPgW92uH3uMFDleQCnft8Q8/r9mZIDd4tGcFCZiuG7m4Tce7Ign4z49qn JmPJRqdVvZI8VdN+JQ+8GrRK8Agb6cG6w8Lh0a2Gt2HICBkipsv4zlL026nysLm2VZ+Y 999KcRGqQckhbdFyTUbbXtgi/EvNlvm/XdyLOJKFMIg3M4s7w/ljyfcQTtCnMESNHzoP AjJDIMcgx2siG81OdfnUu8SadJlr6onLVhleGTjX0QgvRIhEwuf6f4VKS+mjPz/pnxXj ua/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=QJC2+/m6RiNi+eWvnZPamoHfSyfzKAeUxkLp7X65Z/g=; b=zEH9H6WF9A7ykmgCzv5y2GBYYkBHLyetK3OemG+zxn8HLgTfWWeIIcbAehDN1kCdHB Scnj2E4ziddGv2to8V+BG4hgQLhgNH5kQo6TmA71zUgAd1HtkB1mQbvIMs7l1zDOGDEd fDyhLGwMsjuZYO6TO/aZq+ansaOuHLkTNlL1wMYQv9ZHqhFXWqeXNYoJd/cgm2R6ODbT 2R9YyEL9k2TABQD+WZlk5tZgRK65O7idOrHfxStvVLjE9YRaS2JFc3vCYRidel/Y01NJ Qe9aVBATrsKF51rUgdFHbTT07529QSDyw6W4XkXLGIBYSV6RxosBHGKo+zimrMBpiYy4 HNhg== X-Gm-Message-State: ACgBeo2/6Bbxhf6gRQr44MdKumyr3X5v5VwFsnwXXsQc5UN8wn2Batqj 5NfHhbK9TohQVgyjNG6y+kY6K5bXduM= X-Google-Smtp-Source: AA6agR7c86qi8zIDVZVVcZilQub0Y54rWwel9G2qzMVeMcDgt6tUxy+h09mj+ftJeoTm3gxs0S+YPw== X-Received: by 2002:a05:6a00:114f:b0:528:2c7a:634c with SMTP id b15-20020a056a00114f00b005282c7a634cmr29368839pfm.41.1662012376989; Wed, 31 Aug 2022 23:06:16 -0700 (PDT) Received: from ISCNPF1JZGWX.infineon.com (KD106168128197.ppp-bb.dion.ne.jp. [106.168.128.197]) by smtp.gmail.com with ESMTPSA id g194-20020a6252cb000000b00538505ff705sm6991522pfb.91.2022.08.31.23.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 23:06:16 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, pratyush@kernel.org, tudor.ambarus@microchip.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 3/4] mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes Date: Thu, 1 Sep 2022 15:05:32 +0900 Message-Id: <7051c783339892f34f8532ea5d677ca7f8604747.1662011338.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano Read/Write Any Register commands take 3- or 4- byte address depending on flash's internal address mode. The nor->addr_width tracks number of address bytes used in read/program/erase ops that can be 4 (with 4B opcodes) regardless of flash's internal address mode. The nor->addr_mode_nbytes tracks flash's internal address mode so replace nor->addr_width by that. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 360fc9aff1..9f08970188 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -329,10 +329,10 @@ static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, u8 *val) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1), - SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), - SPI_MEM_OP_DUMMY(dummy / 8, 1), - SPI_MEM_OP_DATA_IN(1, NULL, 1)); + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1), + SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, addr, 1), + SPI_MEM_OP_DUMMY(dummy / 8, 1), + SPI_MEM_OP_DATA_IN(1, NULL, 1)); return spi_nor_read_write_reg(nor, &op, val); } @@ -340,10 +340,10 @@ static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val) { struct spi_mem_op op = - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1), - SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), - SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, NULL, 1)); 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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id g194-20020a6252cb000000b00538505ff705sm6991522pfb.91.2022.08.31.23.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 23:06:20 -0700 (PDT) From: tkuw584924@gmail.com X-Google-Original-From: Takahiro.Kuwano@infineon.com To: u-boot@lists.denx.de Cc: jagan@amarulasolutions.com, vigneshr@ti.com, pratyush@kernel.org, tudor.ambarus@microchip.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com, Takahiro Kuwano Subject: [PATCH 4/4] mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode Date: Thu, 1 Sep 2022 15:05:33 +0900 Message-Id: <9a961f8ee872bd4fc8ffb8dcc3494ea4f0c95a62.1662011338.git.Takahiro.Kuwano@infineon.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean From: Takahiro Kuwano The flash's internal address mode is tracked by nor->add_mode_nbytes and it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are 3- or 4-byte address mode by default, depending on model number. We need to make sure that 4-byte address mode is used for multi-die package parts. For single-die package parts (<=1Gb), registers can be accessed by 3-byte address. Read, program, and erase use the 4B opcodes that always take 4-byte address regardless of flash's internal address mode. Signed-off-by: Takahiro Kuwano --- drivers/mtd/spi/spi-nor-core.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9f08970188..0cbc647710 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -161,6 +161,7 @@ struct sfdp_header { #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ #define BFPT_DWORD16_SOFT_RST BIT(12) +#define BFPT_DWORD16_EX4B_PWRCYC BIT(21) #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ @@ -3253,10 +3254,24 @@ static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, nor->erase_opcode = SPINOR_OP_SE_4B; nor->mtd.erasesize = nor->info->sector_size; - ret = set_4byte(nor, nor->info, 1); - if (ret) - return ret; - nor->addr_width = 4; + /* + * The default address mode in multi-die package parts (>1Gb) may be + * 3- or 4-byte, depending on model number. BootROM code in some SoCs + * use 3-byte mode for backward compatibility and should switch to + * 4-byte mode after BootROM phase. Since registers in the 2nd die are + * mapped within 32-bit address space, we need to make sure the flash is + * in 4-byte address mode. The default address mode can be distinguished + * by BFPT 16th DWORD. Power cycle exits 4-byte address mode if default + * is 3-byte address mode. + */ + if (params->size > SZ_128M) { + if (bfpt->dwords[BFPT_DWORD(16)] & BFPT_DWORD16_EX4B_PWRCYC) { + ret = set_4byte(nor, nor->info, 1); + if (ret) + return ret; + } + nor->addr_mode_nbytes = 4; + } /* * The page_size is set to 512B from BFPT, but it actually depends on