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Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 60 ++++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 22 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index c772bae3cc..958432c08d 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -22,6 +22,7 @@ #include #include #include +#include #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) #define GQSPI_CONFIG_MODE_EN_MASK (3 << 30) @@ -102,8 +103,10 @@ #define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 -#define IOU_TAPDLY_BYPASS_OFST 0xFF180390 +#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \ + 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 +#define GQSPI_FREQ_37_5MHZ 37500000 #define GQSPI_FREQ_40MHZ 40000000 #define GQSPI_FREQ_100MHZ 100000000 #define GQSPI_FREQ_150MHZ 150000000 @@ -297,28 +300,41 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", __func__, reqhz, clk_rate, baudrateval); - if (reqhz < GQSPI_FREQ_40MHZ) { - zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); - tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT); - } else if (reqhz <= GQSPI_FREQ_100MHZ) { - zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass); - tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << - TAP_DLY_BYPASS_LQSPI_RX_SHIFT); - lpbkdlyadj = readl(®s->lpbkdly); - lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK); - datadlyadj = readl(®s->gqspidlyadj); - datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) - | (GQSPI_DATA_DLY_ADJ_VALUE << - GQSPI_DATA_DLY_ADJ_SHIFT)); - } else if (reqhz <= GQSPI_FREQ_150MHZ) { - lpbkdlyadj = readl(®s->lpbkdly); - lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) | - GQSPI_LPBK_DLY_ADJ_DLY_0); + if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) { + if (reqhz <= GQSPI_FREQ_40MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; + datadlyadj = (GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT) | + (GQSPI_DATA_DLY_ADJ_VALUE << + GQSPI_DATA_DLY_ADJ_SHIFT); + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | + GQSPI_LPBK_DLY_ADJ_DLY_0; + } + zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, + IOU_TAPDLY_BYPASS_MASK, tapdlybypass); + } else { + if (reqhz <= GQSPI_FREQ_37_5MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT; + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK; + datadlyadj = GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT; + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK | + (GQSPI_LPBK_DLY_ADJ_DLY_1 << + GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT); + } + writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST); } - - zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK, - tapdlybypass); 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But function should be declared to avoid this build warning: drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay': drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function 'zynqmp_mmio_write' [-Wimplicit-function-declaration] 378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, Signed-off-by: Michal Simek Signed-off-by: Ashok Reddy Soma --- arch/arm/mach-versal/include/mach/sys_proto.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 05934c28d6..8e5712e0c9 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,6 +3,8 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ +#include + enum { TCM_LOCK, TCM_SPLIT, @@ -10,3 +12,9 @@ enum { void tcm_init(u8 mode); void mem_map_fill(void); + +static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + BUILD_BUG(); + return -EINVAL; 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Thu, 25 Aug 2022 07:59:25 -0500 From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 3/6] spi: zynqmp_gqspi: Add support for IO mode Date: Thu, 25 Aug 2022 06:59:03 -0600 Message-ID: <20220825125906.11581-4-ashok.reddy.soma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220825125906.11581-1-ashok.reddy.soma@amd.com> References: <20220825125906.11581-1-ashok.reddy.soma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68ce3b14-3fdd-40a2-7079-08da8699a541 X-MS-TrafficTypeDiagnostic: MW4PR12MB6898:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Umn2jrOPeFrvLDq84rjBJhq5tToftUdYO9uYa63Z6V1v3pld8vALGoG2TMEXraxekfYCAkxo2WnwjuGhJpMkVaYLYmVvM2graOTp8l0toEIHJbD6qCA7V8FjtPs8UYRm5qR4mMkZLxfdiPBR4X9PpykeZsHxH/DGVMT0gvIoyGPIMu9GwbuT3Z6cBdS2U2p3WVPIsIRAt9t1DqsTQKky6sin1nZGF82yNO7iEOKi8Hcz1MeRMX/nrcocI0pRRN5SDIYLV0v7UY8W142UAMHxAmfo/N7T/lB+UfZyrMSMyhPe8w6+/rOvR1JBzFwLr4huUsEmOo4WcOmwwoHst8FCmJoZLN0bOfIxlR2x7/Oo36v5wVmf8zr21GX8Un5nOkNkw0xDMeBHkhoMQZT1Kp411KwQcDRWo3vvVXCmOjrOmzmXeyfTNm4OIR+mcempc8f/zw9eJrN5pK6EAe0FZ1OT3lOAb63zAVh4bLG+NYm9lkJt5uidrrEsQQ1WyB9v5FQRsOlCFw29D0+Ecyt2HjakDwueA1KT38L3ARfHG+ajPQnIe8Nx1l+SsLTwchoI9wkzpu78ay0tlPoqa1tpCw3Io7QMQTGanl/tdTw7eo4iTyXEPkEu1fvhiOEJVsZIObT9aOTRwHgnjRiBAiI1iMH3OM1hsjJBM6s3Kk6gtH5MKjC0MApzq8b++JHBdkFTcDySduZgKKc7UmAmyNm1cm8lhqwrreuI+JZAgm1nrdbWvB2fOO43MibeF+2LBpfgq/QR28U/0sgMTx+IXCglkS3IRGCk2zIg5iwD21A6Fo2s4g8= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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This is necessary for UBIFS to work properly with spi-nor devices. The driver will work in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 81 +++++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 5 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 958432c08d..78a1b48731 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -166,6 +166,7 @@ struct zynqmp_qspi_plat { struct zynqmp_qspi_dma_regs *dma_regs; u32 frequency; u32 speed_hz; + unsigned int io_mode; }; struct zynqmp_qspi_priv { @@ -174,6 +175,7 @@ struct zynqmp_qspi_priv { const void *tx_buf; void *rx_buf; unsigned int len; + unsigned int io_mode; int bytes_to_transfer; int bytes_to_receive; const struct spi_mem_op *op; @@ -190,6 +192,8 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus) plat->dma_regs = (struct zynqmp_qspi_dma_regs *) (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET); + plat->io_mode = dev_read_bool(bus, "has-io-mode"); + return 0; } @@ -209,8 +213,11 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv) config_reg = readl(®s->confr); config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | GQSPI_CONFIG_MODE_EN_MASK); - config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD | - GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK; + config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV; + config_reg |= GQSPI_GFIFO_STRT_MODE_MASK; + if (!priv->io_mode) + config_reg |= GQSPI_CONFIG_DMA_MODE; + writel(config_reg, ®s->confr); writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr); @@ -388,6 +395,7 @@ static int zynqmp_qspi_probe(struct udevice *bus) priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; + priv->io_mode = plat->io_mode; ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) { @@ -592,6 +600,66 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) return ret; } +static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, + u32 gen_fifo_cmd, u32 *buf) +{ + u32 len; + u32 actuallen = priv->len; + u32 config_reg, ier, isr; + u32 timeout = GQSPI_TIMEOUT; + struct zynqmp_qspi_regs *regs = priv->regs; + u32 last_bits; + u32 *traverse = buf; + + while (priv->len) { + len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + /* If exponent bit is set, reset immediate to be 2^len */ + if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) + priv->bytes_to_receive = (1 << len); + else + priv->bytes_to_receive = len; + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ + config_reg = readl(®s->confr); + config_reg |= GQSPI_STRT_GEN_FIFO; + writel(config_reg, ®s->confr); + /* Enable RX interrupts for IO mode */ + ier = readl(®s->ier); + ier |= GQSPI_IXR_ALL_MASK; + writel(ier, ®s->ier); + while (priv->bytes_to_receive && timeout) { + isr = readl(®s->isr); + if (isr & GQSPI_IXR_RXNEMTY_MASK) { + if (priv->bytes_to_receive >= 4) { + *traverse = readl(®s->drxr); + traverse++; + priv->bytes_to_receive -= 4; + } else { + last_bits = readl(®s->drxr); + memcpy(traverse, &last_bits, + priv->bytes_to_receive); + priv->bytes_to_receive = 0; + } + timeout = GQSPI_TIMEOUT; + } else { + udelay(1); + timeout--; + } + } + + debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", + (unsigned long)buf, (unsigned long)priv->rx_buf, + *buf, actuallen); + if (!timeout) { + printf("IO timeout: %d\n", readl(®s->isr)); + return -1; + } + } + + return 0; +} + static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { @@ -649,10 +717,13 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) * Check if receive buffer is aligned to 4 byte and length * is multiples of four byte as we are using dma to receive. */ - if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && - !(actuallen % GQSPI_DMA_ALIGN)) { + if ((!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) && + !(actuallen % GQSPI_DMA_ALIGN)) || priv->io_mode) { buf = (u32 *)priv->rx_buf; - return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); + if (priv->io_mode) + return zynqmp_qspi_start_io(priv, gen_fifo_cmd, buf); + else + return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); 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Thu, 25 Aug 2022 07:59:28 -0500 From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 4/6] spi: zynqmp_gqspi: Fix issue of reading more than 32bits length Date: Thu, 25 Aug 2022 06:59:04 -0600 Message-ID: <20220825125906.11581-5-ashok.reddy.soma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220825125906.11581-1-ashok.reddy.soma@amd.com> References: <20220825125906.11581-1-ashok.reddy.soma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f749694-92a6-443b-e4b3-08da8699a69f X-MS-TrafficTypeDiagnostic: DM6PR12MB4316:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qbGE9evAQhyc5Bzf7lCfV4nZETAIip2AmwWisELSHUjoNj8CLNoaqjq4R08eq3p8QHYWd2+vLAYnqQuD7TmDFybkaboQMWV4Mm4+RdG7pfL4/ExYPEGDRkglx6r73dbsnrcxjZS4XCGItr1yjWsTgf3F88ydhL5gdUZxB41/9P7uIifECd2lHhlqRoJhWwHuLh8Fru8xLQYEYSiU4T9HnRpcD22uzUKGffk7NDC5xx/kF3wf+PxAEV1dk9WhHC1SzSpR8Zgd9bztVzT63//mDy2HIvXyVAIkuYmaQx6CWvEmpKmv85n7EK2xZUDKwT+5rogQbmnKXRLiCdZ34UsJ1XjaJTa8QClPCwTbiqqx9XOquz8OVrMImJUc0TDMb6VXtmi5//2U3BrAG3RFpaPk9XPqvFMO7ByiMXv6H2M4XGY8AAnF15HJbw0xoiK2cevyNaEKMLoxv1n2hPhWJz5ux3u3FK6269j80vKaGXCZuIE37VE42bDiNjUN7Ppd7VdVhARC4i037OzGtW57hNFwR2/OMYa/B3GkTR8XX/VAZKyLo5sLwu0oozDcxE+GEe+Agaji/VvPHuLpiWfIyVBLfpoXDPpBQw7P67jgCCEUcbEfD7A5LPKiYKCNL1J264Uqz2WBvU8/USAm8j4Fzl2Q3UMsBN01R4fn/ItDxilXBqlyRb2rW4nvWBkUk7qrozQVy4DA44gFl++UDL8i+fF9fvJot55G0Jv9gTA0CAVIhFt+JdiekwZELAAl2M6jZCBy/by0iVZBmLe0PLT4pfgMdQmD1UUHUNzPOfEyNka3W+0= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(396003)(39860400002)(376002)(346002)(136003)(40470700004)(46966006)(36840700001)(40460700003)(86362001)(54906003)(70206006)(4326008)(40480700001)(1076003)(8676002)(82740400003)(426003)(336012)(186003)(6666004)(316002)(70586007)(6916009)(41300700001)(81166007)(26005)(356005)(47076005)(36860700001)(2616005)(82310400005)(478600001)(83380400001)(8936002)(2906002)(103116003)(36756003)(5660300002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2022 12:59:30.9180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f749694-92a6-443b-e4b3-08da8699a69f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4316 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean As the flash sizes are increasing day by day, QSPI can have devices of size > 512MB. In qspi driver we are trying to read all the data at once using DMA. The DMA descriptor destination size is only 29bits long. QSPIDMA_DST_SIZE 0xFF0F0804 BITS: 1:0 Reserved to keep word alignment BITS: 28:2 Number of 4-byte words the DMA will transfer BITS: 31:29 Reserved: Returns 0 when read, writes ignored So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes. Anything above will overflow this register and will ignore higher bits above 29 bits. Change the DMA functionality if the requested size is greater than or equal to 512MB to read 256MB chunks. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 62 ++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 78a1b48731..d5ccb48fde 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #define GQSPI_GFIFO_STRT_MODE_MASK BIT(29) @@ -666,38 +667,53 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, u32 addr; u32 size; u32 actuallen = priv->len; + u32 totallen = priv->len; int ret = 0; struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs; - writel((unsigned long)buf, &dma_regs->dmadst); - writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); - writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); - addr = (unsigned long)buf; - size = roundup(priv->len, GQSPI_DMA_ALIGN); - flush_dcache_range(addr, addr + size); + while (totallen) { + if (totallen >= SZ_512M) + priv->len = SZ_256M; + else + priv->len = totallen; - while (priv->len) { - zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); - zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + totallen -= priv->len; /* Save remaining bytes length to read */ + actuallen = priv->len; /* Actual number of bytes reading */ - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); - } + writel((unsigned long)buf, &dma_regs->dmadst); + writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize); + writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier); + addr = (unsigned long)buf; + size = roundup(priv->len, GQSPI_DMA_ALIGN); + flush_dcache_range(addr, addr + size); - ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, - 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); - return -ETIMEDOUT; - } + while (priv->len) { + zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); + zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); + + debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + } + + ret = wait_for_bit_le32(&dma_regs->dmaisr, + GQSPI_DMA_DST_I_STS_DONE, 1, + GQSPI_TIMEOUT, 1); + if (ret) { + printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); + return -ETIMEDOUT; + } + + writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); - writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); + debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", + (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, + actuallen); - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, - actuallen); + if (buf != priv->rx_buf) + memcpy(priv->rx_buf, buf, actuallen); - if (buf != priv->rx_buf) - memcpy(priv->rx_buf, buf, actuallen); + buf = (u32 *)((u8 *)buf + actuallen); + priv->rx_buf = (u8 *)priv->rx_buf + actuallen; + } return 0; } From patchwork Thu Aug 25 12:59:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Reddy Soma X-Patchwork-Id: 1670246 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 25 Aug 2022 07:59:30 -0500 From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 5/6] spi: zynqmp_qspi: Code alignment Date: Thu, 25 Aug 2022 06:59:05 -0600 Message-ID: <20220825125906.11581-6-ashok.reddy.soma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220825125906.11581-1-ashok.reddy.soma@amd.com> References: <20220825125906.11581-1-ashok.reddy.soma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 64bef405-28e0-417f-76be-08da8699a85a X-MS-TrafficTypeDiagnostic: BL3PR12MB6450:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qboRGwMRVSfg+DEaCT/udfz6y70lyPZvOIGmpetPw7PflDlBw5a90oWLhgoAf4WDPHb/SBgQp5jKIjEm3Jw0mvo+nqMvPGMy3/ZVXsYfyozqHiQUsK9fFdKAYmYvbYetVMhWxeoA+l9iS96eQfZCMR+amI77QkQN2NcjSgy56CORwvM9LVyCF88hsKLKb5Ela+htPvyYM8qwgvF94aMhnJ657QAQv4eG/ohKL0/yq7yEUgkhpC0RixNCu+oChsVzau73YW6/3v0jTLD39cMMWDlPb6+jDkSCS/UA120URLzbsdlGf9R5CdBvWNzGx1dwat3ZqEFf2TU9AiALbtMtM++9QL+0UZ8FNG6QIjsf86elbA8mpaANEjf2EAxVtlkKhwqeFyUW4oA9zj4HopRBvhxQfCHhXUHWhlkIkD/ZhzCWJPzihxVAedOlNjrfsFl4EaNZt9HQXtXxZmhRr6bN6eTXvOr0EsKS+7gXEvwDedw8ISUtukUjwO0BlLrp7Pgn9AsgeNFDeuv8/tP2V8m4WZZ8gTXBeKQInNpDWbuuSAxey/vaj1Rgzsg/08hTASZQwmuF+n4BZ5tinWA3bZBPVomaEu9eFqsKwJIMZcu2UREvss2laPv3KXHNIzeR6FgTxcvBzoEMUNnp0tx21ZD/+gajl90rHVEPg1lm3IqgEyV/XUL0aDDFJV3RmqVeqRZK4mdlPwqXXVU/n1ux3IYhQDIxUtaLdk8SXat8ynlAimmzT7N2cUueOxTBZkyU7Jnb3jMTT1fZ2kbOkfh3m8Q+UXqKcK8Q9YTJXZvxCKw9gh0= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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No functional change. Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index d5ccb48fde..4e718c545c 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -434,8 +434,7 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) debug("%s\n", __func__); /* Set the SPI Clock phase and polarities */ confr = readl(®s->confr); - confr &= ~(GQSPI_CONFIG_CPHA_MASK | - GQSPI_CONFIG_CPOL_MASK); + confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK); if (mode & SPI_CPHA) confr |= GQSPI_CONFIG_CPHA_MASK; @@ -579,8 +578,7 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); - gen_fifo_cmd |= GQSPI_GFIFO_TX | - GQSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; while (priv->len) { len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); @@ -589,11 +587,9 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd); if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) - ret = zynqmp_qspi_fill_tx_fifo(priv, - 1 << len); + ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len); else - ret = zynqmp_qspi_fill_tx_fifo(priv, - len); + ret = zynqmp_qspi_fill_tx_fifo(priv, len); if (ret) return ret; @@ -726,8 +722,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); - gen_fifo_cmd |= GQSPI_GFIFO_RX | - GQSPI_GFIFO_DATA_XFR_MASK; + gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; /* * Check if receive buffer is aligned to 4 byte and length @@ -742,8 +737,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf); } - ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, - GQSPI_DMA_ALIGN)); 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Thu, 25 Aug 2022 07:59:33 -0500 From: Ashok Reddy Soma To: CC: , , , , Ashok Reddy Soma Subject: [PATCH 6/6] arm64: versal: Enable zynqmp_gqspi driver Date: Thu, 25 Aug 2022 06:59:06 -0600 Message-ID: <20220825125906.11581-7-ashok.reddy.soma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220825125906.11581-1-ashok.reddy.soma@amd.com> References: <20220825125906.11581-1-ashok.reddy.soma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2fd64196-6468-447d-dad1-08da8699a9e8 X-MS-TrafficTypeDiagnostic: CH2PR12MB3861:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ekcvyot15zvk4fPogbncbTmjFs8JEOvq+DxshqQVsVEQYqesbOX4cJ95UekEpm5mpSZMOtiTZZBxu4xXRMB/fFngyaHrklS4UxqGgTVcUIMho9KUdpMBC8CgkI3LhnNeZU7ry49Jk9pDbtNtbAFhpXmbBCzwC83J8rf4b7h7HTB4uO5aWLkFtbDfnkiGH1xz5f1cUn8zwlXS3KEaclCDmhE19soM40G56+80/kFzGLveAvYyuJ+awvnFFTXWt16lzWkTuPz+Cs9UGqcaW3XUgVZMG7/4HyK7PLB6EApZepC8FKvARk2z0zKetPN3TocpOr1ilosbybqrH4jMLgpBZifOrelIO7I4gOo+qNi0JO59fOmv0efd2387HAQKS9rI+sn8WpRe7TEf2cwEj3QkM41rtMXHZ/MzvohBO3oH1xUzErsVCCWnhIWyQm0838TrIj9HjJuh3mGXjSwwuPCEAaE//z4Qe0EW/Liv9Ly9/JnUtsDJz3IB5RAP4iquNWKed3OzbDFHhZC1IjhYDkt3gKKvSy/tMV5VH960JduzyRZpLUKocYiYGch7uRCdH2sxzaVMYzA9uY3yV9OEJuksQIK2iXtxHIhb4S5O5ZjVblndnvpWgZf48KSqIkF8aefsimuzumNyzLWYbFGoNejeMEddfiAmQTcP/GqsjPwyQpf3k/E4bvhP/fJjplC36OXo6IgSle1Rn1ejfT6KP9AB91WIqMoV/ivtQz4LOoV2FKISw+ndk4PBxDxnEQFBax49xQZcUuS+xw3kkiDFb4Bs5Ss19TPBChM2QFWusV8xzbgo4KLHEyZIlwMa/TeeI14F X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 6e61abd0c6..239b19d316 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -113,6 +113,7 @@ CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y