From patchwork Sat Aug 20 19:47:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668460 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=XzH1zC46; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98Lz6WWjz1ygC for ; Sun, 21 Aug 2022 05:48:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231164AbiHTTsm (ORCPT ); Sat, 20 Aug 2022 15:48:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231173AbiHTTsh (ORCPT ); Sat, 20 Aug 2022 15:48:37 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC2771C13D for ; Sat, 20 Aug 2022 12:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=1EJJYFLvGwEug/sfNcp8w1KYG92RoXrIliHndeGXgho=; b=XzH1zC46RtfgGb/7MbXdhotLFg n8nTORqCsVsU35P0jwvV4YW6vK/8gy9ft07D8SgqWPwY+b+tRyKO6KtPdPdakc/mwu+o2NRgWtQ0T Jy2IY/gGpg4Z2Ge0PgEeiQLh4ivIbU+3f883sWmOTfZYVPl7PxdBpEInNgTEVZQxZTuM=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E487-DW; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 01/11] DT: RTC: orion-rtc: Convert to YAML Date: Sat, 20 Aug 2022 21:47:54 +0200 Message-Id: <20220820194804.3352415-2-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Covert the text description to YAML. The clock is optional, Orion5x based boards don't have it, but kirkwood should. Signed-off-by: Andrew Lunn --- .../bindings/rtc/marvell,orion-rtc.yaml | 48 +++++++++++++++++++ .../devicetree/bindings/rtc/orion-rtc.txt | 18 ------- 2 files changed, 48 insertions(+), 18 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/marvell,orion-rtc.yaml delete mode 100644 Documentation/devicetree/bindings/rtc/orion-rtc.txt diff --git a/Documentation/devicetree/bindings/rtc/marvell,orion-rtc.yaml b/Documentation/devicetree/bindings/rtc/marvell,orion-rtc.yaml new file mode 100644 index 000000000000..d240e67a4555 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/marvell,orion-rtc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/marvell,orion-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MVEBU Orion RTC Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Andrew Lunn + +properties: + compatible: + oneOf: + - enum: + - marvell,orion-rtc + - items: + - enum: + - marvell,kirkwood-rtc + - const: marvell,orion-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0xd0010300 0x20>; + interrupts = <50>; + }; +... diff --git a/Documentation/devicetree/bindings/rtc/orion-rtc.txt b/Documentation/devicetree/bindings/rtc/orion-rtc.txt deleted file mode 100644 index 3bf63ffa5160..000000000000 --- a/Documentation/devicetree/bindings/rtc/orion-rtc.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Mvebu Real Time Clock - -RTC controller for the Kirkwood, the Dove, the Armada 370 and the -Armada XP SoCs - -Required properties: -- compatible : Should be "marvell,orion-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. - -Example: - -rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0xd0010300 0x20>; - interrupts = <50>; -}; From patchwork Sat Aug 20 19:47:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668461 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=4xUgFpS7; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98M02c45z1yh0 for ; Sun, 21 Aug 2022 05:48:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231173AbiHTTsm (ORCPT ); Sat, 20 Aug 2022 15:48:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231213AbiHTTsh (ORCPT ); Sat, 20 Aug 2022 15:48:37 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B0341C13F for ; Sat, 20 Aug 2022 12:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=i0HCilCw6jcCPr1vZi4sizB85H9MNozoRsxg1qi40w4=; b=4xUgFpS7OET3aArXH2UNyCuo7+ RESNRVGdyJ1MX74HpX8NN2/zMxVa9zTKGowhGwpOICd/0qoKwOo+FwV5hGpK1JIaISQc62A6/Jfft p7E8prDj0FgY2CjtYUIAq+9++RhzWevHYuosOBdgLlsMpNw9oY5ll53HrW33LQSfkYvo=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48A-F4; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 02/11] DT: thermal: marvell,kirkwood-thermal: Convert to YAML Date: Sat, 20 Aug 2022 21:47:55 +0200 Message-Id: <20220820194804.3352415-3-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a simple YAML description of the thermal binding for the kirkwood thermal sensor. Signed-off-by: Andrew Lunn --- .../bindings/thermal/kirkwood-thermal.txt | 15 --------- .../thermal/marvell,kirkwood-thermal.yaml | 32 +++++++++++++++++++ 2 files changed, 32 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt create mode 100644 Documentation/devicetree/bindings/thermal/marvell,kirkwood-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt b/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt deleted file mode 100644 index 8c0f5eb86da7..000000000000 --- a/Documentation/devicetree/bindings/thermal/kirkwood-thermal.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Kirkwood Thermal - -This version is for Kirkwood 88F8262 & 88F6283 SoCs. Other kirkwoods -don't contain a thermal sensor. - -Required properties: -- compatible : "marvell,kirkwood-thermal" -- reg : Address range of the thermal registers - -Example: - - thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - }; diff --git a/Documentation/devicetree/bindings/thermal/marvell,kirkwood-thermal.yaml b/Documentation/devicetree/bindings/thermal/marvell,kirkwood-thermal.yaml new file mode 100644 index 000000000000..5d0cc6c1af33 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/marvell,kirkwood-thermal.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/marvell,kirkwood-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood Thermal Controller Device Tree Bindings + +maintainers: + - Andrew Lunn + +properties: + compatible: + enum: + - marvell,kirkwood-thermal + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + }; +... From patchwork Sat Aug 20 19:47:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668464 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=uk7odAd9; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98M16c6xz1ygC for ; Sun, 21 Aug 2022 05:48:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231262AbiHTTso (ORCPT ); Sat, 20 Aug 2022 15:48:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231313AbiHTTsl (ORCPT ); Sat, 20 Aug 2022 15:48:41 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39B951EEEB for ; Sat, 20 Aug 2022 12:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=HTgYWQzFWv9r1FkSumSkyRbC8ck4bIhUrlxaDtUCu6Q=; b=uk7odAd9CAJxBrujEEyPbsFtLr mXnS1nYWcwO4+eIitUW6QRtURx9rU4zkpauMG35Pj300ia9nBGa+ss/Aco2rQdj7KkzYZLyLY+3N4 Zt5Zl1qGjx1avRZ1jQIIx5D7q+hjDnIwg6Ze8FQkDD5oXHaiNeLMEgCVodwUNfeWBqPM=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48F-Gy; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 03/11] DT: pinctrl: Convert marvell,kirkwood-pintctrl to YAML Date: Sat, 20 Aug 2022 21:47:56 +0200 Message-Id: <20220820194804.3352415-4-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the text description to YAML. To keep the YAML versions readable, add a file per compatible. Signed-off-by: Andrew Lunn --- .../pinctrl/marvell,88f6180-pinctrl.yaml | 73 ++++ .../pinctrl/marvell,88f6190-pinctrl.yaml | 73 ++++ .../pinctrl/marvell,88f6192-pinctrl.yaml | 73 ++++ .../pinctrl/marvell,88f6281-pinctrl.yaml | 74 ++++ .../pinctrl/marvell,88f6282-pinctrl.yaml | 74 ++++ .../pinctrl/marvell,98dx1135-pinctrl.yaml | 72 ++++ .../pinctrl/marvell,98dx4122-pinctrl.yaml | 71 ++++ .../bindings/pinctrl/marvell,ac5-pinctrl.yaml | 14 +- .../pinctrl/marvell,kirkwood-pinctrl.txt | 359 ------------------ 9 files changed, 517 insertions(+), 366 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,88f6180-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,88f6190-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,88f6192-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,88f6281-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,88f6282-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,98dx1135-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,98dx4122-pinctrl.yaml delete mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,88f6180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,88f6180-pinctrl.yaml new file mode 100644 index 000000000000..c3c679f95274 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,88f6180-pinctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,88f6180-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood 88f6180 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's Kirkwood 88F6180 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,88f6180-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-.*$': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ audio, gpio, gpo, mii, nand, pex, ptp, ptp-1, ptp-2, sdio, + spi, sysrst, twsi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spic_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,88f6190-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,88f6190-pinctrl.yaml new file mode 100644 index 000000000000..46f0e61c3730 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,88f6190-pinctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,88f6190-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood 88f6190 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's Kirkwood 88F6190 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,88f6190-pinctrl + + reg: + maxItems: 1 + +patternProperties: + 'pmx-.*$': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ ge1, gpio, gpo, mii, mii-1, nand, pex, ptp, ptp-1, ptp-2, + sata0, sdio, spi, sysrst, twsi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spi_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,88f6192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,88f6192-pinctrl.yaml new file mode 100644 index 000000000000..82f8ce528d13 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,88f6192-pinctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,88f6192-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood 88f6192 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's Kirkwood 88F6192 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,88f6192-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-.*$': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ audio, ge1, gpio, gpo, mii, mii-1, nand, pex, ptp, ptp-1, ptp-2, + sata0, sata1, sdio, spi, sysrst, tdm, ts, twsi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spic_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,88f6281-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,88f6281-pinctrl.yaml new file mode 100644 index 000000000000..1d0c5932ca59 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,88f6281-pinctrl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,88f6281-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood 88f6281 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's Kirkwood 88F6281 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,88f6281-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ audio, ge1, gpio, gpo, mii, mii-1, nand, pex, ptp, ptp-1, ptp-2, + sata0, sata1, sdio, spi, sysrst, tdm, ts, twsi0, twsi1, uart0, + uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44, mpp45, mpp46, mpp47, mpp48, mpp49 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spi_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,88f6282-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,88f6282-pinctrl.yaml new file mode 100644 index 000000000000..1365c392be9e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,88f6282-pinctrl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,88f6282-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood 88f6282 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's Kirkwood 88F6282 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,88f6282-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ audio, ge1, gpio, gpo, lcd, mii, mii-1, nand, pex, + sata0, sata1, sdio, spi, sysrst, tdm, ts, twsi0, twsi1, uart0, + uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44, mpp45, mpp46, mpp47, mpp48 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spi_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,98dx1135-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,98dx1135-pinctrl.yaml new file mode 100644 index 000000000000..38c1a48e7603 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,98dx1135-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,98dx1135-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell 98dx1135 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's 98DX1135 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,98dx1135-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ gpio, gpo, nand, pex, spi, sysrst, twsi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, + mpp18, mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, + mpp26, mpp27, mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, + mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, mpp40, mpp41, + mpp42, mpp43, mpp44 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spi_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,98dx4122-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,98dx4122-pinctrl.yaml new file mode 100644 index 000000000000..32080220748c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,98dx4122-pinctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,98dx4122-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell 98dx4122 pin controller + +maintainers: + - Andrew Lunn + +description: + Bindings for Marvell's 98DX4122 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,98dx4122-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '^pmx-': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ gpio, gpo, nand, pex, spi, sysrst, twsi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, + mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, + mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, + mpp37, mpp38, mpp39, mpp40, mpp41, mpp42, mpp43, mpp44 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,88f6180-pinctrl"; + reg = <0x80020100 0x20>; + + pmx_spi: pmx-spidc { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_spi_gpio: pmx-gpio-spi { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml index a651b2744caf..4109bf1a2e5f 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml @@ -21,7 +21,7 @@ properties: maxItems: 1 patternProperties: - '-pins$': + '^pmx-': type: object $ref: pinmux-node.yaml# @@ -40,10 +40,10 @@ patternProperties: minItems: 1 items: enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, - mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19, - mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29, - mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, - mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ] + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, + mpp19, mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, + mpp28, mpp29, mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, + mpp37, mpp38, mpp39, mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ] allOf: - $ref: "pinctrl.yaml#" @@ -60,12 +60,12 @@ examples: compatible = "marvell,ac5-pinctrl"; reg = <0x80020100 0x20>; - i2c0_pins: i2c0-pins { + pmx_i2c0_pins: pmx-i2c0 { marvell,pins = "mpp26", "mpp27"; marvell,function = "i2c0"; }; - i2c0_gpio: i2c0-gpio-pins { + pmx_i2c0_gpio: pmx-gpio-i2c0 { marvell,pins = "mpp26", "mpp27"; marvell,function = "gpio"; }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt deleted file mode 100644 index 2932f171ee85..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt +++ /dev/null @@ -1,359 +0,0 @@ -* Marvell Kirkwood SoC pinctrl driver for mpp - -Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding -part and usage. - -Required properties: -- compatible: "marvell,88f6180-pinctrl", - "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", - "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl", - "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl" -- reg: register specifier of MPP registers - -This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. -It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. - -Available mpp pins/groups and functions: -Note: brackets (x) are not part of the mpp name for marvell,function and given -only for more detailed description in this document. - -* Marvell Kirkwood 88f6180 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) -mpp17 17 gpio, sdio(d3) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp35 35 gpio, mii(rxerr) -mpp36 36 gpio, audio(spdifi) -mpp37 37 gpio, audio(spdifo) -mpp38 38 gpio, audio(rmclk) -mpp39 39 gpio, audio(bclk) -mpp40 40 gpio, audio(sdo) -mpp41 41 gpio, audio(lrclk) -mpp42 42 gpio, audio(mclk) -mpp43 43 gpio, audio(sdi) -mpp44 44 gpio, audio(extclk) - -* Marvell Kirkwood 88f6190 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0) -mpp21 21 gpio, ge1(txd1), sata0(act) -mpp22 22 gpio, ge1(txd2) -mpp23 23 gpio, ge1(txd3), sata0(prsnt) -mpp24 24 gpio, ge1(rxd0) -mpp25 25 gpio, ge1(rxd1) -mpp26 26 gpio, ge1(rxd2) -mpp27 27 gpio, ge1(rxd3) -mpp28 28 gpio, ge1(col) -mpp29 29 gpio, ge1(txclk) -mpp30 30 gpio, ge1(rxclk) -mpp31 31 gpio, ge1(rxclk) -mpp32 32 gpio, ge1(txclko) -mpp33 33 gpo, ge1(txclk) -mpp34 34 gpio, ge1(txen) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr) - -* Marvell Kirkwood 88f6192 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpo, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) -mpp33 33 gpo, ge1(txclk), tdm(drx) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) - -* Marvell Kirkwood 88f6281 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) -mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) -mpp6 6 sysrst(out), spi(mosi), ptp(trig) -mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), - mii(col), mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), - mii(crs), sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), - ptp-2(trig), sata0(act) -mpp12 12 gpio, sdio(clk) -mpp13 13 gpio, sdio(cmd), uart1(txd) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act) -mpp17 17 gpio, sdio(d3), sata0(prsnt) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) -mpp33 33 gpo, ge1(txclk), tdm(drx) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) -mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi) -mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo) -mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk) -mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk) -mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo) -mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk) -mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk) -mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi) -mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk) -mpp45 45 gpio, ts(mp9), tdm(pclk) -mpp46 46 gpio, ts(mp10), tdm(fs) -mpp47 47 gpio, ts(mp11), tdm(drx) -mpp48 48 gpio, ts(mp12), tdm(dtx) -mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk) - -* Marvell Kirkwood 88f6282 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync) -mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync) -mpp6 6 sysrst(out), spi(mosi) -mpp7 7 gpo, spi(cs), lcd(pwm) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col), - mii-1(rxerr), sata1(prsnt) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs), - sata0(prsnt) -mpp10 10 gpo, spi(sck), uart0(txd), sata1(act) -mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act) -mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda) -mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm) -mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt), - audio(spdifi), audio-1(sdi) -mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act), - spi(cs) -mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), - sata1(act), lcd(extclk) -mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck) -mpp18 18 gpo, nand(io0), pex(clkreq) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), - sata1(act), lcd(d0) -mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), - audio(spdifo), lcd(d1) -mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), - sata1(prsnt), lcd(d2) -mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), - audio(bclk), lcd(d3) -mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo), - lcd(d4) -mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk), - lcd(d5) -mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk), - lcd(d6) -mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi), - lcd(d7) -mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk), - lcd(d8) -mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9) -mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10) -mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11) -mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12) -mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13) -mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14) -mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql), - lcd(d15) -mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda) -mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck) -mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18) -mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19) -mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20) -mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21) -mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22) -mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23) -mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk) -mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e) -mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync) -mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) -mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) -mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) - -* Marvell Bobcat 98dx4122 - -name pins functions -================================================================================ -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd) -mpp5 5 gpo, nand(io7), uart0(txd) -mpp6 6 sysrst(out), spi(mosi) -mpp7 7 gpo, pex(rsto), spi(cs) -mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts) -mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts) -mpp10 10 gpo, spi(sck), uart0(txd) -mpp11 11 gpio, spi(miso), uart0(rxd) -mpp13 13 gpio, uart1(txd) -mpp14 14 gpio, uart1(rxd) -mpp15 15 gpio, uart0(rts) -mpp16 16 gpio, uart0(cts) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp34 34 gpio -mpp35 35 gpio -mpp36 36 gpio -mpp37 37 gpio -mpp38 38 gpio -mpp39 39 gpio -mpp40 40 gpio -mpp41 41 gpio -mpp42 42 gpio -mpp43 43 gpio -mpp44 44 gpio -mpp45 45 gpio -mpp49 49 gpio - -* Marvell Poncat2 98dx1135 - -name pins functions -================================================================================ - -mpp0 0 gpio, nand(io2), spi(cs) -mpp1 1 gpo, nand(io3), spi(mosi) -mpp2 2 gpo, nand(io4), spi(sck) -mpp3 3 gpo, nand(io5), spi(miso) -mpp4 4 gpio, nand(io6), uart0(rxd) -mpp5 5 gpo, nand(io7), uart0(txd) -mpp6 6 sysrst(out) -mpp7 7 gpo, spi(cs) -mpp8 8 gpio, twsi0(sda), uart1(rts) -mpp9 9 gpio, twsi(sck), uart1(cts) -mpp10 10 gpo, uart0(txd) -mpp11 11 gpio, uart0(rxd) -mpp13 13 gpio, uart1(txd) -mpp14 14 gpio, uart1(rxd) -mpp15 15 gpio, uart0(rts) -mpp16 16 gpio, uart0(cts) -mpp17 17 gpio, nand(cle) -mpp18 18 gpo, nand(io0) -mpp19 19 gpo, nand(io1) -mpp20 20 gpio -mpp21 21 gpio -mpp22 22 gpio -mpp23 23 gpio -mpp24 24 gpio -mpp25 25 gpio -mpp26 26 gpio -mpp27 27 gpio -mpp28 28 gpio, nand(ren) -mpp29 29 gpio, nand(wen) -mpp30 30 gpio -mpp31 31 gpio -mpp32 32 gpio -mpp33 33 gpio -mpp34 34 gpio, nand(ale) -mpp35 35 gpio, nand(cen) From patchwork Sat Aug 20 19:47:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668458 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=OwGij1xB; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98Ly3Df9z1yh0 for ; Sun, 21 Aug 2022 05:48:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229714AbiHTTsk (ORCPT ); Sat, 20 Aug 2022 15:48:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230004AbiHTTsg (ORCPT ); Sat, 20 Aug 2022 15:48:36 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A393617E05 for ; Sat, 20 Aug 2022 12:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=IceNY8bexB1L9jAUSLx8LdnUn95xilHn6loRWJYWVOg=; b=OwGij1xB/VZcbViSYtsMk7kNx7 Qkf8pCBS8H1UehXLdius4srnyrrfHARDzua0UjVDSaaRQtP86PYaQ3QpFiqEyp+wnUQq/Wvyspb3N hWE0HcQ2hVxpT5YFNCeiGYtiumjqy0BXf4joUOglaOEe1egLNzqnVkvBNTDQvJHC/bJk=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48I-JY; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 04/11] DT: USB: Convert ehci-orion to YAML Date: Sat, 20 Aug 2022 21:47:57 +0200 Message-Id: <20220820194804.3352415-5-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andrew Lunn --- .../devicetree/bindings/usb/ehci-orion.txt | 22 ---------- .../bindings/usb/marvell,orion-ehci.yaml | 44 +++++++++++++++++++ 2 files changed, 44 insertions(+), 22 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/ehci-orion.txt create mode 100644 Documentation/devicetree/bindings/usb/marvell,orion-ehci.yaml diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt deleted file mode 100644 index 2855bae79fda..000000000000 --- a/Documentation/devicetree/bindings/usb/ehci-orion.txt +++ /dev/null @@ -1,22 +0,0 @@ -* EHCI controller, Orion Marvell variants - -Required properties: -- compatible: must be one of the following - "marvell,orion-ehci" - "marvell,armada-3700-ehci" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The EHCI interrupt - -Optional properties: -- clocks: reference to the clock -- phys: reference to the USB PHY -- phy-names: name of the USB PHY, should be "usb" - -Example: - - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - }; diff --git a/Documentation/devicetree/bindings/usb/marvell,orion-ehci.yaml b/Documentation/devicetree/bindings/usb/marvell,orion-ehci.yaml new file mode 100644 index 000000000000..5db56d62b3b5 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/marvell,orion-ehci.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/marvell,orion-ehci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion USB Controller Device Tree Bindings + +maintainers: + - Andrew Lunn + +properties: + compatible: + enum: + - marvell,orion-ehci + - marvell,armada-3700-ehci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + phys: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + }; +... From patchwork Sat Aug 20 19:47:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668457 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=2RBnx2Qn; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98Ly02S7z1ygC for ; Sun, 21 Aug 2022 05:48:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229833AbiHTTsk (ORCPT ); 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Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48L-Kk; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 05/11] DT: watchdog: Convert marvel.txt to YAML Date: Sat, 20 Aug 2022 21:47:58 +0200 Message-Id: <20220820194804.3352415-6-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andrew Lunn --- .../devicetree/bindings/watchdog/marvel.txt | 45 ---------- .../bindings/watchdog/marvell,orion-wdt.yaml | 83 +++++++++++++++++++ 2 files changed, 83 insertions(+), 45 deletions(-) delete mode 100644 Documentation/devicetree/bindings/watchdog/marvel.txt create mode 100644 Documentation/devicetree/bindings/watchdog/marvell,orion-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt deleted file mode 100644 index c1b67a78f00c..000000000000 --- a/Documentation/devicetree/bindings/watchdog/marvel.txt +++ /dev/null @@ -1,45 +0,0 @@ -* Marvell Orion Watchdog Time - -Required Properties: - -- Compatibility : "marvell,orion-wdt" - "marvell,armada-370-wdt" - "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt" - -- reg : Should contain two entries: first one with the - timer control address, second one with the - rstout enable address. - -For "marvell,armada-375-wdt" and "marvell,armada-380-wdt": - -- reg : A third entry is mandatory and should contain the - shared mask/unmask RSTOUT address. - -Clocks required for compatibles = "marvell,orion-wdt", - "marvell,armada-370-wdt": -- clocks : Must contain a single entry describing the clock input - -Clocks required for compatibles = "marvell,armada-xp-wdt" - "marvell,armada-375-wdt" - "marvell,armada-380-wdt": -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: - "nbclk" (L2/coherency fabric clock), - "fixed" (Reference 25 MHz fixed-clock). - -Optional properties: - -- interrupts : Contains the IRQ for watchdog expiration -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - - wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>, <0x20108 0x4>; - interrupts = <3>; - timeout-sec = <10>; - clocks = <&gate_clk 7>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/marvell,orion-wdt.yaml b/Documentation/devicetree/bindings/watchdog/marvell,orion-wdt.yaml new file mode 100644 index 000000000000..8607e1620f72 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/marvell,orion-wdt.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/marvell,orion-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion Watchdog Device Tree Bindings + +allOf: + - $ref: "watchdog.yaml#" + +maintainers: + - Andrew Lunn + +properties: + compatible: + enum: + - marvell,orion-wdt + - marvell,armada-370-wdt + - marvell,armada-xp-wdt + - marvell,armada-375-wdt + - marvell,armada-380-wdt + + reg: + description: + Normally two items, the timer control address and the rstout enable + address. However armada-375 and 380 require and additional shared + mask/unmask rstout address + + clocks: + minItems: 1 + items: + - description: L2/coherency fabric clock + - description: Reference 25 MHz fixed-clock + + interrupts: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - clocks + - interrupts + +if: + properties: + compatible: + contains: + enum: + - marvell,armada-xp-wdt + - marvell,armada-375-wdt + - marvell,armada-380-wdt +then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: nbclk + - const: fixed + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + watchdog@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>, <0x20108 0x4>; + interrupts = <3>; + timeout-sec = <10>; + clocks = <&gate_clk 7>; + }; +... From patchwork Sat Aug 20 19:48:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668456 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=TIgA+c4D; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98Lw6zFPz1ygC for ; Sun, 21 Aug 2022 05:48:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229488AbiHTTsj (ORCPT ); Sat, 20 Aug 2022 15:48:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229833AbiHTTsg (ORCPT ); Sat, 20 Aug 2022 15:48:36 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F46517ABD for ; Sat, 20 Aug 2022 12:48:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=aN5182nSfXEkiRzkgHdn65ByCd4rqoUfZ4uBAP3pET0=; b=TIgA+c4DwfNIuxa4Dmw2fQirfH 55sr7DmLGm09nyD4sTX2gYcsoZDSYTbOaGpiuX+pxgziQJ5okq2wRAKtj4UTOomp4J5XLFaDbtYcr v/iL+HEABD1krU0hJjrUAXkW0v/tQrPdRAXjVD50pRoK0ahtWem+2uCD2dTE0YfBKEu4=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48R-NG; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 07/11] DT: nand-controller: Reflect reality of marvell,orion-nand Date: Sat, 20 Aug 2022 21:48:00 +0200 Message-Id: <20220820194804.3352415-8-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Marvell Orion NAND driver comes from before the time of the standardised NAND binding. The controller only supports a single device, and expects the NAND partition table to be directly in the controller node. This goes against the standardised NAND binding which expects a sub node per NAND device, which contains the partition table. Since the partition table contains a reg property indicating the start address of the partition and its length, it needs #size-cells set to 1. However, for a list of nand devices, the reg value is the device number, requiring #size-cells of 0. Add an exception to nand-controller.yaml to allow this #size-cells value when the compatible matches the orion controller. In order that the example works, it needs a compatible string so the comparison can be made. Signed-off-by: Andrew Lunn --- .../bindings/mtd/nand-controller.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index 359a015d4e5a..ab90e34557ad 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -34,7 +34,7 @@ properties: const: 1 "#size-cells": - const: 0 + enum: [0, 1] ranges: true @@ -130,11 +130,26 @@ required: - "#address-cells" - "#size-cells" +if: + properties: + compatible: + contains: + const: marvell,orion-nand +then: + properties: + "#size-cells": + const: 1 +else: + properties: + "#size-cells": + const: 0 + additionalProperties: true examples: - | nand-controller { + compatible = "bar"; #address-cells = <1>; #size-cells = <0>; cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */ From patchwork Sat Aug 20 19:48:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668462 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=QVJsiCob; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98M10DNdz1ygC for ; Sun, 21 Aug 2022 05:48:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231213AbiHTTsn (ORCPT ); Sat, 20 Aug 2022 15:48:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230399AbiHTTsj (ORCPT ); Sat, 20 Aug 2022 15:48:39 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8CE217A88 for ; Sat, 20 Aug 2022 12:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=yPQNUvxFfjxuFGLxuzDbBYBYTShrxNxLh7RaBOiSVN0=; b=QVJsiCobhDs5UE4t0lPKf0gjET dlgOEBH+rhsGk0y+7xzPwS596oE+g4g2+G3/fROWgyCLT2MAYCiqOoNYuH7jWo4l7yJU4UKS5LQ5Z WzH/bhPTvfunrdInJ78TkTTyq3vk+NtJivoQVZKKbyNfNS7c240jmR8BqzqpsmG+mVfU=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48U-Oe; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 08/11] DT: mtd: Convert orion-nand to YAML Date: Sat, 20 Aug 2022 21:48:01 +0200 Message-Id: <20220820194804.3352415-9-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This works for Kirkwood, but orion5x has an odd bus structure which results in some warnings. Signed-off-by: Andrew Lunn --- .../bindings/mtd/marvell,orion-nand.yaml | 85 +++++++++++++++++++ .../devicetree/bindings/mtd/orion-nand.txt | 50 ----------- 2 files changed, 85 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/marvell,orion-nand.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/orion-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/marvell,orion-nand.yaml b/Documentation/devicetree/bindings/mtd/marvell,orion-nand.yaml new file mode 100644 index 000000000000..127c12e6f5ce --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/marvell,orion-nand.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/marvell,orion-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion NAND Controller Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Andrew Lunn + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + enum: + - marvell,orion-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cle: + description: + Address line number connected to CLE. Default is 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + ale: + description: + Address line number connected to ALE. Default is 1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + bank-width: + description: Width (in bytes) of the bank. Equal to the device width times + the number of interleaved chips. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 2, 4 ] + + chip-delay: + description: + Chip dependent delay for transferring data from array to read + registers in usecs + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + + partitions: + type: object + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + nand-controller@f4000000 { + #address-cells = <1>; + #size-cells = <1>; + cle = <0>; + ale = <1>; + bank-width = <1>; + chip-delay = <25>; + compatible = "marvell,orion-nand"; + reg = <0xf4000000 0x400>; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt deleted file mode 100644 index 2d6ab660e603..000000000000 --- a/Documentation/devicetree/bindings/mtd/orion-nand.txt +++ /dev/null @@ -1,50 +0,0 @@ -NAND support for Marvell Orion SoC platforms - -Required properties: -- compatible : "marvell,orion-nand". -- reg : Base physical address of the NAND and length of memory mapped - region - -Optional properties: -- cle : Address line number connected to CLE. Default is 0 -- ale : Address line number connected to ALE. Default is 1 -- bank-width : Width in bytes of the device. Default is 1 -- chip-delay : Chip dependent delay for transferring data from array to read - registers in usecs - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -nand@f4000000 { - #address-cells = <1>; - #size-cells = <1>; - cle = <0>; - ale = <1>; - bank-width = <1>; - chip-delay = <25>; - compatible = "marvell,orion-nand"; - reg = <0xf4000000 0x400>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - partition@100000 { - label = "uImage"; - reg = <0x0100000 0x200000>; - }; - - partition@300000 { - label = "dtb"; - reg = <0x0300000 0x100000>; - }; - - partition@400000 { - label = "root"; - reg = <0x0400000 0x7d00000>; - }; -}; From patchwork Sat Aug 20 19:48:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668463 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=jzcLYikk; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98M13Px2z1yh0 for ; Sun, 21 Aug 2022 05:48:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbiHTTso (ORCPT ); Sat, 20 Aug 2022 15:48:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231262AbiHTTsj (ORCPT ); Sat, 20 Aug 2022 15:48:39 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E708D1EC67 for ; Sat, 20 Aug 2022 12:48:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=gZ05criROPJOI6jRGySfjkdG7y3rkJwp0PpmApMj5Ys=; b=jzcLYikkjeq7hW3GTmFDGDqJ8e Hu5uQ5aqtTanUgR7nxi1ySPGb7XyzJecoEO6uyKRQd5cZl46nXQOUZk1wm03b/u4t6WGKS8GARqud kakL0cR/mn4ibwY+SkAl0pqpie/KTjmoYIJZt7KOlrM7rfa8OMEMyn/hno+MkYRdekYw=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48a-RE; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 10/11] DT: timer: Convert marvell,orion-timer.txt to YAML Date: Sat, 20 Aug 2022 21:48:03 +0200 Message-Id: <20220820194804.3352415-11-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andrew Lunn --- .../bindings/timer/marvell,orion-timer.txt | 16 ------ .../bindings/timer/marvell,orion-timer.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/marvell,orion-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt deleted file mode 100644 index cd1a0c256f94..000000000000 --- a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt +++ /dev/null @@ -1,16 +0,0 @@ -Marvell Orion SoC timer - -Required properties: -- compatible: shall be "marvell,orion-timer" -- reg: base address of the timer register starting with TIMERS CONTROL register -- interrupts: should contain the interrupts for Timer0 and Timer1 -- clocks: phandle of timer reference clock (tclk) - -Example: - timer: timer { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml new file mode 100644 index 000000000000..330bb3cd9c26 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/marvell,orion-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion Timer bindings + +maintainers: + - Andrew Lunn + +properties: + $nodename: + pattern: '^timer@[a-f0-9]+$' + + compatible: + const: marvell,orion-timer + + reg: + description: + Base address of the timer register starting with TIMERS CONTROL register + maxItems: 1 + + interrupts: + description: + Should contain the interrupts for Timer0 and Timer1 + minItems: 2 + maxItems: 2 + + clocks: + description: + phandle of timer reference clock (tclk) + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; +... From patchwork Sat Aug 20 19:48:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1668465 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256 header.s=20171124 header.b=4S2rbcbD; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M98M66lDDz1ygC for ; Sun, 21 Aug 2022 05:48:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229735AbiHTTst (ORCPT ); Sat, 20 Aug 2022 15:48:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229600AbiHTTss (ORCPT ); Sat, 20 Aug 2022 15:48:48 -0400 Received: from vps0.lunn.ch (vps0.lunn.ch [185.16.172.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E71B6220C3 for ; Sat, 20 Aug 2022 12:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:From:Sender:Reply-To:Subject:Date: Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=9c/m3HYF5objKw9/G2hjUYwRsYS3THqF8Se7/W8r5Hw=; b=4S2rbcbD73PjCugdvWpxHnHnCT IWk/0UbGcn49JBH8tepmrjKiC8wLtyVR+1ZX/U+i/z8MLjHSSKeMmWGJWKWBwS1/mMVxRzVWvuYJB TOM5FgE5hYGcrYTp7N9ThHxY0h/uNcu1fbGngm0LWiS7isX3lretfVYURsw7Rg9ggzY8=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1oPUSL-00E48d-SX; Sat, 20 Aug 2022 21:48:29 +0200 From: Andrew Lunn To: Gregory Clement Cc: arm-soc , Device Tree , Andrew Lunn Subject: [PATCH 11/11] DT: clock: Convert mvebu-gated-clock.txt to YAML Date: Sat, 20 Aug 2022 21:48:04 +0200 Message-Id: <20220820194804.3352415-12-andrew@lunn.ch> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220820194804.3352415-1-andrew@lunn.ch> References: <20220820194804.3352415-1-andrew@lunn.ch> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Andrew Lunn --- .../clock/marvell,kirkwood-gating-clock.yaml | 230 ++++++++++++++++++ .../bindings/clock/mvebu-gated-clock.txt | 205 ---------------- 2 files changed, 230 insertions(+), 205 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/marvell,kirkwood-gating-clock.yaml delete mode 100644 Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt diff --git a/Documentation/devicetree/bindings/clock/marvell,kirkwood-gating-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,kirkwood-gating-clock.yaml new file mode 100644 index 000000000000..b420a2c2a8d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,kirkwood-gating-clock.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,kirkwood-gating-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvel Gating Clock Device Tree Bindings + +maintainers: + - Andrew Lunn + +# Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some +# peripheral clocks to be gated to save some power. The clock consumer +# should specify the desired clock by having the clock ID in its +# "clocks" phandle cell. The clock ID is directly mapped to the +# corresponding clock gating control bit in HW to ease manual clock +# lookup in datasheet. +# +# The following is a list of provided IDs for Armada 370: +# ID Clock Peripheral +# ----------------------------------- +# 0 Audio AC97 Cntrl +# 1 pex0_en PCIe 0 Clock out +# 2 pex1_en PCIe 1 Clock out +# 3 ge1 Gigabit Ethernet 1 +# 4 ge0 Gigabit Ethernet 0 +# 5 pex0 PCIe Cntrl 0 +# 9 pex1 PCIe Cntrl 1 +# 15 sata0 SATA Host 0 +# 17 sdio SDHCI Host +# 23 crypto CESA (crypto engine) +# 25 tdm Time Division Mplx +# 28 ddr DDR Cntrl +# 30 sata1 SATA Host 0 +# +# The following is a list of provided IDs for Armada 375: +# ID Clock Peripheral +# ----------------------------------- +# 2 mu Management Unit +# 3 pp Packet Processor +# 4 ptp PTP +# 5 pex0 PCIe 0 Clock out +# 6 pex1 PCIe 1 Clock out +# 8 audio Audio Cntrl +# 11 nd_clk Nand Flash Cntrl +# 14 sata0_link SATA 0 Link +# 15 sata0_core SATA 0 Core +# 16 usb3 USB3 Host +# 17 sdio SDHCI Host +# 18 usb USB Host +# 19 gop Gigabit Ethernet MAC +# 20 sata1_link SATA 1 Link +# 21 sata1_core SATA 1 Core +# 22 xor0 XOR DMA 0 +# 23 xor1 XOR DMA 0 +# 24 copro Coprocessor +# 25 tdm Time Division Mplx +# 28 crypto0_enc Cryptographic Unit Port 0 Encryption +# 29 crypto0_core Cryptographic Unit Port 0 Core +# 30 crypto1_enc Cryptographic Unit Port 1 Encryption +# 31 crypto1_core Cryptographic Unit Port 1 Core +# +# The following is a list of provided IDs for Armada 380/385: +# ID Clock Peripheral +# ----------------------------------- +# 0 audio Audio +# 2 ge2 Gigabit Ethernet 2 +# 3 ge1 Gigabit Ethernet 1 +# 4 ge0 Gigabit Ethernet 0 +# 5 pex1 PCIe 1 +# 6 pex2 PCIe 2 +# 7 pex3 PCIe 3 +# 8 pex0 PCIe 0 +# 9 usb3h0 USB3 Host 0 +# 10 usb3h1 USB3 Host 1 +# 11 usb3d USB3 Device +# 13 bm Buffer Management +# 14 crypto0z Cryptographic 0 Z +# 15 sata0 SATA 0 +# 16 crypto1z Cryptographic 1 Z +# 17 sdio SDIO +# 18 usb2 USB 2 +# 21 crypto1 Cryptographic 1 +# 22 xor0 XOR 0 +# 23 crypto0 Cryptographic 0 +# 25 tdm Time Division Multiplexing +# 28 xor1 XOR 1 +# 30 sata1 SATA 1 +# +# The following is a list of provided IDs for Armada 39x: +# ID Clock Peripheral +# ----------------------------------- +# 5 pex1 PCIe 1 +# 6 pex2 PCIe 2 +# 7 pex3 PCIe 3 +# 8 pex0 PCIe 0 +# 9 usb3h0 USB3 Host 0 +# 10 usb3h1 USB3 Host 1 +# 15 sata0 SATA 0 +# 17 sdio SDIO +# 22 xor0 XOR 0 +# 28 xor1 XOR 1 +# +# The following is a list of provided IDs for Armada XP: +# ID Clock Peripheral +# ----------------------------------- +# 0 audio Audio Cntrl +# 1 ge3 Gigabit Ethernet 3 +# 2 ge2 Gigabit Ethernet 2 +# 3 ge1 Gigabit Ethernet 1 +# 4 ge0 Gigabit Ethernet 0 +# 5 pex0 PCIe Cntrl 0 +# 6 pex1 PCIe Cntrl 1 +# 7 pex2 PCIe Cntrl 2 +# 8 pex3 PCIe Cntrl 3 +# 13 bp +# 14 sata0lnk +# 15 sata0 SATA Host 0 +# 16 lcd LCD Cntrl +# 17 sdio SDHCI Host +# 18 usb0 USB Host 0 +# 19 usb1 USB Host 1 +# 20 usb2 USB Host 2 +# 22 xor0 XOR DMA 0 +# 23 crypto CESA engine +# 25 tdm Time Division Mplx +# 28 xor1 XOR DMA 1 +# 29 sata1lnk +# 30 sata1 SATA Host 1 +# +# The following is a list of provided IDs for 98dx3236: +# ID Clock Peripheral +# ----------------------------------- +# 3 ge1 Gigabit Ethernet 1 +# 4 ge0 Gigabit Ethernet 0 +# 5 pex0 PCIe Cntrl 0 +# 17 sdio SDHCI Host +# 18 usb0 USB Host 0 +# 22 xor0 XOR DMA 0 +# +# The following is a list of provided IDs for Dove: +# ID Clock Peripheral +# ----------------------------------- +# 0 usb0 USB Host 0 +# 1 usb1 USB Host 1 +# 2 ge Gigabit Ethernet +# 3 sata SATA Host +# 4 pex0 PCIe Cntrl 0 +# 5 pex1 PCIe Cntrl 1 +# 8 sdio0 SDHCI Host 0 +# 9 sdio1 SDHCI Host 1 +# 10 nand NAND Cntrl +# 11 camera Camera Cntrl +# 12 i2s0 I2S Cntrl 0 +# 13 i2s1 I2S Cntrl 1 +# 15 crypto CESA engine +# 21 ac97 AC97 Cntrl +# 22 pdma Peripheral DMA +# 23 xor0 XOR DMA 0 +# 24 xor1 XOR DMA 1 +# 30 gephy Gigabit Ethernel PHY +# Note: gephy(30) is implemented as a parent clock of ge(2) +# +# The following is a list of provided IDs for Kirkwood: +# ID Clock Peripheral +# ----------------------------------- +# 0 ge0 Gigabit Ethernet 0 +# 2 pex0 PCIe Cntrl 0 +# 3 usb0 USB Host 0 +# 4 sdio SDIO Cntrl +# 5 tsu Transp. Stream Unit +# 6 dunit SDRAM Cntrl +# 7 runit Runit +# 8 xor0 XOR DMA 0 +# 9 audio I2S Cntrl 0 +# 14 sata0 SATA Host 0 +# 15 sata1 SATA Host 1 +# 16 xor1 XOR DMA 1 +# 17 crypto CESA engine +# 18 pex1 PCIe Cntrl 1 +# 19 ge1 Gigabit Ethernet 1 +# 20 tdm Time Division Mplx +# +# + +properties: + compatible: + enum: + - marvell,armada-370-gating-clock + - marvell,armada-375-gating-clock + - marvell,armada-380-gating-clock + - marvell,armada-390-gating-clock + - marvell,armada-xp-gating-clock + - marvell,mv98dx3236-gating-clock + - marvell,dove-gating-clock + - marvell,kirkwood-gating-clock + + reg: + description: + Shall be the register address of the Clock Gating Control register + maxItems: 1 + + "#clock-cells": + const: 1 + description: + This additional argument passed to that clock is the offset of + the bit controlling this particular gate in the register. + + clocks: + description: + default parent clock phandle (e.g. tclk) + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + gate_clk: clock-gating-control@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + /* default parent clock is tclk */ + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt deleted file mode 100644 index de562da2ae77..000000000000 --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt +++ /dev/null @@ -1,205 +0,0 @@ -* Gated Clock bindings for Marvell EBU SoCs - -Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some -peripheral clocks to be gated to save some power. The clock consumer -should specify the desired clock by having the clock ID in its -"clocks" phandle cell. The clock ID is directly mapped to the -corresponding clock gating control bit in HW to ease manual clock -lookup in datasheet. - -The following is a list of provided IDs for Armada 370: -ID Clock Peripheral ------------------------------------ -0 Audio AC97 Cntrl -1 pex0_en PCIe 0 Clock out -2 pex1_en PCIe 1 Clock out -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -9 pex1 PCIe Cntrl 1 -15 sata0 SATA Host 0 -17 sdio SDHCI Host -23 crypto CESA (crypto engine) -25 tdm Time Division Mplx -28 ddr DDR Cntrl -30 sata1 SATA Host 0 - -The following is a list of provided IDs for Armada 375: -ID Clock Peripheral ------------------------------------ -2 mu Management Unit -3 pp Packet Processor -4 ptp PTP -5 pex0 PCIe 0 Clock out -6 pex1 PCIe 1 Clock out -8 audio Audio Cntrl -11 nd_clk Nand Flash Cntrl -14 sata0_link SATA 0 Link -15 sata0_core SATA 0 Core -16 usb3 USB3 Host -17 sdio SDHCI Host -18 usb USB Host -19 gop Gigabit Ethernet MAC -20 sata1_link SATA 1 Link -21 sata1_core SATA 1 Core -22 xor0 XOR DMA 0 -23 xor1 XOR DMA 0 -24 copro Coprocessor -25 tdm Time Division Mplx -28 crypto0_enc Cryptographic Unit Port 0 Encryption -29 crypto0_core Cryptographic Unit Port 0 Core -30 crypto1_enc Cryptographic Unit Port 1 Encryption -31 crypto1_core Cryptographic Unit Port 1 Core - -The following is a list of provided IDs for Armada 380/385: -ID Clock Peripheral ------------------------------------ -0 audio Audio -2 ge2 Gigabit Ethernet 2 -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex1 PCIe 1 -6 pex2 PCIe 2 -7 pex3 PCIe 3 -8 pex0 PCIe 0 -9 usb3h0 USB3 Host 0 -10 usb3h1 USB3 Host 1 -11 usb3d USB3 Device -13 bm Buffer Management -14 crypto0z Cryptographic 0 Z -15 sata0 SATA 0 -16 crypto1z Cryptographic 1 Z -17 sdio SDIO -18 usb2 USB 2 -21 crypto1 Cryptographic 1 -22 xor0 XOR 0 -23 crypto0 Cryptographic 0 -25 tdm Time Division Multiplexing -28 xor1 XOR 1 -30 sata1 SATA 1 - -The following is a list of provided IDs for Armada 39x: -ID Clock Peripheral ------------------------------------ -5 pex1 PCIe 1 -6 pex2 PCIe 2 -7 pex3 PCIe 3 -8 pex0 PCIe 0 -9 usb3h0 USB3 Host 0 -10 usb3h1 USB3 Host 1 -15 sata0 SATA 0 -17 sdio SDIO -22 xor0 XOR 0 -28 xor1 XOR 1 - -The following is a list of provided IDs for Armada XP: -ID Clock Peripheral ------------------------------------ -0 audio Audio Cntrl -1 ge3 Gigabit Ethernet 3 -2 ge2 Gigabit Ethernet 2 -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -6 pex1 PCIe Cntrl 1 -7 pex2 PCIe Cntrl 2 -8 pex3 PCIe Cntrl 3 -13 bp -14 sata0lnk -15 sata0 SATA Host 0 -16 lcd LCD Cntrl -17 sdio SDHCI Host -18 usb0 USB Host 0 -19 usb1 USB Host 1 -20 usb2 USB Host 2 -22 xor0 XOR DMA 0 -23 crypto CESA engine -25 tdm Time Division Mplx -28 xor1 XOR DMA 1 -29 sata1lnk -30 sata1 SATA Host 1 - -The following is a list of provided IDs for 98dx3236: -ID Clock Peripheral ------------------------------------ -3 ge1 Gigabit Ethernet 1 -4 ge0 Gigabit Ethernet 0 -5 pex0 PCIe Cntrl 0 -17 sdio SDHCI Host -18 usb0 USB Host 0 -22 xor0 XOR DMA 0 - -The following is a list of provided IDs for Dove: -ID Clock Peripheral ------------------------------------ -0 usb0 USB Host 0 -1 usb1 USB Host 1 -2 ge Gigabit Ethernet -3 sata SATA Host -4 pex0 PCIe Cntrl 0 -5 pex1 PCIe Cntrl 1 -8 sdio0 SDHCI Host 0 -9 sdio1 SDHCI Host 1 -10 nand NAND Cntrl -11 camera Camera Cntrl -12 i2s0 I2S Cntrl 0 -13 i2s1 I2S Cntrl 1 -15 crypto CESA engine -21 ac97 AC97 Cntrl -22 pdma Peripheral DMA -23 xor0 XOR DMA 0 -24 xor1 XOR DMA 1 -30 gephy Gigabit Ethernel PHY -Note: gephy(30) is implemented as a parent clock of ge(2) - -The following is a list of provided IDs for Kirkwood: -ID Clock Peripheral ------------------------------------ -0 ge0 Gigabit Ethernet 0 -2 pex0 PCIe Cntrl 0 -3 usb0 USB Host 0 -4 sdio SDIO Cntrl -5 tsu Transp. Stream Unit -6 dunit SDRAM Cntrl -7 runit Runit -8 xor0 XOR DMA 0 -9 audio I2S Cntrl 0 -14 sata0 SATA Host 0 -15 sata1 SATA Host 1 -16 xor1 XOR DMA 1 -17 crypto CESA engine -18 pex1 PCIe Cntrl 1 -19 ge1 Gigabit Ethernet 1 -20 tdm Time Division Mplx - -Required properties: -- compatible : shall be one of the following: - "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating - "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating - "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating - "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating - "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating - "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating - "marvell,dove-gating-clock" - for Dove SoC clock gating - "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating -- reg : shall be the register address of the Clock Gating Control register -- #clock-cells : from common clock binding; shall be set to 1 - -Optional properties: -- clocks : default parent clock phandle (e.g. tclk) - -Example: - -gate_clk: clock-gating-control@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; - /* default parent clock is tclk */ - clocks = <&core_clk 0>; - #clock-cells = <1>; -}; - -sdio0: sdio@92000 { - compatible = "marvell,dove-sdhci"; - /* get clk gate bit 8 (sdio0) */ - clocks = <&gate_clk 8>; -};