From patchwork Thu Aug 18 09:16:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1667612 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=d/Te43mm; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M7fRj4Nw9z1ygs for ; Thu, 18 Aug 2022 19:17:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236657AbiHRJRc (ORCPT ); Thu, 18 Aug 2022 05:17:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232900AbiHRJRb (ORCPT ); Thu, 18 Aug 2022 05:17:31 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98CB067CA5; Thu, 18 Aug 2022 02:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660814205; cv=none; d=zohomail.com; s=zohoarc; b=mfWE9788EDfsm55K8i8vHWwCMzj+jvHGrVXjWFgD+3NI0Se/zUBg9SkK0YE/x6QeCrndEwoqdKIJCTjbS0EQg27O2zkigNB8VS3q9yMVIn9t7g1UXMcHKXH4piZv66ftIYjiw3/QJsStbQcgMADRbZfYe5Ks1OCqcRjO1NLtdu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660814205; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=wpAUAfc07ylNY9oSdQ6DPJcvSW66IDwq4Ksnwpr1SWA=; b=RrhhNRiX/4mh+bl6eE4oNd45nR2F9ndMoUvmHxhFfHJgGxeYmmBmdcDORsRbmfSQorB7Q8sDBeyD9WhZ0XJzFQtqP8hzP1sKAB4kH4aK/swQ2nlaHb3oZ18T0HBgAnh8BSSBDozFShu366PuAKjS7MX80IO2FmIhb3xUvUMINOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814205; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=wpAUAfc07ylNY9oSdQ6DPJcvSW66IDwq4Ksnwpr1SWA=; b=d/Te43mme5wi6A1Qtwq2i2032uIc1QxhgO7Ypz5rcxXD7UyirsmOCWREZT6Bksnb bw/MMHGfs7OSIHA7QUx2+Rj0IjUXk4kTmtyb17oSCU2gb/2q3B9bq4hsyw7D4KGOxmI pAkYVq/EHYXnoKMzf0GpIx+QveGvhNHuUIrbuf1Y= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 166081420373773.15587554921001; Thu, 18 Aug 2022 02:16:43 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Rob Herring Subject: [PATCH v3 1/6] dt-bindings: net: dsa: mediatek,mt7530: make trivial changes Date: Thu, 18 Aug 2022 12:16:22 +0300 Message-Id: <20220818091627.51878-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make trivial changes on the binding. - Update title to include MT7531 switch. - Add me as a maintainer. List maintainers in alphabetical order by first name. - Add description to compatible strings. - Stretch descriptions up to the 80 character limit. - Remove quotes from $ref: "dsa.yaml#". Signed-off-by: Arınç ÜNAL Reviewed-by: Rob Herring --- .../bindings/net/dsa/mediatek,mt7530.yaml | 36 ++++++++++++------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 17ab6c69ecc7..edf48e917173 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -4,12 +4,13 @@ $id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7530 Ethernet switch +title: Mediatek MT7530 and MT7531 Ethernet Switches maintainers: - - Sean Wang + - Arınç ÜNAL - Landen Chao - DENG Qingfang + - Sean Wang description: | Port 5 of mt7530 and mt7621 switch is muxed between: @@ -61,10 +62,21 @@ description: | properties: compatible: - enum: - - mediatek,mt7530 - - mediatek,mt7531 - - mediatek,mt7621 + oneOf: + - description: + Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC + items: + - const: mediatek,mt7530 + + - description: + Standalone MT7531 + items: + - const: mediatek,mt7531 + + - description: + Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + items: + - const: mediatek,mt7621 reg: maxItems: 1 @@ -79,7 +91,7 @@ properties: gpio-controller: type: boolean description: - if defined, MT7530's LED controller will run on GPIO mode. + If defined, MT7530's LED controller will run on GPIO mode. "#interrupt-cells": const: 1 @@ -92,8 +104,8 @@ properties: io-supply: description: Phandle to the regulator node necessary for the I/O power. - See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt - for details for the regulator setup on these boards. + See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for + details for the regulator setup on these boards. mediatek,mcm: type: boolean @@ -110,8 +122,8 @@ properties: resets: description: - Phandle pointing to the system reset controller with line index for - the ethsys. + Phandle pointing to the system reset controller with line index for the + ethsys. maxItems: 1 patternProperties: @@ -148,7 +160,7 @@ required: - reg allOf: - - $ref: "dsa.yaml#" + - $ref: dsa.yaml# - if: required: - mediatek,mcm From patchwork Thu Aug 18 09:16:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1667611 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=CVZZLg4C; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M7fRj1Bwcz1ygq for ; Thu, 18 Aug 2022 19:17:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235068AbiHRJRb (ORCPT ); Thu, 18 Aug 2022 05:17:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229986AbiHRJRb (ORCPT ); Thu, 18 Aug 2022 05:17:31 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 480D867447; Thu, 18 Aug 2022 02:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660814211; cv=none; d=zohomail.com; s=zohoarc; b=iSK5aEHEz2NKsaTUHblmGN+Z5pVtKSH8OgDzOFj90fAKga+dH50mWMB9+qQ7wUeS8p5Aaq1L93RomIW68+f1aO3raNjWOiQiXvxud03HAW7x9MVD8IoJ/7J35hBQAEVQwMBf6rpDYsrXyuZ280X98RTlrbEdO0URdGE4oQdtIbw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660814211; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=tUPXDCTkwC2zhPMuq078yFzwDdf8nbUXFo0CgcNnnAg=; b=SiwuLfHgKVmz2KSkESTYCsRYuMieBJ3R2/dW6MpFew/z5WE2kcRKBFDiLZko/l27wovFFuW95VJ0jv72wPPShWaRb/+kNwNlDBgcwND4epKAlS8H6IxvFYx1QgeIBNHnlXgQ/S/wItwFP1lxDhrKGhI7BN0q4uR6UUdFMiNUhWg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814211; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=tUPXDCTkwC2zhPMuq078yFzwDdf8nbUXFo0CgcNnnAg=; b=CVZZLg4CvcouhU8MKyUBZAC4OlA5yIlRgBNdecIalutTdo3sCj8ZJvJl/8dGyI+r mcWNof2dn8s2LNljHEV+1TkQ2dEI/9P/g7BoQIlo01pD1aKImlKckIoufMANtE48z6H AcHdkPNQwyAtj4j6EqtOvjzFFREpnqUjNH2Dwu/Q= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1660814210407956.4809054082643; Thu, 18 Aug 2022 02:16:50 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v3 2/6] dt-bindings: net: dsa: mediatek,mt7530: fix reset lines Date: Thu, 18 Aug 2022 12:16:23 +0300 Message-Id: <20220818091627.51878-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org - Fix description of mediatek,mcm. mediatek,mcm is not used on MT7623NI. - Add description for reset-gpios. - Invalidate reset-gpios if mediatek,mcm is used. We cannot use multiple reset lines at the same time. - Invalidate mediatek,mcm if the compatible device is mediatek,mt7531. There is no multi-chip module version of mediatek,mt7531. - Require mediatek,mcm for mediatek,mt7621 as the compatible string is only used for the multi-chip module version of MT7530. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index edf48e917173..4c99266ce82a 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -110,11 +110,15 @@ properties: mediatek,mcm: type: boolean description: - if defined, indicates that either MT7530 is the part on multi-chip - module belong to MT7623A has or the remotely standalone chip as the - function MT7623N reference board provided for. + Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530 + switch is a part of the multi-chip module. reset-gpios: + description: + GPIO to reset the switch. Use this if mediatek,mcm is not used. + This property is optional because some boards share the reset line with + other components which makes it impossible to probe the switch if the + reset line is used. maxItems: 1 reset-names: @@ -165,6 +169,9 @@ allOf: required: - mediatek,mcm then: + properties: + reset-gpios: false + required: - resets - reset-names @@ -182,6 +189,24 @@ allOf: - core-supply - io-supply + - if: + properties: + compatible: + items: + - const: mediatek,mt7531 + then: + properties: + mediatek,mcm: false + + - if: + properties: + compatible: + items: + - const: mediatek,mt7621 + then: + required: + - mediatek,mcm + unevaluatedProperties: false examples: From patchwork Thu Aug 18 09:16:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1667614 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=ZHZGM3qx; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M7fRk4GD5z1ygq for ; Thu, 18 Aug 2022 19:17:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238600AbiHRJRh (ORCPT ); Thu, 18 Aug 2022 05:17:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238208AbiHRJRg (ORCPT ); Thu, 18 Aug 2022 05:17:36 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBE5967CB9; Thu, 18 Aug 2022 02:17:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660814219; cv=none; d=zohomail.com; s=zohoarc; b=EIsC7FHOjXOlY5bTlhQwiggONhG2wvuJkKRV9XDBEvkYkhz5JxGIu7JoFrTwWbWrtbBqCpSkb2ACbC0VG+K8/UdHqwOUwMVu1CR9UCP0aaz39dmRc12NdMf5pn012Oxm1d0Ke7/G7lq7S0OVOJtncq/Jp0kOQhj0zpb+vVbk7sQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660814219; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=X58HP+jpMWyRagRKBKPQuDr9qBshq9q4UxSrLugB3xv4Ee2dqcH6v855wARSKF85Senuw6MlhTF/XiJwGcQYNBEjyJM3KrEnpNgdGoYu7B81xFLViJ/LXJQhgfs2EMdD0zzKtbl94ISNdPvD4l4Nqdigds2fwXSDrTRUBdi82NQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814219; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=H5il8SQXZ0PUGfPI0E3JkFSwueZxe2N6hD1oee9wSV4=; b=ZHZGM3qxhGu1Exq2WOUYd3seDJwPVn1wEaiKdTZMxVHnrKMlKhmrGJf4+2Rjl2La vGc9ZTSCTcT81d+1QmHFv0CRaRcD2zaQZ4um+43E5ZzhlkAPUfdH+PTcQ6R3aojope9 6QhrBnDbpvAWFSx1SvdjysSXhyjHXrg4k0c1t2nA= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1660814217619717.9051921463371; Thu, 18 Aug 2022 02:16:57 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v3 3/6] dt-bindings: net: dsa: mediatek,mt7530: update examples Date: Thu, 18 Aug 2022 12:16:24 +0300 Message-Id: <20220818091627.51878-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the examples on the binding. - Add examples which include a wide variation of configurations. - Make example comments YAML comment instead of DT binding comment. - Add interrupt controller to the examples. Include header file for interrupt. - Change reset line for MT7621 examples. - Pretty formatting for the examples. - Change switch reg to 0. - Change port labels to fit the example, change port 4 label to wan. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 402 +++++++++++++++--- 1 file changed, 347 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 4c99266ce82a..657e162a1c01 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -210,42 +210,111 @@ allOf: unevaluatedProperties: false examples: + # Example 1: Standalone MT7530 - | #include + mdio { #address-cells = <1>; #size-cells = <0>; + switch@0 { compatible = "mediatek,mt7530"; reg = <0>; + reset-gpios = <&pio 33 0>; + core-supply = <&mt6323_vpa_reg>; io-supply = <&mt6323_vemc3v3_reg>; - reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; ethernet-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 2: MT7530 in MT7623AI SoC + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7530"; + reg = <0>; + + mediatek,mcm; + resets = <ðsys MT2701_ETHSYS_MCM_RST>; + reset-names = "mcm"; + + core-supply = <&mt6323_vpa_reg>; + io-supply = <&mt6323_vemc3v3_reg>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; label = "lan3"; }; + port@3 { + reg = <3>; + label = "lan4"; + }; + port@4 { reg = <4>; label = "wan"; @@ -256,85 +325,219 @@ examples: label = "cpu"; ethernet = <&gmac0>; phy-mode = "trgmii"; + fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; }; }; + # Example 3: Standalone MT7531 - | - //Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4. + #include + #include - ethernet { + mdio { #address-cells = <1>; #size-cells = <0>; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; + + switch@0 { + compatible = "mediatek,mt7531"; reg = <0>; - phy-mode = "rgmii"; - fixed-link { - speed = <1000>; - full-duplex; - pause; + reset-gpios = <&pio 54 0>; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; }; }; + }; + + # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs + - | + #include + #include - gmac1: mac@1 { + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1 + - | + #include + #include + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; - phy-mode = "rgmii-txid"; - phy-handle = <&phy4>; + + phy-mode = "rgmii"; + phy-handle = <&example5_ethphy4>; }; - mdio: mdio-bus { + mdio { #address-cells = <1>; #size-cells = <0>; - /* Internal phy */ - phy4: ethernet-phy@4 { + /* MT7530's phy4 */ + example5_ethphy4: ethernet-phy@4 { reg = <4>; }; - mt7530: switch@1f { + switch@0 { compatible = "mediatek,mt7621"; - reg = <0x1f>; - mediatek,mcm; + reg = <0>; - resets = <&rstctrl 2>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan3"; + label = "lan4"; }; - /* Commented out. Port 4 is handled by 2nd GMAC. + /* Commented out, phy4 is muxed to gmac1. port@4 { reg = <4>; - label = "lan4"; + label = "wan"; }; */ @@ -342,7 +545,7 @@ examples: reg = <6>; label = "cpu"; ethernet = <&gmac0>; - phy-mode = "rgmii"; + phy-mode = "trgmii"; fixed-link { speed = <1000>; @@ -355,82 +558,171 @@ examples: }; }; + # Example 6: MT7621: mux external phy to SoC's gmac1 - | - //Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY. + #include + #include ethernet { #address-cells = <1>; #size-cells = <0>; - gmac_0: mac@0 { + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mac@1 { compatible = "mediatek,eth-mac"; - reg = <0>; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&example6_ethphy7>; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* External PHY */ + example6_ethphy7: ethernet-phy@7 { + reg = <7>; + phy-mode = "rgmii"; + }; + + switch@0 { + compatible = "mediatek,mt7621"; + reg = <0>; + + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; - fixed-link { - speed = <1000>; - full-duplex; - pause; + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; }; }; + }; - mdio0: mdio-bus { + # Example 7: MT7621: mux external phy to MT7530's port 5 + - | + #include + #include + + ethernet { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii2_pins>; + + mdio { #address-cells = <1>; #size-cells = <0>; - /* External phy */ - ephy5: ethernet-phy@7 { + /* External PHY */ + example7_ethphy7: ethernet-phy@7 { reg = <7>; + phy-mode = "rgmii"; }; - switch@1f { + switch@0 { compatible = "mediatek,mt7621"; - reg = <0x1f>; - mediatek,mcm; + reg = <0>; - resets = <&rstctrl 2>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; - label = "lan0"; + label = "lan1"; }; port@1 { reg = <1>; - label = "lan1"; + label = "lan2"; }; port@2 { reg = <2>; - label = "lan2"; + label = "lan3"; }; port@3 { reg = <3>; - label = "lan3"; + label = "lan4"; }; port@4 { reg = <4>; - label = "lan4"; + label = "wan"; }; port@5 { reg = <5>; - label = "lan5"; - phy-mode = "rgmii"; - phy-handle = <&ephy5>; + label = "extphy"; + phy-mode = "rgmii-txid"; + phy-handle = <&example7_ethphy7>; }; - cpu_port0: port@6 { + port@6 { reg = <6>; label = "cpu"; - ethernet = <&gmac_0>; - phy-mode = "rgmii"; + ethernet = <&gmac0>; + phy-mode = "trgmii"; fixed-link { speed = <1000>; From patchwork Thu Aug 18 09:16:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1667615 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=dlTHnTnd; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M7fRz2X8cz1ygq for ; Thu, 18 Aug 2022 19:17:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239478AbiHRJRt (ORCPT ); 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mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814225; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=wWNYVGiTjPtPc/6FPyJ0S/2bJSMkD8JLkLPy2T5896U=; b=dlTHnTndnu4TosT6JgT8zIVfKRD+INelJZiD2aq5T8Yi+jpvPE9AJDvP76GawDW5 H0jGH1Kch2CJwcCQm1zmAzJUq+XbmRVet8IPNdYN+w1/+Y2Tga6KXxK00fxg/o9ZIAy cyMmGRK9qCLPSfmc0jaCJ9Vm7LUqM6oOwCsbDNmo= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1660814224598289.3097465535868; Thu, 18 Aug 2022 02:17:04 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v3 4/6] dt-bindings: net: dsa: mediatek,mt7530: define port binding per switch Date: Thu, 18 Aug 2022 12:16:25 +0300 Message-Id: <20220818091627.51878-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define DSA port binding per switch model as each switch model requires different values for certain properties. Remove unnecessary lines as they are already included from the referred dsa.yaml. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 59 ++++++++++++------- 1 file changed, 37 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 657e162a1c01..b6c5cf4e706b 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -130,38 +130,50 @@ properties: ethsys. maxItems: 1 -patternProperties: - "^(ethernet-)?ports$": - type: object +required: + - compatible + - reg +$defs: + mt7530-dsa-port: patternProperties: - "^(ethernet-)?port@[0-9]+$": - type: object - description: Ethernet switch ports - - unevaluatedProperties: false - - properties: - reg: - description: - Port address described must be 5 or 6 for CPU port and from 0 - to 5 for user ports. - - allOf: - - $ref: dsa-port.yaml# - - if: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. + + if: properties: label: items: - const: cpu then: required: - - reg - phy-mode -required: - - compatible - - reg + mt7531-dsa-port: + patternProperties: + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-9]+$": + properties: + reg: + description: + Port address described must be 5 or 6 for CPU port and from + 0 to 5 for user ports. + + if: + properties: + label: + items: + - const: cpu + then: + required: + - phy-mode allOf: - $ref: dsa.yaml# @@ -185,6 +197,7 @@ allOf: items: - const: mediatek,mt7530 then: + $ref: "#/$defs/mt7530-dsa-port" required: - core-supply - io-supply @@ -195,6 +208,7 @@ allOf: items: - const: mediatek,mt7531 then: + $ref: "#/$defs/mt7531-dsa-port" properties: mediatek,mcm: false @@ -204,6 +218,7 @@ allOf: items: - const: mediatek,mt7621 then: + $ref: "#/$defs/mt7530-dsa-port" required: - mediatek,mcm From patchwork Thu Aug 18 09:16:26 2022 Content-Type: text/plain; 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dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814233; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=6WCFNVdLELkDaCKJt4wFLENChRk7qUoEcMMckwo+ZtU=; b=gOezG8XRCN9vBophl5IydUxef5k4lSRImFaKjGrjHc8+wOSCDwsWhhWbMwZwDE7Z aa0Ea9Rfu5G7X3XBcfnG68NFK3JHUadF3IxGbOgBrCHIs74DvlY2r2yvyM3a55MwYa6 mmDxIh5CshjWfvy+cjIta4E/OIz/czEmgsakxGpc= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1660814231021988.2191981946787; Thu, 18 Aug 2022 02:17:11 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v3 5/6] dt-bindings: net: dsa: mediatek,mt7530: define phy-mode for switch models Date: Thu, 18 Aug 2022 12:16:26 +0300 Message-Id: <20220818091627.51878-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define acceptable phy-mode values for the CPU port of mt7530 and mt7531 switches. Remove relevant information from the description of the binding. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 61 +++++++++++++++---- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index b6c5cf4e706b..b36497c4636e 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -49,17 +49,6 @@ description: | * mt7621: phy-mode = "rgmii-txid"; * mt7623: phy-mode = "rgmii"; - CPU-Ports need a phy-mode property: - Allowed values on mt7530 and mt7621: - - "rgmii" - - "trgmii" - On mt7531: - - "1000base-x" - - "2500base-x" - - "rgmii" - - "sgmii" - - properties: compatible: oneOf: @@ -152,6 +141,30 @@ $defs: items: - const: cpu then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - gmii + - mii + - rgmii + else: + properties: + phy-mode: + enum: + - rgmii + - trgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode @@ -172,6 +185,32 @@ $defs: items: - const: cpu then: + if: + properties: + reg: + const: 5 + then: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - rgmii + - sgmii + else: + properties: + phy-mode: + enum: + - 1000base-x + - 2500base-x + - sgmii + + properties: + reg: + enum: + - 5 + - 6 + required: - phy-mode From patchwork Thu Aug 18 09:16:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 1667617 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=arinc9.com header.i=arinc.unal@arinc9.com header.a=rsa-sha256 header.s=zmail header.b=LQTdkQNl; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4M7fSF2L0Tz1ygs for ; Thu, 18 Aug 2022 19:18:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234053AbiHRJSC (ORCPT ); Thu, 18 Aug 2022 05:18:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239083AbiHRJRu (ORCPT ); Thu, 18 Aug 2022 05:17:50 -0400 Received: from sender4-op-o14.zoho.com (sender4-op-o14.zoho.com [136.143.188.14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6242367CBF; Thu, 18 Aug 2022 02:17:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1660814239; cv=none; d=zohomail.com; s=zohoarc; b=cBP8geGX2ylyhP3nABk3rAijRIaQY633+iZ8iexA7hNYJHYmjhjiTpXncvaEHR07kDcXyF4wV5YSgmGkJ4dqBCOH/H0jJp/k/pwowDBsjlJG9B3KGnCyvrtVgCZwLQ/6ZbNtGaJqQRRzTswcqDzN1wuRXqGgaAUuKama1ogusuI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1660814239; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=kCoStLRYCDJomu2FK7JWpgJUoeguj2TGBHb8GnavUkA=; b=SLD1IGXgc8fc8/LwY+fh2QF/AjaBszVct5rdFI2YklD28Ziy53vRDMqaqyQMfJaMDF1p6ok4QBkv0r3tanbRD5/yiAC6JnDEz+BGGoLubACZewWSFH7DwK0vC9Qy0y+kMgyWh5C54k6vmOYSEC9V51ax5gzmXLLxRWjsPsrrwgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1660814239; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=kCoStLRYCDJomu2FK7JWpgJUoeguj2TGBHb8GnavUkA=; b=LQTdkQNlPNElQOBLSFSFZTrpMyGq4/uVD34ACdq/L+U94S3C52Xmr6L/zMrOp2QJ 2YpHDLnYd6n1kUN01D7GPIpR5iQO316B6ib+2mwr7XA1QA5dwYr0hDnZ3QPSlrK2nNv PjQKQ8PGogC82WMXmOO3nDYVWpOamGlpxFsJOals= Received: from arinc9-PC.lan (37.120.152.236 [37.120.152.236]) by mx.zohomail.com with SMTPS id 1660814237710308.04653731142696; Thu, 18 Aug 2022 02:17:17 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Landen Chao , DENG Qingfang , Frank Wunderlich , Luiz Angelo Daros de Luca , Sander Vanheule , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Daniel Golle , erkin.bozoglu@xeront.com, Sergio Paracuellos Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= Subject: [PATCH v3 6/6] dt-bindings: net: dsa: mediatek,mt7530: update binding description Date: Thu, 18 Aug 2022 12:16:27 +0300 Message-Id: <20220818091627.51878-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220818091627.51878-1-arinc.unal@arinc9.com> References: <20220818091627.51878-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the description of the binding. - Describe the switches, which SoCs they are in, or if they are standalone. - Explain the various ways of configuring MT7530's port 5. - Remove phy-mode = "rgmii-txid" from description. Same code path is followed for delayed rgmii and rgmii phy-mode on mtk_eth_soc.c. Signed-off-by: Arınç ÜNAL --- .../bindings/net/dsa/mediatek,mt7530.yaml | 97 ++++++++++++------- 1 file changed, 62 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index b36497c4636e..caecdf224e2b 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -13,41 +13,68 @@ maintainers: - Sean Wang description: | - Port 5 of mt7530 and mt7621 switch is muxed between: - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC - of the SOC. Used in many setups where port 0/4 becomes the WAN port. - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not - connected to external component! - - Port 5 modes/configurations: - 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd - GMAC of the SOC. - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd - GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. - It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode - and RGMII delay. - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. - Port 5 becomes an extra switch port. - Only works on platform where external phy TX<->RX lines are swapped. - Like in the Ubiquiti ER-X-SFP. - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. - Currently a 2nd CPU port is not supported by DSA code. - - Depending on how the external PHY is wired: - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch - 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as - a ethernet port. But can't interface to the 2nd GMAC. - - Based on the DT the port 5 mode is configured. - - Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. - phy-mode must be set, see also example 2 below! - * mt7621: phy-mode = "rgmii-txid"; - * mt7623: phy-mode = "rgmii"; + There are two versions of MT7530, standalone and in a multi-chip module. + + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. + + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs + and the switch registers are directly mapped into SoC's memory map rather than + using MDIO. The DSA driver currently doesn't support this. + + There is only the standalone version of MT7531. + + Port 5 on MT7530 has got various ways of configuration. + + For standalone MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC + which port 5 is wired to. Usually used for connecting the wan port + directly to the CPU to achieve 2 Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the + compatible string and the reg must be 1. So, for now, only gmac1 of an + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. + Check out example 5 for a similar configuration. + + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. + Check out example 7 for a similar configuration. + + For multi-chip module MT7530: + + - Port 5 can be used as a CPU port. + + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. + Usually used for connecting the wan port directly to the CPU to achieve 2 + Gbps routing in total. + + The driver looks up the reg on the ethernet-phy node which the phy-handle + property refers to on the gmac node to mux the specified phy. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 5. + + - In case of an external phy wired to gmac1 of the SoC, port 5 must not be + enabled. + + In case of muxing PHY 0 or 4, the external phy must not be enabled. + + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. + Check out example 6. + + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. + The external phy must be wired TX to TX to gmac1 of the SoC for this to + work. Ubiquiti EdgeRouter X SFP is wired this way. + + Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. + + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. + Check out example 7. properties: compatible: