From patchwork Thu Mar 1 01:15:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruslan Bilovol X-Patchwork-Id: 879782 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Y6I9OZfE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zsW4q1s6Sz9rxx for ; Thu, 1 Mar 2018 22:52:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DF3D8C21F52; Thu, 1 Mar 2018 11:51:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D5C7EC21C3F; Thu, 1 Mar 2018 11:51:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 65430C21C2F; Thu, 1 Mar 2018 01:16:02 +0000 (UTC) Received: from mail-lf0-f68.google.com (mail-lf0-f68.google.com [209.85.215.68]) by lists.denx.de (Postfix) with ESMTPS id CE2F3C21C3F for ; Thu, 1 Mar 2018 01:16:01 +0000 (UTC) Received: by mail-lf0-f68.google.com with SMTP id q69so6352880lfi.10 for ; Wed, 28 Feb 2018 17:16:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=a6b/CTJyQ+mv/Ns6K3WsvkdLoa/HD0ibWXQaqHWm67E=; b=Y6I9OZfE9TVCHHNn5IU2Z/wMcPas1BxSCFsf6TFLMW9/AT5ynH4d1ue/ALQomSq0CL EKyfxbuLpxGvW+lLqKLRDi2AWI89nS5Oq2ZCIsfQNV1reKMjfnPsXbCkuVcPtSsCcLaM j8KW4Wq4OcXfg0kbAQpVuutz9ryn3bq1jZRmLv+HJz0Q+RwCje/SzGrlGFR9aglTdg7x MgJrVzK/r5iqvD3RYn4DGpsu2P6jRdIM0DdNo6QV9zjWyDdedHCTRwX4Zy6/4a5iPhTW k6V1EI1LX59DcSo39QSlv+eQ/zHN/hRtYghXi+d+TqndSOUc7V8nunZibRmV4+555gul akSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=a6b/CTJyQ+mv/Ns6K3WsvkdLoa/HD0ibWXQaqHWm67E=; b=MtKdrDPUwHuhslK8jaDYOQUify1Fxxs4izBbRu8h74jag+FJEaXFVR4RRkNlCPPtP6 Khh/y5bwoRSUXfJhkGnsI2LBwrhR5vQPoBv6C6B1HfmjvfGdyR5dYs7XGLkuioWnr63t Ctsy0Y5VQJVC1Iuwm5XHyfvgxm7seWVy54ij1voITZbsN3aORgq3Tx4nmPo59WXSGavv LKapnuRdh20d2D45rmM1E3eD+dDUrRdZ0KFEq+/iUSHWe6MamwVx4xktzFjCKEedYnnN nE6nyeBWU+4K094DMSc8pWDHvJVSQDSs3hnmy1gCxBBpC6PaXyZFYBWgD3bwX5zUUqlh /caA== X-Gm-Message-State: APf1xPBRrItaCjQmVYMOJL3Au5gOnRBF3eU6Z8arNg5PHaiZtzAr/EGD Pkf/AeQ+qiUIMaRfz56q5xwUcoeghe8= X-Google-Smtp-Source: AG47ELvAJVIKKuPaKA7cGhpQFFj4Y7k4/A91pMGENG5KiLRYMHcer97oiTm1FgUoojPBfpSDh06sUQ== X-Received: by 10.46.29.23 with SMTP id d23mr44711ljd.7.1519866960814; Wed, 28 Feb 2018 17:16:00 -0800 (PST) Received: from localhost ([62.216.61.51]) by smtp.gmail.com with ESMTPSA id i15sm631255lfj.8.2018.02.28.17.15.59 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 28 Feb 2018 17:16:00 -0800 (PST) From: Ruslan Bilovol To: u-boot@lists.denx.de, Tom Rini Date: Thu, 1 Mar 2018 03:15:48 +0200 Message-Id: <1519866948-25614-1-git-send-email-ruslan.bilovol@gmail.com> X-Mailer: git-send-email 1.9.1 X-Mailman-Approved-At: Thu, 01 Mar 2018 11:51:10 +0000 Cc: Marek Vasut , Roger Quadros Subject: [U-Boot] [PATCH] watchdog: omap_wdt: improve watchdog reset path X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove busy looping during watchdog reset. Each polling of W_PEND_WTGR bit ("finish posted write") after watchdog reset takes 120-140us on BeagleBone Black board. Current U-Boot code has watchdog resets in random places and often there is situation when watchdog is reset few times in a row in nested functions. This adds extra delays and slows the whole system. Instead of polling W_PEND_WTGR bit, we skip watchdog reset if the bit is set. Anyway, watchdog is in the middle of reset *right now*, so we can just return. This noticeably increases performance of the system. Below are some measurements on BBB: - DFU upload over USB 15% faster - fastboot image upload 3x times faster - USB ep0 transfers with 4k packets 20% faster Signed-off-by: Ruslan Bilovol Tested-by: Sam Protsenko Reviewed-by: Lokesh Vutla Reviewed-by: Lukasz Majewski Tested-by: Alex Kiernan --- drivers/watchdog/omap_wdt.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7b1f429..d724c96 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -53,16 +53,25 @@ void hw_watchdog_reset(void) { struct wd_timer *wdt = (struct wd_timer *)WDT_BASE; - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) - ; + /* + * Somebody just triggered watchdog reset and write to WTGR register + * is in progress. It is resetting right now, no need to trigger it + * again + */ + if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) + return; wdt_trgr_pattern = ~wdt_trgr_pattern; writel(wdt_trgr_pattern, &wdt->wdtwtgr); - /* wait for posted write to complete */ - while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR)) - ; + /* + * Don't wait for posted write to complete, i.e. don't check + * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to + * WTGR register outside of this func, and if entering it + * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset + * was just triggered. This prevents us from wasting time in busy + * polling of WDT_WWPS_PEND_WTGR bit. + */ } static int omap_wdt_set_timeout(unsigned int timeout)