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Wed, 28 Feb 2018 16:47:30 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Wed, 28 Feb 2018 16:47:29 +0100 From: Ludovic Barre To: Ulf Hansson , Rob Herring Subject: [PATCH V2 3/5] ARM: dts: stm32: add sdmmc support for stm32h743 Date: Wed, 28 Feb 2018 16:47:22 +0100 Message-ID: <1519832844-28068-4-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519832844-28068-1-git-send-email-ludovic.Barre@st.com> References: <1519832844-28068-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-28_08:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180228_074746_182065_63519F5C X-CRM114-Status: GOOD ( 11.12 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [91.207.212.93 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Torgue , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Ludovic Barre , Maxime Coquelin , Gerald Baeza , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Ludovic Barre This patch adds sdmmc support for stm32h743. 2×SD/SDIO/MMC interfaces (up to 125 MHz) Signed-off-by: Ludovic Barre --- arch/arm/boot/dts/stm32h743.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index bbfcbac..5e85538 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -217,6 +217,19 @@ }; }; + sdmmc2: sdmmc@48022400 { + compatible = "st,stm32h7-sdmmc"; + reg = <0x48022400 0x400>; + reg-names = "sdmmc"; + interrupts = <124>; + clocks = <&rcc SDMMC2_CK>; + resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <125000000>; + status = "disabled"; + }; + mdma1: dma@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; @@ -227,6 +240,19 @@ dma-requests = <32>; }; + sdmmc1: sdmmc@52007000 { + compatible = "st,stm32h7-sdmmc"; + reg = <0x52007000 0x1000>; + reg-names = "sdmmc"; + interrupts = <49>; + clocks = <&rcc SDMMC1_CK>; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <125000000>; + status = "disabled"; + }; + lptimer2: timer@58002400 { #address-cells = <1>; #size-cells = <0>;