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[2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:18 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:13 +0100 Message-Id: <87dbe541bbacbe1cbdcacec6d1fa4cbf67585a0d.1519589817.git.yann.morin.1998@free.fr> X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Nothing fancy, just a plain Cortex-M, armv7-M core... Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index b05e83e33c..67f8a16737 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -241,6 +241,11 @@ config BR2_cortex_m4 bool "cortex-M4" select BR2_ARM_CPU_HAS_THUMB2 select BR2_ARM_CPU_ARMV7M +config BR2_cortex_m7 + bool "cortex-M7" + select BR2_ARM_CPU_HAS_THUMB2 + select BR2_ARM_CPU_ARMV7M + select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 endif # !BR2_ARCH_IS_64 comment "armv8 cores" @@ -716,6 +721,7 @@ config BR2_GCC_TARGET_CPU # armv7m default "cortex-m3" if BR2_cortex_m3 default "cortex-m4" if BR2_cortex_m4 + default "cortex-m7" if BR2_cortex_m7 # armv8a default "cortex-a32" if BR2_cortex_a32 default "cortex-a35" if BR2_cortex_a35 From patchwork Sun Feb 25 20:18:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yann E. MORIN" X-Patchwork-Id: 877629 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=busybox.net (client-ip=140.211.166.133; helo=hemlock.osuosl.org; envelope-from=buildroot-bounces@busybox.net; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=free.fr Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MPAfcsSA"; dkim-atps=neutral Received: from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zqGVw715Rz9s2S for ; Mon, 26 Feb 2018 07:18:32 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id 6740887520; Sun, 25 Feb 2018 20:18:29 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hnDms2pO8PSw; Sun, 25 Feb 2018 20:18:28 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by hemlock.osuosl.org (Postfix) with ESMTP id 0677F87460; Sun, 25 Feb 2018 20:18:28 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by ash.osuosl.org (Postfix) with ESMTP id D00091CE447 for ; Sun, 25 Feb 2018 20:18:25 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id C94DB85E8D for ; Sun, 25 Feb 2018 20:18:25 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qcanBqIC6Xyf for ; Sun, 25 Feb 2018 20:18:24 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by fraxinus.osuosl.org (Postfix) with ESMTPS id F2BF885E8E for ; Sun, 25 Feb 2018 20:18:22 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id z81so13703357wmb.4 for ; Sun, 25 Feb 2018 12:18:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=PAGkrnt73lBGHNMOI1MAliUnpWGCFsV2XVvFyTPVt2M=; b=MPAfcsSAgRcDqJsnRTsY1P0PNqHfCIPXjCVHAtVy9MX/mbKEkpxGOuj3UuVL17VE9J hPunnl5Rvez/NyEbbI0CT49+VOOmi32u8WWJQAhuY5TW8p5+z3BgNVizxTY0+wxL+o5n mcNaSNi9dR0MZAcryvbwrwyNaHkw418GOLVzU0vHrOSBgo6Kk3wKY/KdJtghp/K91mcl jqTbiu4eC/IG4JsnAk+zw2wrQrBJvqSDWelRHwtutxYnNbZszSoI6CxxlN5kpensTatr pNYFifZACPL8up3Bs8aH3NrITjMqm120MoioMUpr/fykQp8kMdLnJAMWXtuSrt1lwNVx UvnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=PAGkrnt73lBGHNMOI1MAliUnpWGCFsV2XVvFyTPVt2M=; b=m2YcbKHl3/0y7rHj8ujJrAJGxkkjpFmGEehKRTL+G3xP19m7JwdGIG/YCYUBEnZ8mc qLDG2dUyRF12zg5v5wg7QZDsjyWzmdyhOMics2VFqtvLauymm3vaBF9+WmxLK1PFMM38 SP9NtenzXhQg6XOrMMZYEWCM4xMazPD5NkXk9JaDVFs/KhbrSW2V4rEBH/+6883mhmmw HrbEgWtoEhOR76Q5R8mySeXN7rCIz8XKfeTUYGVL52bv7BS7PjEllYUfvifQrk8P346l 5zhsNvTUsHny5d4qa6c8jY5qn5xeFCeDBRCH4RCPgQpFEelE79LoDhDGDM/ihUKWIeIF /bUw== X-Gm-Message-State: APf1xPBl7M7umhDcV+cI5qPhqBeray81LksguR2AnBcQZxpoERUwvEPD dY9gtvgmPrMAD0V1KCdzZgEiYA== X-Google-Smtp-Source: AG47ELsXb7IHW52VXS4Aqr0HOzUbgU/LRyP9hbrcVyNYzXuwESgTHzq+6hB9ZuPGTV3jdPcIONCZfQ== X-Received: by 10.28.4.81 with SMTP id 78mr6286035wme.22.1519589901273; Sun, 25 Feb 2018 12:18:21 -0800 (PST) Received: from scaer.bzh.lan (2a01cb0886107300a556795e0851f8aa.ipv6.abo.wanadoo.fr. [2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:20 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:14 +0100 Message-Id: <5ef50865f7d01e80a46e4f95c95916a6744d8250.1519589817.git.yann.morin.1998@free.fr> X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 2/6] arch/arm: introduce generic FPU internal option X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Currently, we consider that any VFP FPU is a superset of VFPv2, and thus we use VFPv2 as a way to detect that a VFP is used. However, for Cortex-M cores, the optional FPU is not a superset of VFPv2; it is even not a VFP [0]. As a consequence, we can no longer consider VFPv2 as a indication that an FPU is present. So, we introduce two new internal options, BR2_ARM_CPU_MAYBE_HAS_FPU and BR2_ARM_CPU_HAS_FPU, which we use to consider the presence of an FPU. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 67f8a16737..89db5fad08 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -6,12 +6,21 @@ config BR2_ARM_CPU_HAS_NEON config BR2_ARM_CPU_MAYBE_HAS_NEON bool +# For some cores, the FPU is optional +config BR2_ARM_CPU_MAYBE_HAS_FPU + bool + +config BR2_ARM_CPU_HAS_FPU + bool + # for some cores, VFPv2 is optional config BR2_ARM_CPU_MAYBE_HAS_VFPV2 bool + select BR2_ARM_CPU_MAYBE_HAS_FPU config BR2_ARM_CPU_HAS_VFPV2 bool + select BR2_ARM_CPU_HAS_FPU # for some cores, VFPv3 is optional config BR2_ARM_CPU_MAYBE_HAS_VFPV3 @@ -450,7 +459,7 @@ config BR2_ARM_ENABLE_NEON config BR2_ARM_ENABLE_VFP bool "Enable VFP extension support" - depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 + depends on BR2_ARM_CPU_MAYBE_HAS_FPU select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2 @@ -462,7 +471,7 @@ config BR2_ARM_ENABLE_VFP choice prompt "Target ABI" depends on BR2_arm || BR2_armeb - default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2 + default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU default BR2_ARM_EABI help Application Binary Interface to use. The Application Binary @@ -496,7 +505,7 @@ config BR2_ARM_EABI config BR2_ARM_EABIHF bool "EABIhf" - depends on BR2_ARM_CPU_HAS_VFPV2 + depends on BR2_ARM_CPU_HAS_FPU help The EABIhf is an extension of EABI which supports the 'hard' floating point model. This model uses the floating point @@ -520,7 +529,7 @@ choice default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2 - default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2 + default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU config BR2_ARM_SOFT_FLOAT bool "Soft float" From patchwork Sun Feb 25 20:18:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yann E. 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[2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:21 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:15 +0100 Message-Id: <3d450412ff52439ace479474eddc5e90964e2626.1519589817.git.yann.morin.1998@free.fr> X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 3/6] arch/arm: add option for FPv4 FPU X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" The FPv4-SP FPU is a single-precision FPU with 16 double registers [0] [1]. It is only available for cortex-m4 cores, and is known to gcc as fpv4-sp-d16 (note that there is no leading 'v') since gcc-4.5 [2]. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 [1] https://developer.arm.com/docs/ddi0439/latest/floating-point-unit [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=639cb7b789a54bf78d6ae5e2644450f5eb1837a6 Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 89db5fad08..b063ee33fd 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -40,6 +40,15 @@ config BR2_ARM_CPU_HAS_VFPV4 bool select BR2_ARM_CPU_HAS_VFPV3 +# FPv4 is always optional +config BR2_ARM_CPU_MAYBE_HAS_FPV4 + bool + select BR2_ARM_CPU_MAYBE_HAS_FPU + +config BR2_ARM_CPU_HAS_FPV4 + bool + select BR2_ARM_CPU_HAS_FPU + config BR2_ARM_CPU_HAS_FP_ARMV8 bool select BR2_ARM_CPU_HAS_VFPV4 @@ -460,6 +469,7 @@ config BR2_ARM_ENABLE_NEON config BR2_ARM_ENABLE_VFP bool "Enable VFP extension support" depends on BR2_ARM_CPU_MAYBE_HAS_FPU + select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2 @@ -526,6 +536,7 @@ endchoice choice prompt "Floating point strategy" default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8 + default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2 @@ -636,6 +647,14 @@ config BR2_ARM_FPU_NEON_VFPV4 example on Cortex-A5 and Cortex-A7, support for VFPv4 and NEON is optional. +config BR2_ARM_FPU_FPV4D16 + bool "FPv4-D16" + depends on BR2_ARM_CPU_HAS_FPV4 + help + This option allows to use the FPv4-SP (single precision) + floating point unit, as available in some ARMv7m processors + (Cortex-M4). + config BR2_ARM_FPU_FP_ARMV8 bool "FP-ARMv8" depends on BR2_ARM_CPU_HAS_FP_ARMV8 @@ -769,6 +788,7 @@ config BR2_GCC_TARGET_FPU default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16 default "neon" if BR2_ARM_FPU_NEON default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4 + default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16 default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8 default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8 From patchwork Sun Feb 25 20:18:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yann E. 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[2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:23 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:16 +0100 Message-Id: X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 4/6] arch/arm: add options for FPv5 FPU X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Contrary to its older brother, the FPv5 comes in two flavours; single- and double-precision [0] [1]. the two variants are only available for cortex-m7 cores, and the two variants are known to gcc as fpv5-sp-d16 and fpv5-d16, respectively, since gcc-5 [2]. [0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M7 [1] https://developer.arm.com/docs/ddi0489/latest/floating-point-unit [2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a076f99fa702deac764f6e0441b9435ad999f521 Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index b063ee33fd..8fd11cc157 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -49,6 +49,15 @@ config BR2_ARM_CPU_HAS_FPV4 bool select BR2_ARM_CPU_HAS_FPU +# FPv5 is always optional +config BR2_ARM_CPU_MAYBE_HAS_FPV5 + bool + select BR2_ARM_CPU_MAYBE_HAS_FPV4 + +config BR2_ARM_CPU_HAS_FPV5 + bool + select BR2_ARM_CPU_HAS_FPV4 + config BR2_ARM_CPU_HAS_FP_ARMV8 bool select BR2_ARM_CPU_HAS_VFPV4 @@ -469,6 +478,7 @@ config BR2_ARM_ENABLE_NEON config BR2_ARM_ENABLE_VFP bool "Enable VFP extension support" depends on BR2_ARM_CPU_MAYBE_HAS_FPU + select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5 select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3 @@ -536,6 +546,7 @@ endchoice choice prompt "Floating point strategy" default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8 + default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5 default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3 @@ -655,6 +666,30 @@ config BR2_ARM_FPU_FPV4D16 floating point unit, as available in some ARMv7m processors (Cortex-M4). +config BR2_ARM_FPU_FPV5D16 + bool "FPv5-D16" + depends on BR2_ARM_CPU_HAS_FPV5 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 + help + This option allows to use the FPv5-SP (single precision) + floating point unit, as available in some ARMv7m processors + (Cortex-M7). + + Note that if you want binary code that works on the earlier + Cortex-M4, you should instead select FPv4-D16. + +config BR2_ARM_FPU_FPV5DPD16 + bool "FPv5-DP-D16" + depends on BR2_ARM_CPU_HAS_FPV5 + select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 + help + This option allows to use the FPv5-DP (double precision) + floating point unit, as available in some ARMv7m processors + (Cortex-M7). + + Note that if you want binary code that works on the earlier + Cortex-M4, you should instead select FPv4-D16. + config BR2_ARM_FPU_FP_ARMV8 bool "FP-ARMv8" depends on BR2_ARM_CPU_HAS_FP_ARMV8 @@ -789,6 +824,8 @@ config BR2_GCC_TARGET_FPU default "neon" if BR2_ARM_FPU_NEON default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4 default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16 + default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16 + default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16 default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8 default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8 From patchwork Sun Feb 25 20:18:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yann E. 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[2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:24 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:17 +0100 Message-Id: X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 5/6] arch/arm: cortex-m4 may have an FPv4 FPU X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 8fd11cc157..7c0fcacc36 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -267,6 +267,7 @@ config BR2_cortex_m3 config BR2_cortex_m4 bool "cortex-M4" select BR2_ARM_CPU_HAS_THUMB2 + select BR2_ARM_CPU_MAYBE_HAS_FPV4 select BR2_ARM_CPU_ARMV7M config BR2_cortex_m7 bool "cortex-M7" From patchwork Sun Feb 25 20:18:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yann E. 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[2a01:cb08:8610:7300:a556:795e:851:f8aa]) by smtp.gmail.com with ESMTPSA id l3sm5633256wml.47.2018.02.25.12.18.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 25 Feb 2018 12:18:26 -0800 (PST) From: "Yann E. MORIN" To: buildroot@buildroot.org Date: Sun, 25 Feb 2018 21:18:18 +0100 Message-Id: X-Mailer: git-send-email 2.14.1 In-Reply-To: References: Subject: [Buildroot] [PATCH 6/6] arch/arm: cortex-m7 may have a FPv5 FPU X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.24 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Yann E. MORIN" , Richard Braun MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" Signed-off-by: "Yann E. MORIN" --- arch/Config.in.arm | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 7c0fcacc36..640ad93f8b 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -272,6 +272,7 @@ config BR2_cortex_m4 config BR2_cortex_m7 bool "cortex-M7" select BR2_ARM_CPU_HAS_THUMB2 + select BR2_ARM_CPU_MAYBE_HAS_FPV5 select BR2_ARM_CPU_ARMV7M select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 endif # !BR2_ARCH_IS_64