From patchwork Thu Jun 9 09:29:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1641086 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xEq2Ezz6; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LJf2F1ZQgz9s2R for ; Thu, 9 Jun 2022 19:29:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240451AbiFIJ3y (ORCPT ); Thu, 9 Jun 2022 05:29:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233025AbiFIJ3w (ORCPT ); Thu, 9 Jun 2022 05:29:52 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0219267CC9 for ; Thu, 9 Jun 2022 02:29:47 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id gl15so32407560ejb.4 for ; Thu, 09 Jun 2022 02:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oQCEzz12ukJcqXabLCIweZqpeRWMz2frfEfSdC7n6WI=; b=xEq2Ezz6CrU830NkrO8MBbZYSvUHIf31/ROvyYHt1UvRN8h7Rk8UAddUikfjj4Pe98 GKB6iI9LQgq4j8uKqQuLWc3b33FkPKRG5Ied+Sk7gBDribwOGs+EC273NPCD0pYtNa/O 0ifY1cDH2fRcHcpi1/Hy5//iyDMd/b1mmwoS69RXU2WtkS8e3JyNtlA5UFgv5B6hhhGk m2aaai2OcDNnI5hunNZa8tOShkHGNb7TG/fxeZu5OrCYR3AcyAonUAIxPwfV4nPX4APO MWO8unOcxkPzhRYGZ3R3hhLY70lXXL/TdkPwzLnPivDx4wbmQjaGtz09bhkm58ElmTdi JzbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oQCEzz12ukJcqXabLCIweZqpeRWMz2frfEfSdC7n6WI=; b=4OW87gTjIP8BhL0Tyw4aoDqS4xruC7ubRm/BH4pqrMWt9UX3A8qf4/FaOQ+OCSqkpV lUNFk0URN7gm3P9udnF/m23cgIg1khoWNP3IEViv2DzrwYg+1ZoaWLM0dmCvry2mTSDv CyvQe6a6Gr+f3wdolf36XDVUzI9/kJvtgyrF3+eKpbNHwCrOptkt2gB+swT00c20a9/l Luxzti6ifBhQa7M1tFrSBkOrIfgijwRJUCGSSxtI9lDroDGsaT5O611C3CL4I1gDfnlB J9jg9Qctlrd4gKTJgDuFBR5ZeYFOZvp25ahusLLk9v4+Y7NwQuJM3RI0kDqR1+cRXHFp JxZg== X-Gm-Message-State: AOAM5305GSgVsH5zUfhCoRIBSjXCi8h7PkZAkOYH/OfEEMlVXKdnv/rj 6N1hnePrQh/tOqZg7KHymS0HllbNLvZSfK00 X-Google-Smtp-Source: ABdhPJwk+xmn5SurY9iYay63P74ewXYNsm5jhUhp81Z4B4384bJPHBOD2iMAck8Efwj0WS+WPX5O1g== X-Received: by 2002:a17:907:62a1:b0:6da:7952:d4d2 with SMTP id nd33-20020a17090762a100b006da7952d4d2mr34722809ejc.260.1654766987446; Thu, 09 Jun 2022 02:29:47 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:46 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Dmitry Baryshkov Subject: [PATCH v5 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Thu, 9 Jun 2022 11:29:37 +0200 Message-Id: <20220609092940.304740-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reported-by: kernel test robot Reviewed-by: Rob Herring --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Thu Jun 9 09:29:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1641087 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=MvqSF2C/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LJf2K12ZYz9s2R for ; Thu, 9 Jun 2022 19:30:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233300AbiFIJ37 (ORCPT ); Thu, 9 Jun 2022 05:29:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229771AbiFIJ3z (ORCPT ); Thu, 9 Jun 2022 05:29:55 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA4026A918 for ; Thu, 9 Jun 2022 02:29:51 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id v1so35590333ejg.13 for ; Thu, 09 Jun 2022 02:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tk8xKk87g7KBs4W4kVam7IN5r8rBhn+IuNaPzOCvkIw=; b=MvqSF2C/gpuiIsR1eSf/uq4UboM18mebtjm1gBpJ5iOX/w4rxrtA83bZjtI+3/HuJ9 KYpuNrbqgXjb/by+hio9F2JJ5FFH5+MaDGxzBiFkk8ygc/LJqku7HGTNjvWwOaDUP/Nr J6CFxYLVN5YqolZiESku49SJeTyrNetTd64UNzPwc6Ai5bVxlfkARV0LBFu/wkpS5klf F0/vw3gQ9KO1xmuiTVb9gYfLbSLdSl2PigW7yE7ZKPJ3In8+z/XKUMUAoDFCaBBsxUid CTfoX3+UGjpD/zllGo0iOafyyux1JDQkzo7RUywolWpQ0as681piWLWIYGyuqReaNpSQ MQqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tk8xKk87g7KBs4W4kVam7IN5r8rBhn+IuNaPzOCvkIw=; b=J9L0wl4gDwcjoTCdyqx83TGIkSYfjtmIgABzm/Ft3y5O/2A14sxNWH4O+709NfHkrJ gN4KDAmtQq1NH5g/TcYaxTqiICuvDNlhpMfrHqcpfUcHT02LZtI3wPLHaEbFvAkHQt18 vDAyXo31XtP1HjnUhxEbGYODW+inuebKlVWrWPBQGnHLd8wXkqtwDGJRiVZ57SV+Ekx5 vvWbVdi8cE84qoor9ydgY9v2XPY84Tu8XKnu1eVG1OkzCiXwpOPiZc9PBaApRd+azwRo PZzPdI5Dtaj5icvQ20Fl8JUHNhef0ITOcGaxOtPpv+Nem6KAuBjM/EfWhCfpjaHNgjlj +F6w== X-Gm-Message-State: AOAM533kljwUpx6tlVYVoqTgLx8AKrsspmeYBaU+6ZFL+fi6pamD1SB0 E5JPLnE69Awz505zCu2LkYUTKA== X-Google-Smtp-Source: ABdhPJx40CklTvHnvZRbXzyT8+3O05/kofWZm+QaUbSdhNWpUItOQa9FbvmrnCaduxCob2rME6ki6Q== X-Received: by 2002:a17:906:5d14:b0:6ff:4a45:11de with SMTP id g20-20020a1709065d1400b006ff4a4511demr34179801ejt.576.1654766991526; Thu, 09 Jun 2022 02:29:51 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id l9-20020a50cbc9000000b0042ab87ea713sm8653417edi.22.2022.06.09.02.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 02:29:50 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Rob Herring Subject: [PATCH v5 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Thu, 9 Jun 2022 11:29:39 +0200 Message-Id: <20220609092940.304740-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220609092940.304740-1-robert.foss@linaro.org> References: <20220609092940.304740-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add sm8350 DISPCC bindings, while these bindings are similar to the sm8x50 bindings, the way clocks are represented has changed in ABI incompatible ways. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- Changes since v2 - Add my SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v4 - Add RB - Rob .../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++++++++++++++++++ .../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +- .../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 3 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml new file mode 100644 index 000000000000..d7e8739cab32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SM8350 + +maintainers: + - Robert Foss + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SM8350. + + See also: + dt-bindings/clock/qcom,dispcc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-dispcc + + clocks: + items: + - description: Board XO source + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: Link clock from DPTX1 PHY + - description: VCO DIV clock from DPTX1 PHY + - description: Link clock from DPTX2 PHY + - description: VCO DIV clock from DPTX2 PHY + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from EDP PHY + - description: VCO DIV clock from EDP PHY + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dp_phy 0>, + <&dp_phy 1>, + <&dptx1_phy 0>, + <&dptx1_phy 1>, + <&dptx2_phy 0>, + <&dptx2_phy 1>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..951fe2ecb7a6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250. See also: dt-bindings/clock/qcom,dispcc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file