From patchwork Thu Jun 2 21:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=UiMz+ICI; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfxV0tpyz9s5V for ; Fri, 3 Jun 2022 07:57:00 +1000 (AEST) Received: from localhost ([::1]:56104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsoL-0004Mu-C2 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:56:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsge-0004QH-CB for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:00 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:53061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgb-0008U5-5j for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:00 -0400 Received: by mail-pj1-x1033.google.com with SMTP id gd1so6024314pjb.2 for ; Thu, 02 Jun 2022 14:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AP39jqbPiQO8vlhvr3vURJ9OZT2UOimjCnaJk3rF7/M=; b=UiMz+ICIQZL2tXgVEHPvffEvf6NhyTrNcFana0UdkZRLIaTYWS2USJ9x7XtlppAs0x dYgwTK7GrS9xRCAlK4d4edSxTl3JbEnT/08b8T9iryl+W6Kb8vtefmBK8zZPf0HWE0ja n3hySf3C/5lzeMzFOdwP/OQPS87eovFyQru3gJimQG7Wh2Dha4iFF4H+8ChP3tcZfLSw i0J4NgRkhdi93Y73c1YpVc3DGPa+H2Py612xoOl/+dLwdRHicKXUaPalw7BLuMe+K3Br I/Xvj1paETT5bNQ4WxJAlqihxWimlNLU4RbbVNZwusLHA7YON81xbj7BdxMIGSU5W6Kh qx2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AP39jqbPiQO8vlhvr3vURJ9OZT2UOimjCnaJk3rF7/M=; b=SbfRysWFkCJEVxjUFeFZ9R4wSXfaVawbHp5v4kqDfyCsH9TxeuXvbuGpYtVbzzzxu9 D7r7o3/9wUpdkIFaFo9NChRGUUkGz30cRusrcuQN0Smoiec0fUCEXwQ+1FL5wbOg2BYs vtP7FI2NWB8FchVmaq9AuvGlkSIWh0dLLJA5PcWE5zLp4qIyIPKscjhFyh4U2js7smCl OZzASrjFHTNQiiHdH/KomWiSD4NtyN8cIJ1lLKZ7cRkx5xraCaa4fH5Vbl79o+NPgIAR dflnNFaWTWBeVhi0OiOZSSbVLjFbimMj8rz4kgX3XClv5DEHT9qvUQx15/UXTqV4wI2P Qmiw== X-Gm-Message-State: AOAM532ZlOq2nSAbaZNsIIKzo/3MJuXOOnW47T3AxsjRRaklXpI5kadd kugmJdRKZjB3b7YHB1qWAoQ5fJBlewehsA== X-Google-Smtp-Source: ABdhPJzGoqd7Hxm7KLjGxzCKEt97OFZCyzwwbAmxgsMXRsK1vYxg6pLUTSzKIoXGeJiI3wEfUTYSnQ== X-Received: by 2002:a17:90b:3510:b0:1e0:b82:7558 with SMTP id ls16-20020a17090b351000b001e00b827558mr42390763pjb.21.1654206535719; Thu, 02 Jun 2022 14:48:55 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 01/71] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL Date: Thu, 2 Jun 2022 14:47:43 -0700 Message-Id: <20220602214853.496211-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Renamed from SVE_LEN to VL. --- target/arm/cpu.h | 3 ++- target/arm/translate-a64.h | 2 +- target/arm/translate.h | 2 +- target/arm/helper.c | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate-sve.c | 2 +- 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5da..015ce12fe2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3241,7 +3241,8 @@ FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ */ FIELD(TBFLAG_A64, TBII, 0, 2) FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) -FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) +/* The current vector length, either NVL or SVL. */ +FIELD(TBFLAG_A64, VL, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f2e8ee0ee1..dbc917ee65 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -104,7 +104,7 @@ static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) /* Return the byte size of the "whole" vector register, VL / 8. */ static inline int vec_full_reg_size(DisasContext *s) { - return s->sve_len; + return s->vl; } bool disas_sve(DisasContext *, uint32_t); diff --git a/target/arm/translate.h b/target/arm/translate.h index 9f0bb270c5..f473a21ed4 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,7 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ - int sve_len; /* SVE vector length in bytes */ + int vl; /* current vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..960899022d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13696,7 +13696,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, zcr_len = sve_zcr_len_for_el(env, el); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); + DP_TBFLAG_A64(flags, VL, zcr_len); } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 935e1929bb..d438fb89e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14608,7 +14608,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); - dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16; + dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 836511d719..67761bf2cc 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -111,7 +111,7 @@ static inline int pred_full_reg_offset(DisasContext *s, int regno) /* Return the byte size of the whole predicate register, VL / 64. */ static inline int pred_full_reg_size(DisasContext *s) { - return s->sve_len >> 3; + return s->vl >> 3; } /* Round up the size of a register to a size allowed by From patchwork Thu Jun 2 21:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=DPb7Aazh; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfpR5Pzwz9sFr for ; Fri, 3 Jun 2022 07:50:54 +1000 (AEST) Received: from localhost ([::1]:44102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsiS-0004UC-6o for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsge-0004QB-9L for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:00 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:34302) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgc-0008UE-1u for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:48:59 -0400 Received: by mail-pj1-x102d.google.com with SMTP id nn3-20020a17090b38c300b001e0e091cf03so6655797pjb.1 for ; Thu, 02 Jun 2022 14:48:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BnYlj1QWtoxKlbicrTFs8TmSm+Qpy+0FoE3R3RxAx04=; b=DPb7AazhBnPiJ/I9UdyRKp+2L6bEJMFCf0lvlhKV4q5ZlmgIY7+c5HI/Ta+Y4EyAmr dTfC5SZyr0mnV3NlyQrcU4eWsAmvSYGEAttlEUF5WMrOgQHR2IPcZroWpdTgQjUYeeld t5uYb41KApfLfA/xcSSBAo19fCrg0MBVO2bWAdk8hXBWGvwciJyPiyGJHEjs/Ag22yme 8aULnzdGjNAXC9j0AfanGOQtD2JzbTAS7SAxPrEOaqNbhuu1vGEB2W29afWRvSLKocs9 h5BBz5JXk48RSpRVHHra2l2U8rzzTPCH2Oobxhw5cll/sUhCeKiZPRpZaFXykaPAYgn2 584g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BnYlj1QWtoxKlbicrTFs8TmSm+Qpy+0FoE3R3RxAx04=; b=xbNP0xVNcpzISm8WBSIPoXBUJZviEwNfVXkf0qD+1gg6ySONeYsOWIGDWzTnLSwwXN S1YPKOGEZQaZoOoIeEBiSf0tnLVq2DKYaZumdJf6mi4GRSJJnYA/Z3jzVCiIzFfiC2J8 5wfnulZArtv4E2EGr0fjxRvsJEHtB+Fkc1MHMsD7k8W/Z7eowskusQrLeveUbt964h1X xqhyArKDYQxV19nurlGC0grWi6xIKZPG18kl+xIu7HzFhVG+OiPuGnd3HjWQOj4ghVCy VN47nx5cqcTw8EKfzkcYSUt5c2DQdhJNZeDX0dOVLNQgy+hjr8XRcIZ0+dwY2ecQu3Gp JUkQ== X-Gm-Message-State: AOAM531L+tzpudDJDyRkiRI4b4Ulvv24xotq9J/3qyDOduqJ/Z1AtqCH 8IoH8LWZwZZyRKVZVtfVMmQ0a5BcYf3KTg== X-Google-Smtp-Source: ABdhPJzWwyyutlrfr1IHjnSEQZyTu2KKgRTvXmJKrN7OnWHJSpCoRB4Wgz/WbVndqr5tHKAeeZjMeg== X-Received: by 2002:a17:90a:7e02:b0:1e0:a6a7:6eb with SMTP id i2-20020a17090a7e0200b001e0a6a706ebmr7445024pjl.203.1654206536631; Thu, 02 Jun 2022 14:48:56 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 02/71] linux-user/aarch64: Introduce sve_vq_cached Date: Thu, 2 Jun 2022 14:47:44 -0700 Message-Id: <20220602214853.496211-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add an interface function to extract the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Add sve_vq_cached rather than directly access hflags. --- linux-user/aarch64/target_prctl.h | 20 +++++++++++++------- target/arm/cpu.h | 11 +++++++++++ linux-user/aarch64/signal.c | 4 ++-- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 3f5a5d3933..fdd973e07d 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,7 +10,7 @@ static abi_long do_prctl_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { - return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + return sve_vq_cached(env) * 16; } return -TARGET_EINVAL; } @@ -25,18 +25,24 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { - ARMCPU *cpu = env_archcpu(env); uint32_t vq, old_vq; - old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; - vq = MAX(arg2 / 16, 1); - vq = MIN(vq, cpu->sve_max_vq); + old_vq = sve_vq_cached(env); + /* + * Bound the value of arg2, so that we know that it fits into + * the 4-bit field in ZCR_EL1. Rely on the hflags rebuild to + * sort out the length supported by the cpu. + */ + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, ARM_MAX_VQ); + env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); + + vq = sve_vq_cached(env); if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); } - env->vfp.zcr_el[1] = vq - 1; - arm_rebuild_hflags(env); return vq * 16; } return -TARGET_EINVAL; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 015ce12fe2..830d358d46 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3286,6 +3286,17 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) return EX_TBFLAG_ANY(env->hflags, MMUIDX); } +/** + * sve_vq_cached + * @env: the cpu context + * + * Return the VL cached within env->hflags, in units of quadwords. + */ +static inline int sve_vq_cached(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, VL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 7de4c96eb9..30e89f67c8 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -315,7 +315,7 @@ static int target_restore_sigframe(CPUARMState *env, case TARGET_SVE_MAGIC: if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = sve_vq_cached(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); if (!sve && size == sve_size) { sve = (struct target_sve_context *)ctx; @@ -434,7 +434,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = (env->vfp.zcr_el[1] & 0xf) + 1; + vq = sve_vq_cached(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs = alloc_sigframe_space(sve_size, &layout); } From patchwork Thu Jun 2 21:47:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=DDh1dNJY; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfph0qxBz9s5V for ; Fri, 3 Jun 2022 07:51:08 +1000 (AEST) Received: from localhost ([::1]:45546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsig-0005Zf-67 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:51:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgf-0004SB-Fh for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:01 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:39783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgc-0008UL-Tl for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:01 -0400 Received: by mail-pl1-x634.google.com with SMTP id o17so5533764pla.6 for ; Thu, 02 Jun 2022 14:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=80S55FypfkD2P2t6Vkw3PZn9gYfntg1XNKdtyYp1U90=; b=DDh1dNJYUj7ab/yKsg7Jp6GsTSGOUo+qthEPoOPyYgwBxq44wGW3N7dSva5qSlc+MP FwSsB2KSQHyRNJM8mH8BwVNhJj0sCX7CyAkDm9AV/pe78xRDjcppzOpQUUM1r8XTW8Za sk3WuDBruuPIL3i5RngtGXNodvDnFblReRUEOtVkwwcpxuKPCZ90beaAu5M5PE79TAOE fuRVQRNon99gv60lmOWJYD7ZAKJf40dbq3crcOO2jPADjIAaYGfo9DLbyViNZTv1TZKo uCI6nCpQvdk7BHvxxkh9iqT9zrwNw7/a5ukbMQE8SjtJX2guFAv7ymUDvLEWlN/PMGNC /uqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=80S55FypfkD2P2t6Vkw3PZn9gYfntg1XNKdtyYp1U90=; b=101C/dLvByXDABKsO+e2AJKxOzRg0DnKwEa1/MPIg2Y9hn5bgdDVSL0KfujogDHrPJ SRPezELB2A9/30rEq749q2BItpt2ei1s2wqaQrPZbQ1gNrfpx4v1/xZB2vgZaKIX0nbv PZyFMyZGNCJpT12OnIijYbgYMTE37RGGmMuF+hWno0UPn0L3T3AMvq/KECzsl3NnfajB vfQGMELjOaJV82XuSTNVXbBI/gThlMaYvEfeqJvOXIFx0J/0MiOKDjrqtTcIBzZxs5AA pOHlbDQnXACCw5PGO2uF7H33k2glNwdT1ysoNbUu/Tue7V8IyMLDlKFInIDWPhOS17pe Xdqw== X-Gm-Message-State: AOAM532PQ4++/yRjJo+Q2poBC2YqFgl609QVryT6MA8FlsIQrU+jDNSJ HzyesvTkKB/+1usX+xkjXmG5i5UTzIH+lg== X-Google-Smtp-Source: ABdhPJwuIgwoYcZe5mfUy9R4CqL9VDxpZrewkYhXQaiMPTgpWdpKJra0wFrS8m22M0/80JKKLApe1A== X-Received: by 2002:a17:90b:2404:b0:1e3:4db0:f32a with SMTP id nr4-20020a17090b240400b001e34db0f32amr14706764pjb.201.1654206537513; Thu, 02 Jun 2022 14:48:57 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/71] target/arm: Remove route_to_el2 check from sve_exception_el Date: Thu, 2 Jun 2022 14:47:45 -0700 Message-Id: <20220602214853.496211-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We handle this routing in raise_exception. Promoting the value early means that we can't directly compare FPEXC_EL and SVEEXC_EL. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 960899022d..8ace3ad533 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6159,8 +6159,7 @@ int sve_exception_el(CPUARMState *env, int el) /* fall through */ case 0: case 2: - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; + return 1; } /* Check CPACR.FPEN. */ From patchwork Thu Jun 2 21:47:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638463 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jgFqSxNr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg2b0HDKz9s0w for ; Fri, 3 Jun 2022 08:01:27 +1000 (AEST) Received: from localhost ([::1]:36732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwssf-00023g-3S for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:01:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgf-0004Sj-Ka for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:01 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:35412) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgd-0008Ug-Jt for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:01 -0400 Received: by mail-pj1-x102d.google.com with SMTP id o6-20020a17090a0a0600b001e2c6566046so10649319pjo.0 for ; Thu, 02 Jun 2022 14:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0e4LsisXhmXFsvM3FU/zvbh2EDjCmsWCEXLT7Sf9YRE=; b=jgFqSxNrIJzy5m5awI4C8iInfwp9rcDciK50cKOXhJZOdZCHMI4QmwZtwyHSKz7wof GdZWLXsAJ/7dNGpRK0IQmg0dhYcTR7OmfDn9oD9G422eA21P2vJgVoAqvf4dzsj67ErI iZKsy7ld5UDoJd1o/HhPLpxLJAfiM6xdU4811Kcz34rQB91fq+uK+xlNJc0d6LE+9+xB dz9OWWLYVTt6oGJgA03JdufCx6X3OvpJTPj9cM0UoCQaXPbOkhJQxHUKzEj6+IV1umIx UmsfGf8fwc1vPG19Ijgh68U/2mNdQIDjRIksfctFkEKLbadnn4KCrCdscFSaSOkUHnwL 2hJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0e4LsisXhmXFsvM3FU/zvbh2EDjCmsWCEXLT7Sf9YRE=; b=U5VRqnb3ooRbgbP4a6eRbQ/kEkMF/7NkeKfG6FD+4joNaej51xoe7BX4SvplTM8bol quJOUu/0/1pCgxVQ7JmkWWVDLMj+Itrk2I0uKUr+JiLPiYPMtusMbZfS0P7A4ZS8SX9C RJ0YJTlbUf4RGZG6paaGQlkg00pTza7pf6suE2a9iKQ6INNZ1LYrnZ519ujQ9NEYq/Eo MxoYcUdhkUmREjRyf/ilHYArgB6F0J4yEhwcFSMYWNreKtGt22230dSKA2ivL+eAja9y OE0ZBPILsmzcvdpA7lkY3sEHngfQuBkSlB66HWZ1rGSVAuITgLhXckt4IHxGB3s9rbiJ wqTw== X-Gm-Message-State: AOAM5301khG9TjoefBv/GcW6SSt1CR4l5a2t9MTwZO+Yzzgosy/j1BW9 jiTAtYx4hLI6zleq2PbIAsQM9IvcXRRihw== X-Google-Smtp-Source: ABdhPJylIuFtKLIGEaBm0nU5frLD2tqhRgPSmp4Gqs2+OedJbsROlIyWA9eeWwLYA4xEguhDpft1IQ== X-Received: by 2002:a17:90a:4fe1:b0:1de:fc11:331e with SMTP id q88-20020a17090a4fe100b001defc11331emr7525093pjh.145.1654206538229; Thu, 02 Jun 2022 14:48:58 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/71] target/arm: Remove fp checks from sve_exception_el Date: Thu, 2 Jun 2022 14:47:46 -0700 Message-Id: <20220602214853.496211-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 39 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ace3ad533..bcf48f1b11 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6139,11 +6139,15 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, }; -/* Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. This excludes the check for whether the exception + * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily + * be found by testing 0 < fp_exception_el < sve_exception_el. + * + * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the + * pseudocode does *not* separate out the FP trap checks, but has them + * all in one function. */ int sve_exception_el(CPUARMState *env, int el) { @@ -6161,18 +6165,6 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 1; } - - /* Check CPACR.FPEN. */ - switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { - case 1: - if (el != 0) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } /* @@ -6190,24 +6182,10 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - - switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { - case 1: - if (el == 2 || !(hcr_el2 & HCR_TGE)) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } else if (arm_is_el2_enabled(env)) { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { - return 0; - } } } @@ -13683,19 +13661,21 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el = sve_exception_el(env, el); - uint32_t zcr_len; /* - * If SVE is disabled, but FP is enabled, - * then the effective len is 0. + * If either FP or SVE are disabled, translator does not need len. + * If SVE EL > FP EL, FP exception has precedence, and translator + * does not need SVE EL. Save potential re-translations by forcing + * the unneeded data to zero. */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, el); + if (fp_el != 0) { + if (sve_el > fp_el) { + sve_el = 0; + } + } else if (sve_el == 0) { + DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); - DP_TBFLAG_A64(flags, VL, zcr_len); } sctlr = regime_sctlr(env, stage1); From patchwork Thu Jun 2 21:47:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638464 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=U4SDgABt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg306Df1z9s0w for ; Fri, 3 Jun 2022 08:01:48 +1000 (AEST) Received: from localhost ([::1]:37690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwst0-0002vF-UF for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:01:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgm-0004bz-05 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:08 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:38803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsge-0008Uu-CQ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:07 -0400 Received: by mail-pj1-x1034.google.com with SMTP id v11-20020a17090a4ecb00b001e2c5b837ccso10610722pjl.3 for ; Thu, 02 Jun 2022 14:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bgSSWj3FWGjqqOHg3NGXEoGoqiXuSmAzBvkeO1FtIzY=; b=U4SDgABtc7qf5g49OVWbGQJvO3x2QaH5yFiFAOEre0YLKzh7rpPy5ZXMabsrBz2dlv sFRfNlKnLRbH+LJIIfg27obrmm2Zn1eiWBThBo07GsdMkkBVw7OupjcV4h1KCYxvuvKp hBMiYfvru7XdZg4IeWIZ2K9hUKsTo2JU8N9Pdzg7EAAMheqbdvQh3jDTKq2GrWmSqUFf +UXP/F6Wn30jKevcgQTuh/jF2jNJsml868X+ZtQ4bVGvVowWTyVxlu7eM7eKv85/U0Um c+cjtHr0rmklsIpsaCSr9lEymhwUCyB6oXTvkgXoL/v/JSrNcC1R4yn9THAP0dFwnPaV UwYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bgSSWj3FWGjqqOHg3NGXEoGoqiXuSmAzBvkeO1FtIzY=; b=1zlcXjKDjZyd9RgGPlkp53FQlhUKfELGBF3oqMoiols5gjOH800gW1LgY0JqU/e8hv IoBQvUBJ3h/MNtwoS5qSAsSXG/cJeEhFK5XftS0YWSLfITY6vQTnfKGwox0X3K3hJf/n 8VkSBixxA9MEdTj+6xDc8rix5X7+ZcFCA7afwlLyjZnzXnEo5o5IM3Sd+krc9jwv19um UIdZISYCt6kBj7j+Q3iO/bPEgVv5jjE5A0ACwtMPWQdEk+Y+7iP4+bIwzQvu5j5XxHqK m0esPJ43TyGlWrvMrMcfERrz3g0JBLKtvy7WVAZWFQOyuAebVNHDUPqNoUNcYDpncODl Usfg== X-Gm-Message-State: AOAM530/yuyIdhwyHW37fMSSGhZViWxQuXaDjDby59CbK/5Gg9xmqOsC tOzuc5OqmuJDf4samgb1y9pC4POl43rG5A== X-Google-Smtp-Source: ABdhPJy3HSjPFjSmoHdsCoxs8SZpG+RBuE6WJLGRvO5sPqAq6euvQZWNdo/Kvhvgnmn4MD22jczEiQ== X-Received: by 2002:a17:90b:1a8a:b0:1e0:3630:19f0 with SMTP id ng10-20020a17090b1a8a00b001e0363019f0mr42099725pjb.89.1654206539020; Thu, 02 Jun 2022 14:48:59 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 05/71] target/arm: Add el_is_in_host Date: Thu, 2 Jun 2022 14:47:47 -0700 Message-Id: <20220602214853.496211-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee468..a73f2a94c5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1328,6 +1328,8 @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif +bool el_is_in_host(CPUARMState *env, int el); + void aa32_max_features(ARMCPU *cpu); #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index bcf48f1b11..839d6401b0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5292,6 +5292,34 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } +/* + * Corresponds to ARM pseudocode function ELIsInHost(). + */ +bool el_is_in_host(CPUARMState *env, int el) +{ + uint64_t mask; + + /* + * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). + * Perform the simplest bit tests first, and validate EL2 afterward. + */ + if (el & 1) { + return false; /* EL1 or EL3 */ + } + + /* + * Note that hcr_write() checks isar_feature_aa64_vh(), + * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. + */ + mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; + if ((env->cp15.hcr_el2 & mask) != mask) { + return false; + } + + /* TGE and/or E2H set: double check those bits are currently legal. */ + return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); +} + static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { From patchwork Thu Jun 2 21:47:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=oaEB+Kht; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgLk0qhMz9s0w for ; Fri, 3 Jun 2022 08:15:26 +1000 (AEST) Received: from localhost ([::1]:46258 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt6B-0002g6-TK for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:15:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgs-0004li-MB for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:15 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:40476) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgf-0008VH-0f for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:14 -0400 Received: by mail-pf1-x430.google.com with SMTP id z17so5795452pff.7 for ; Thu, 02 Jun 2022 14:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gadtRptqMEMWzO7/udpBazlKdbGTM/FsnG+P+qdCdG4=; b=oaEB+KhtZc1zLhG/G4M45S21gRBhcnC6h1BoqWq7DFhO+a3mUG88XRWbsFwjjRcnNy opfJJzBqlqkirgFODo2TQyyo0Hnkbp97pvJqTOXQwEApv5zBX06Zm3QGL9a33k0jAAcv 7CwA57mmRw4JULmmmGsakVtZZjPDb9BxoYnR+9zy+syXEQgGznO+TnMIsi+teazVU76v DfvVF5Das5j5GmJdQLepyTQyrVx2UQHACaaXyveMyqK7liouukb/wslF89tMjGpStWl5 im9D+Tfqb8ubztacgBAVQh6qZ9sbt9Fems6Tdga32lw/awWABGl4CmuBND1eNmeE6Eem ivLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gadtRptqMEMWzO7/udpBazlKdbGTM/FsnG+P+qdCdG4=; b=iW3dPvuuTMdgsFkmyhHiA5kQX19PzFNvtN2tQFXndaoyeRaXjGDtB3r9XNQ7UXZbil mTH21mBrQhVfQZWJF2UAD8px0cagiCDMFohavL7uzjVzp6zpw9lfcd3ipac1FWds3DZU r1bplzymZWhRbUa9hnfI92YsIh8uHExU0X80025evYMKPyX+ZNnAfqVrFe2Jlv4Qp9sp 3qq9zjbcjDgbXgo642bjATbCklDH0QaU/XPKsYc5PJhFSaHSYCT9Ioeed2F5MY800bsx X3mCEMi/d+9oJkF6YBQXEqnNgGzW77z8plc1ljX0m0W+HguGu00e2rB4hnMOBsd94AQF +FoA== X-Gm-Message-State: AOAM530s8RihJ8ebCoK1+liFrfVvz3wA4+xPgFnltxljgqaLKP1yDKhx KVtHDrNfwYzL2r+m1Kz1nh0Covh6++yC9w== X-Google-Smtp-Source: ABdhPJy+beCHN/eyvTtmfn+f7JH6WNwr5R93uJ6MIKgm3sTvr7IkTaLvsO2cw7ckAOI2i0QJYDd5dg== X-Received: by 2002:a63:2c15:0:b0:3f6:6a5f:8f0a with SMTP id s21-20020a632c15000000b003f66a5f8f0amr5891187pgs.76.1654206539702; Thu, 02 Jun 2022 14:48:59 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:48:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 06/71] target/arm: Use el_is_in_host for sve_zcr_len_for_el Date: Thu, 2 Jun 2022 14:47:48 -0700 Message-Id: <20220602214853.496211-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 839d6401b0..135c3e790c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6248,8 +6248,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) ARMCPU *cpu = env_archcpu(env); uint32_t zcr_len = cpu->sve_max_vq - 1; - if (el <= 1 && - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + if (el <= 1 && !el_is_in_host(env, el)) { zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { From patchwork Thu Jun 2 21:47:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638458 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Jc0ALYc5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfqz3F2jz9s5V for ; Fri, 3 Jun 2022 07:52:15 +1000 (AEST) Received: from localhost ([::1]:48036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsjl-0007Ly-Gk for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:52:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgi-0004VB-E3 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:04 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:34777) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgf-0008Ve-UW for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:03 -0400 Received: by mail-pf1-x435.google.com with SMTP id c196so5815378pfb.1 for ; Thu, 02 Jun 2022 14:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Ev7rY3/e5SYquDaVsOHvuROOoufvb4/pczCNQeIm0s=; b=Jc0ALYc59bQuLEB4BfzZhnPtgcOVwL+Ykm8IF3ZLApPx7eSQE10WZuS2Gp0K/E52xL A0tRxCRjo7LjlZPymmB4p8PpC9OJtN2N4O3FbbgP4PfpVB0drjjJ8MBbFz+PwFyY/EfB Er+ff44LpOgYOEeOjyoRsQZ0IwM4E1AkudqXtHWnzBUsrpA4DggyEBNMLlHB14uTGp4v ZcNkBh+fIEsdS4ulblMZgMaEM+i5+JXaAOnPmXdZ3WuDkzJvZQrwMIX+NuVQO1LPL/qI 6+JF1w0MSd+1r+0mhsu8/N45nm0Li5ejqcRdOjmObMLFl/Z3pgfsmwfmMUrbYPeIYP9Z yJeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Ev7rY3/e5SYquDaVsOHvuROOoufvb4/pczCNQeIm0s=; b=Dr5TP/nf/K1venNG8P38X4ZlNwlMxJNnC4+gAsC1Ov9wtneOnPY1rlCr0Yu8Xte7RL tclOrnIQB2QCyqoPCxKg9nqvftfRTMTFwSmVyj29UEnvFFSL3Ygv+j1BFnFuw3iKhR25 ztIbu5LTsGIMootBMJMbwKHUd0+hlMbWwVo/MM7JIA9Jq39ELn6UfIP/qzjoAqa0YIKC rRpdCnIOKvUGOJPr5dYgw9FJ/g7RKmILEB3KiCdKOsaA2kMuOybi+btHjIt7fBQ/2lq7 qOP/hSjSqs2r8wiP1MtECjA3POvJ1ybo5RwBniAmPm7YJwFuYSzqIckmIMHGm3C1VxBu nUjw== X-Gm-Message-State: AOAM533FMkeZQUIFVjLz8EBytFOjrCv01z94mcmVOmCR2FMbbzFBGTMd 3/eZysAXXMcR90NKFM//85d1gD3lXz/OzQ== X-Google-Smtp-Source: ABdhPJwXivQGBK5K21g1Zud8AgX7CIFRgtGKvyO506ylsyoWSC7WphV1cE9P2k2dA2AXaSV83wzRsg== X-Received: by 2002:a05:6a00:2488:b0:518:afb4:bb60 with SMTP id c8-20020a056a00248800b00518afb4bb60mr7073816pfv.51.1654206540593; Thu, 02 Jun 2022 14:49:00 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 07/71] target/arm: Use el_is_in_host for sve_exception_el Date: Thu, 2 Jun 2022 14:47:49 -0700 Message-Id: <20220602214853.496211-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The ARM pseudocode function CheckNormalSVEEnabled uses this predicate now, and I think it's a bit clearer. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 135c3e790c..7319c91fc2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6180,9 +6180,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 = arm_hcr_el2_eff(env); - - if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { + if (el <= 1 && !el_is_in_host(env, el)) { switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el != 0) { @@ -6199,6 +6197,7 @@ int sve_exception_el(CPUARMState *env, int el) * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ if (el <= 2) { + uint64_t hcr_el2 = arm_hcr_el2_eff(env); if (hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: From patchwork Thu Jun 2 21:47:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638460 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=RTyDCht9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfy11bLcz9s0w for ; Fri, 3 Jun 2022 07:57:29 +1000 (AEST) Received: from localhost ([::1]:57192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsoo-00056F-Sp for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:57:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgk-0004Yz-5N for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:06 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:33574) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgg-0008Vz-Nn for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:05 -0400 Received: by mail-pg1-x52e.google.com with SMTP id r71so5834186pgr.0 for ; Thu, 02 Jun 2022 14:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=76vB8wrE1Opihq5ZL4xDfiTWT29p2624W3Se2XeubnM=; b=RTyDCht9+yNtoXqwwpW6Lk2yOdUEKbX73tD5t69qtR5/egnInjoqAsn0e68hs7V8Uv qdf+S1ThrSmNZeudZjhkrlaEx75q8SsCdiCpE70tFHELyRR+yaV78EcK8CYv3dgBrxT5 jLWRMg/Ii+r8FpGpqli0zyhOoY9o0H5stawH7Q78C/7KQ6sKXKNV9ER28gLMItvzrG7U KO5h6RraxOXTFGo7zsHO2MwTLTkEuycaDSqPN+3X7pl5kvzC+6gmBiaAmXpO/ryVaYYa 51+IXXrFeRPmpIppG+eVfv2fJgB4UHp8w1GlzMKuWDdH0zNcMG7agQnpuV6Ff6uDTpl4 S+eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=76vB8wrE1Opihq5ZL4xDfiTWT29p2624W3Se2XeubnM=; b=MLxtuO7nJ7NMGl4fIEoeEQPouvcjMe/fBfeiVGPjSY0gxjoIXtXJg7jJj0jZySEdbe Wi/IeUF6E9cQMG5hwf3YD+6ksuP+UNzUH8CYKS6RX8R2fvtMpJvFnw35ojFRKgGAaEvE epe/ZJfv38KR/vYRTVf6TIX3DXh1Vch3vAnJfE+UxNN68lc1Pf1EJGpebbDyA5WvKd1e WEegRY8EGyTQc5NZfW2OFJk782loG7h0HSC6f8+ShXdL2LI3tYWNUyWBvXC3yYozZXsP 1GfuIjjouwFKkWT4qlsThLZXzwF0NBD/VUlrAciJJFeMBh1l5efeE5eoU/0xTKSntXXH 7ypw== X-Gm-Message-State: AOAM53365/uVznuIfoP/1zSM7oeTpujT6u7L+HHlcWqOhzYVjM/5SeX7 +mG7WVU6NNoFxNBIqmaRofTN3c4a4wSATg== X-Google-Smtp-Source: ABdhPJyZFkuALg/fx8XNhr7ZtLYycQ//eGXkNxyrQy+ltaKzaUnbBOkzVOWAtbMXc+9DKBUS7hdKBQ== X-Received: by 2002:a05:6a02:105:b0:381:fd01:330f with SMTP id bg5-20020a056a02010500b00381fd01330fmr5875797pgb.483.1654206541335; Thu, 02 Jun 2022 14:49:01 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/71] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el Date: Thu, 2 Jun 2022 14:47:50 -0700 Message-Id: <20220602214853.496211-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This check is buried within arm_hcr_el2_eff(), but since we have to have the explicit check for CPTR_EL2.TZ, we might as well just check it once at the beginning of the block. Once this is done, we can test HCR_EL2.{E2H,TGE} directly, rather than going through arm_hcr_el2_eff(). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7319c91fc2..dc8f1e44cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6193,15 +6193,12 @@ int sve_exception_el(CPUARMState *env, int el) } } - /* - * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). - */ - if (el <= 2) { - uint64_t hcr_el2 = arm_hcr_el2_eff(env); - if (hcr_el2 & HCR_E2H) { + if (el <= 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: - if (el != 0 || !(hcr_el2 & HCR_TGE)) { + if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { break; } /* fall through */ @@ -6209,7 +6206,7 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - } else if (arm_is_el2_enabled(env)) { + } else { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } From patchwork Thu Jun 2 21:47:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638467 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bywEvkmn; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg550yfHz9s0w for ; Fri, 3 Jun 2022 08:03:36 +1000 (AEST) Received: from localhost ([::1]:45204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsuk-0007x4-U8 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:03:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgk-0004aL-QJ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:06 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:42892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgi-0008WS-H2 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:06 -0400 Received: by mail-pf1-x435.google.com with SMTP id 187so5791686pfu.9 for ; Thu, 02 Jun 2022 14:49:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CQLR9+ZabdVBvj8yT9hoESiXzPxfvDoRGYhKlSAaF0=; b=bywEvkmnIb7r7ZyRdZI97F7nc/D52jZRCdOtDo6VwfxJrbCe1kBxIg8dYCSiI5CXcr RfdnG0flMby4SkyKS/d8FYOalskgszDFWbv+OeQHNE8vXYRB/q6Q3UNoCgUY9EqmwBIG lLU0rZaFk58qNMNQMZJfvDb+bXwnhg6ijKs6FidUiL/MDb0RQn5q432DjvKz+7eINLzy IUVaExTTYxUdgVDhZ4E/jvap0NuWA1RmIiYVZElJadWbr1FAGg1mXDpsKXoCm5S7eXUs doTipSrO2Hp/NIehwvlOGatB27eeC34fJEO6fC+aKlfHLlqRJow7bSrlpBUtQhEzvbly cHmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9CQLR9+ZabdVBvj8yT9hoESiXzPxfvDoRGYhKlSAaF0=; b=8Q6jvEmqyLJubv0Ws8AxViM/wiD0A4uq2xBjzbvXS+fVFXqFu4LgCzwHze2hQgfKm+ GaGMnjAF1ubzUDRyyGzCUYURd2DtrGqZY615w7yeP4IMN4+RDvw7fQIh/iL2bkcBDXQc tFr1piyTq5xPhV5BaSfYuBHP899f1jZduSDiIL31eBlb25L3wVwZBHjPwl6NUBQKpx8k RLSk5ia9ceJKSQRao3Sf9AUnWsoB9rDp1QNB2mGTNWYaocQimiSUvkTBz70qIs+bboZL yrU6pkPVdIIDLspmDnaWGXYyeYg9xqGs+f/+LAjMNFCIEzXi+Gv8GY+g0IyP27ygiAMq 9ysA== X-Gm-Message-State: AOAM532OUdeIfSnlg1jf/13re8iY4kiRarI5vfNWFTX8qSpC6tyjbtPU 3oDdyxkj0XlpV0prCwfoKtx4uugHZ9BINQ== X-Google-Smtp-Source: ABdhPJyPjEsVHkV7FwTFNCOtO9cD+g+uQXtAdnV8rIrzOJfxaGrhSLG4LkqCowoz0tyYr8UrMblQhA== X-Received: by 2002:a63:44b:0:b0:3fc:cd1c:49e8 with SMTP id 72-20020a63044b000000b003fccd1c49e8mr6061503pge.172.1654206542235; Thu, 02 Jun 2022 14:49:02 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 09/71] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Date: Thu, 2 Jun 2022 14:47:51 -0700 Message-Id: <20220602214853.496211-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2bd74c2ed..0621944167 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,8 +208,7 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] = - aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); + env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } /* * Enable 48-bit address space (TODO: take reserved_va into account). From patchwork Thu Jun 2 21:47:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638472 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=yrBi8/HO; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgCD24DMz9sFr for ; Fri, 3 Jun 2022 08:08:56 +1000 (AEST) Received: from localhost ([::1]:54858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwszu-0006Kh-CC for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:08:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgn-0004ec-6g for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:09 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:36649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgj-00005A-MQ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:08 -0400 Received: by mail-pf1-x42f.google.com with SMTP id 15so5806471pfy.3 for ; Thu, 02 Jun 2022 14:49:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wdmw1yZnvA+hHeQ/W/SOHIyofz1vGsnPTS9QtN7as88=; b=yrBi8/HOIzwuYuwb3tsIBKPlLlv4ge6+TAx7ctt8P+ZhZyKbL87/APHr8HDXPfRftX O9ogNZKIXwn52SyHNdaoui/53O1zN3zB0V2ZRK+hxU7NtZzrNgvuSgtXiclMviy4JR8n k+VSn+EHwsrrbtePViwGaia+noLkrQKj9pXHfqlSvwaNObjhN9F5zPL9SzZCBgav9Xdi PhUCc7wDlsQ7BXEP8NSF9Rl+tvRYM0CxjrP/4vx278HnFf3Z4GRuj+lloneqSHBoZWDW Kh8uH+5HHn5WCDNfxTf6SZJenJTr1JI/pMboTWvnDR7IKo63CpdtOkTdlO9bOilm9Ct/ rRrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wdmw1yZnvA+hHeQ/W/SOHIyofz1vGsnPTS9QtN7as88=; b=z0U8qdfi0Gilnu04cRVxE4c/AA2XIUsIcOjnMRs46ju7adNzG4Ec79WMI2N8UmNhiw fZaLAj8DAP1mmqYwgIbH7ofyn6EquTEtG61sLzlrNG4pdB2up6c3xnS8jxBHBrHouUwm i7eB1anFP5Uo2f46aANqWA0dckkMxCvewUpljigK/+A16f76xl3iCNB7/xJc51bXkrHe ntV1NKNXDsB2quuNurzaURA813DJFZ7o+ggZT22edCE1w3dPmz7GIupZ1SXFE28d235Z h8JIpn8K3fVcuXAaavDupXdPnitAbKqYlsDqTapCanYXjqeTKxoIZV3Qj5aarwPowsK8 cTug== X-Gm-Message-State: AOAM5328XiTpproXhZNto/B2w6E95jHcAcmpEDT/UfhWQS364zuI9cfH zg70Aie4wiogljZFj+nSP4D6C2gs8o27Gw== X-Google-Smtp-Source: ABdhPJyuPQwHUF3H0CtB8Zs4+nfFa9bZcrPG4Kz/nlLbbO6s3OjtbBWmn3QRjWTLaadmHkMMNlE9pw== X-Received: by 2002:a63:91ca:0:b0:3fc:9077:c7c7 with SMTP id l193-20020a6391ca000000b003fc9077c7c7mr6000905pge.201.1654206543279; Thu, 02 Jun 2022 14:49:03 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/71] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Date: Thu, 2 Jun 2022 14:47:52 -0700 Message-Id: <20220602214853.496211-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This function is used only once, and will need modification for Streaming SVE mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 11 ----------- target/arm/helper.c | 30 +++++++++++------------------- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a73f2a94c5..4dcdca918b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -189,17 +189,6 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ -/** - * aarch64_sve_zcr_get_valid_len: - * @cpu: cpu context - * @start_len: maximum len to consider - * - * Return the maximum supported sve vector length <= @start_len. - * Note that both @start_len and the return value are in units - * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. - */ -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/helper.c b/target/arm/helper.c index dc8f1e44cc..e84d30e5fc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6222,39 +6222,31 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - start_len = MIN(start_len, ARM_MAX_VQ - 1); - end_len = start_len; - - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len = find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - /* * Given that SVE is enabled, return the vector length for EL. */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); - uint32_t zcr_len = cpu->sve_max_vq - 1; + uint32_t len = cpu->sve_max_vq - 1; + uint32_t end_len; if (el <= 1 && !el_is_in_host(env, el)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); + end_len = len; + if (!test_bit(len, cpu->sve_vq_map)) { + end_len = find_last_bit(cpu->sve_vq_map, len); + assert(end_len < len); + } + return end_len; } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Thu Jun 2 21:47:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=qqVglmdP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfy83dvrz9s0w for ; Fri, 3 Jun 2022 07:57:36 +1000 (AEST) Received: from localhost ([::1]:57798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsow-0005Yy-Id for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:57:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgm-0004cO-5U for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:08 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:41921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgj-0008VG-3X for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:07 -0400 Received: by mail-pf1-x42e.google.com with SMTP id p8so5795319pfh.8 for ; Thu, 02 Jun 2022 14:49:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EVyZvmlYsEV05qY937aLYRbVAXbV11KqU2qhcOkYz0E=; b=qqVglmdP1BrMQMv9WOI/QvFeQlhcBvuPVJa2iGGds8ak1UZmiXn7DEOadBM9P8A7W5 BFFW126rhLLSo2J6Lnyq+7OiP3TP3MIGylCMZzMypa4RhFyapgDvjIXt9JU001/XBYMl s6fWAcvqlsY7om/7qOM3LjCiaihRu9XSYMMsX2LVN+709GEqSLWu/T6me6+gBOSRX0Na A/QimdLDJcDdsaAR/VvfpOer/yuKECU8WN5nbyErfTvfpAy3H64R4Kp59lK0pQo0jvyA 8UZUPOxxwk5VCiTK89XCFrfvC25z5M8UPZHLItV8AGeKqqZDv9GBK48AYqv+Bdrrz9SA O1ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EVyZvmlYsEV05qY937aLYRbVAXbV11KqU2qhcOkYz0E=; b=tou27VK9xsGFSPBaV/gLgFFdVs1iM+sjYGW0/zH0jNK+8IZwboLYqdIonKMI7xSn1u JRWmU2Fm9m+q4+P/ViGAtoM8R4droSKjIUUzrNCxMmZOnVfFwiGKNvsl2e085Rkazx3B RI8whyeep6jPtPbgyvS8u12ohKPzDuhG9QVSTVzLkuV3FFq2y+6VjXdl5RJlUN1yUTAR 10c0RJieDsRTYGeS7JY5rhnYkU/df0n82hdiUuW+cLV2HeaakKtE08ypNDO1mS3edLOh v5WDBsNGGKuMrhFv7ZWi68bzhgeduPE2ivb966VonHWHJbLSD8aK6fyb0VZc4Smdb/Ds Yy9A== X-Gm-Message-State: AOAM530BZkzJ2wXsC2bBH+n9JSNNTTttGOtu7htaYGadiALJWy285exW rEgJ4row71DlPqczzORk26uBlcE9jnS/xQ== X-Google-Smtp-Source: ABdhPJwj5qZP3hTiFOGmo0t60Dc3EZues/3zsOa2zSMp3ErKynszY2bYVeSHWh1+Gom7G2VbDFBISQ== X-Received: by 2002:a63:5706:0:b0:3fc:a31b:9083 with SMTP id l6-20020a635706000000b003fca31b9083mr5863292pgb.333.1654206544125; Thu, 02 Jun 2022 14:49:04 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 11/71] target/arm: Use uint32_t instead of bitmap for sve vq's Date: Thu, 2 Jun 2022 14:47:53 -0700 Message-Id: <20220602214853.496211-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing zeros as required to find the result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +-- target/arm/internals.h | 5 ++ target/arm/kvm_arm.h | 7 ++- target/arm/cpu64.c | 117 ++++++++++++++++++++--------------------- target/arm/helper.c | 9 +--- target/arm/kvm64.c | 36 +++---------- 6 files changed, 75 insertions(+), 105 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 830d358d46..ef51c3774e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1041,9 +1041,9 @@ struct ArchCPU { * Bits set in sve_vq_supported represent valid vector lengths for * the CPU type. */ - DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); + uint32_t sve_vq_map; + uint32_t sve_vq_init; + uint32_t sve_vq_supported; /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 4dcdca918b..8bac570475 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1321,4 +1321,9 @@ bool el_is_in_host(CPUARMState *env, int el); void aa32_max_features(ARMCPU *cpu); +/* Powers of 2 for sve_vq_map et al. */ +#define SVE_VQ_POW2_MAP \ + ((1 << (1 - 1)) | (1 << (2 - 1)) | \ + (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) + #endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b7f78b5215..99017b635c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -239,13 +239,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); /** * kvm_arm_sve_get_vls: * @cs: CPUState - * @map: bitmap to fill in * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one - * (vq - 1) in @map up to ARM_MAX_VQ. + * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); +uint32_t kvm_arm_sve_get_vls(CPUState *cs); /** * kvm_arm_set_cpu_features_from_host: @@ -439,7 +438,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) g_assert_not_reached(); } -static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ff9219ca3..51c5d8d4bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least one * vector length must be enabled. */ - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq = 0; + uint32_t vq_map = cpu->sve_vq_map; + uint32_t vq_init = cpu->sve_vq_init; + uint32_t vq_supported; + uint32_t vq_mask = 0; + uint32_t tmp, vq, max_vq = 0; /* * CPU models specify a set of supported vector lengths which are @@ -364,10 +367,16 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * in the supported bitmap results in an error. When KVM is enabled we * fetch the supported bitmap from the host. */ - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); + if (kvm_enabled()) { + if (kvm_arm_sve_supported()) { + cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported = cpu->sve_vq_supported; + } else { + assert(!cpu_isar_feature(aa64_sve, cpu)); + vq_supported = 0; + } + } else { + vq_supported = cpu->sve_vq_supported; } /* @@ -375,8 +384,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * From the properties, sve_vq_map implies sve_vq_init. * Check first for any sve enabled. */ - if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { - max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; + if (vq_map != 0) { + max_vq = 32 - clz32(vq_map); + vq_mask = MAKE_64BIT_MASK(0, max_vq); if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { error_setg(errp, "cannot enable sve%d", max_vq * 128); @@ -392,15 +402,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * For KVM we have to automatically enable all supported unitialized * lengths, even when the smaller lengths are not all powers-of-two. */ - bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |= vq_supported & ~vq_init & vq_mask; } else { /* Propagate enabled bits down through required powers-of-two. */ - for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } + vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask; } } else if (cpu->sve_max_vq == 0) { /* @@ -413,25 +418,18 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) if (kvm_enabled()) { /* Disabling a supported length disables all larger lengths. */ - for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, cpu->sve_vq_supported)) { - break; - } - } + tmp = vq_init & vq_supported; } else { /* Disabling a power-of-two disables all larger lengths. */ - for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } + tmp = vq_init & SVE_VQ_POW2_MAP; } + vq = ctz32(tmp) + 1; max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, - cpu->sve_vq_init, max_vq); - if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { + vq_mask = MAKE_64BIT_MASK(0, max_vq); + vq_map = vq_supported & ~vq_init & vq_mask; + + if (max_vq == 0 || vq_map == 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n", @@ -441,7 +439,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } - max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1; + max_vq = 32 - clz32(vq_map); + vq_mask = MAKE_64BIT_MASK(0, max_vq); } /* @@ -451,9 +450,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (cpu->sve_max_vq != 0) { max_vq = cpu->sve_max_vq; + vq_mask = MAKE_64BIT_MASK(0, max_vq); - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { + if (vq_init & ~vq_map & (1 << (max_vq - 1))) { error_setg(errp, "cannot disable sve%d", max_vq * 128); error_append_hint(errp, "The maximum vector length must be " "enabled, sve-max-vq=%d (%d bits)\n", @@ -462,8 +461,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |= ~vq_init & vq_mask; } /* @@ -472,13 +470,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * are clear, just in case anybody looks. */ assert(max_vq != 0); - bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); + assert(vq_mask != 0); + vq_map &= vq_mask; /* Ensure the set of lengths matches what is supported. */ - bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq = find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { + tmp = vq_map ^ (vq_supported & vq_mask); + if (tmp) { + vq = 32 - clz32(tmp); + if (vq_map & (1 << (vq - 1))) { if (cpu->sve_max_vq) { error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); error_append_hint(errp, "This CPU does not support " @@ -502,15 +501,15 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } else { /* Ensure all required powers-of-two are enabled. */ - for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smaller " - "than the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } + tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map; + if (tmp) { + vq = 32 - clz32(tmp); + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller " + "than the maximum, sve%d\n", + vq * 128, max_vq * 128); + return; } } } @@ -530,6 +529,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq = max_vq; + cpu->sve_vq_map = vq_map; } static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, @@ -590,7 +590,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value = false; } else { - value = test_bit(vq - 1, cpu->sve_vq_map); + value = extract32(cpu->sve_vq_map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -612,12 +612,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - if (value) { - set_bit(vq - 1, cpu->sve_vq_map); - } else { - clear_bit(vq - 1, cpu->sve_vq_map); - } - set_bit(vq - 1, cpu->sve_vq_init); + cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value); + cpu->sve_vq_init |= 1 << (vq - 1); } static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -978,7 +974,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); + cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1025,12 +1021,11 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_vprebits = 5; cpu->gic_pribits = 5; - /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); - set_bit(0, cpu->sve_vq_supported); /* 128bit */ - set_bit(1, cpu->sve_vq_supported); /* 256bit */ - set_bit(3, cpu->sve_vq_supported); /* 512bit */ + cpu->sve_vq_supported = (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ cpu->isar.reset_pmcr_el0 = 0x46014040; diff --git a/target/arm/helper.c b/target/arm/helper.c index e84d30e5fc..7b6f31e9c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6229,7 +6229,6 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); uint32_t len = cpu->sve_max_vq - 1; - uint32_t end_len; if (el <= 1 && !el_is_in_host(env, el)) { len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); @@ -6241,12 +6240,8 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - end_len = len; - if (!test_bit(len, cpu->sve_vq_map)) { - end_len = find_last_bit(cpu->sve_vq_map, len); - assert(end_len < len); - } - return end_len; + len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + return len; } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 363032da90..b3f635fc95 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -760,15 +760,13 @@ bool kvm_arm_steal_time_supported(void) QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +uint32_t kvm_arm_sve_get_vls(CPUState *cs) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; static bool probed; uint32_t vq = 0; - int i, j; - - bitmap_zero(map, ARM_MAX_VQ); + int i; /* * KVM ensures all host CPUs support the same set of vector lengths. @@ -809,46 +807,24 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) if (vq > ARM_MAX_VQ) { warn_report("KVM supports vector lengths larger than " "QEMU can enable"); + vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ); } } - for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) { - if (!vls[i]) { - continue; - } - for (j = 1; j <= 64; ++j) { - vq = j + i * 64; - if (vq > ARM_MAX_VQ) { - return; - } - if (vls[i] & (1UL << (j - 1))) { - set_bit(vq - 1, map); - } - } - } + return vls[0]; } static int kvm_arm_sve_set_vls(CPUState *cs) { - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0}; + ARMCPU *cpu = ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq_map }; struct kvm_one_reg reg = { .id = KVM_REG_ARM64_SVE_VLS, .addr = (uint64_t)&vls[0], }; - ARMCPU *cpu = ARM_CPU(cs); - uint32_t vq; - int i, j; assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX); - for (vq = 1; vq <= cpu->sve_max_vq; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_map)) { - i = (vq - 1) / 64; - j = (vq - 1) % 64; - vls[i] |= 1UL << j; - } - } - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); } From patchwork Thu Jun 2 21:47:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vpnDYxlY; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg3h6CTGz9s0w for ; Fri, 3 Jun 2022 08:02:23 +1000 (AEST) Received: from localhost ([::1]:39922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwstY-0004Rc-F0 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:02:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgo-0004en-NQ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:10 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:44705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgk-00005u-EV for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:09 -0400 Received: by mail-pf1-x433.google.com with SMTP id g205so5773136pfb.11 for ; Thu, 02 Jun 2022 14:49:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X907WscUJ/vcZY0rjH59HojFCAmIiYCNZ0u3IiREgKo=; b=vpnDYxlYuZYLgYNpIYFkkT24zO6YkyrtA8Gc1rtudDgRGZfMAiBLme/WfIVuCdy/MA Bexr6gWCUxz61KB4H71Ijv3dAKTFgmHeEn7nwY12nHBLMiUl3BwZITTUincJ0OIZwHaG MzD8Cf0VyIycjteSUUEuwgG8FgITh2Hjb93DuonlFzf4z2m3cLBIoBicgW1O5q6834yh qrH6eP2vZv+mvirXdE57/UJvN/Hazqsc4ALeAglWiZfGzApVWTq6RmY/Z4TJGJUQvh2h aVJ05WKTtNKNMNWDHZuYIDqXhHzgdmhHMRWChsz4cPej9V5WGBA8FxrsE03tvq0P7AVJ gHAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X907WscUJ/vcZY0rjH59HojFCAmIiYCNZ0u3IiREgKo=; b=CPdyzPDLuBW+QhLalEk888HV3mYKlUGM1lPCR9b83DJczxzwvH31BdHVLQjS1lkibe ZizYtbW4xRSQpL7LIkEqoJ+j7Qpb8rnRUkJWJ6jOwKQbI9u067vMacaA9usW4lBxUo35 FUD+NFBj8hlSYhspZr4qsXndFfL5CVB+QQIYIAa3ImC+8n0tcfOzVVxFtP+AxCdm7IYl AcX2xhzF7GKVRg9+HBNjT5k4el04A69XJ///P7maiy5EWcYw/8hTec9VG6vT+OudiJ/q XngsxJh86ddg6olh8cR9oU2UUuwX0s1pnAwga0fdNBZq5QQg5VFSwJOIBk39+S8A50BE cy8w== X-Gm-Message-State: AOAM532oT3f2QIg+7aBw9q5TYun7GXHOkIyDpB2pj2PjVlDsXXf9hKs+ sABFEBP/TsmWf81FUFUy6g5htBubUA8okQ== X-Google-Smtp-Source: ABdhPJwQ6DBMhl5awfoK4T3GPqjPSSTuCHoHuKle7vsDGM5VQLeJCdsmX994gvesHmCtZItRblwruQ== X-Received: by 2002:aa7:90d5:0:b0:4e1:307c:d94a with SMTP id k21-20020aa790d5000000b004e1307cd94amr7127556pfk.38.1654206545025; Thu, 02 Jun 2022 14:49:05 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 12/71] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el Date: Thu, 2 Jun 2022 14:47:54 -0700 Message-Id: <20220602214853.496211-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 11 ++++++++++- target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 12 ++++++------ 5 files changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ef51c3774e..cb37787c35 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1132,7 +1132,16 @@ void aarch64_sync_64_to_32(CPUARMState *env); int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); + +/** + * sve_vqm1_for_el: + * @env: CPUARMState + * @el: exception level + * + * Compute the current SVE vector length for @el, in units of + * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + */ +uint32_t sve_vqm1_for_el(CPUARMState *env, int el); static inline bool is_a64(CPUARMState *env) { diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 0184845310..b1f040e69f 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -166,7 +166,7 @@ static off_t sve_fpcr_offset(uint32_t vq) static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return sve_vqm1_for_el(env, arm_current_el(env)) + 1; } static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0621944167..1b5d535788 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -925,7 +925,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { - int j, zcr_len = sve_zcr_len_for_el(env, el); + int j, zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 596878666d..07a6746944 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -152,7 +152,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1; return gdb_get_reg64(buf, vq * 2); } default: diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b6f31e9c8..cb44d528c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6225,7 +6225,7 @@ int sve_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); uint32_t len = cpu->sve_max_vq - 1; @@ -6248,7 +6248,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { int cur_el = arm_current_el(env); - int old_len = sve_zcr_len_for_el(env, cur_el); + int old_len = sve_vqm1_for_el(env, cur_el); int new_len; /* Bits other than [3:0] are RAZ/WI. */ @@ -6259,7 +6259,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len = sve_zcr_len_for_el(env, cur_el); + new_len = sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { aarch64_sve_narrow_vq(env, new_len + 1); } @@ -13683,7 +13683,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sve_el = 0; } } else if (sve_el == 0) { - DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el)); + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } @@ -14049,10 +14049,10 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, */ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len = (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? sve_vqm1_for_el(env, old_el) : 0); new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len = (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? sve_vqm1_for_el(env, new_el) : 0); /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { From patchwork Thu Jun 2 21:47:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NWY0ctmt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg5c5ll8z9s0w for ; Fri, 3 Jun 2022 08:04:04 +1000 (AEST) Received: from localhost ([::1]:46302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsvC-0000FJ-I4 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:04:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgo-0004fr-Hc for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:10 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:33133) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgk-0008UD-Ky for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:10 -0400 Received: by mail-pj1-x102e.google.com with SMTP id hv24-20020a17090ae41800b001e33eebdb5dso6070513pjb.0 for ; Thu, 02 Jun 2022 14:49:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F4rHpbD5Ee0Gqq7jh/rhx4dfJgd9LnpoppwR09o1CsY=; b=NWY0ctmtTpDldBeAWXB8jEGJcYtIubk5aMg3PW6/k3GtBw+HYdfEJBNnfmbRRDa8B3 uESckvfxNOoxel7Pu/E/+PramxgrR7qjz+gJkul9KLugCOeEjuaYgfxoQxNDQki0JgEU y/3LXTcW3I0CUCb9yeNWQBXec/GySElBb0AvfZaeRBBFWEkv/myo2wDW9KzqOB2jQ/qP 2Jqeo6kUIdcrH9bR9HviMOZ9qKEBmKvNN+cKU6+TOq2Q6IgHaDype8VIJzYTxAUPLmmP Tkd7D8AiIn3aRkIiYa5bvW1FxP9zqSDLf6CpodtZy5RiI4lhmDB2S84OeosJYTupyl4y iXBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F4rHpbD5Ee0Gqq7jh/rhx4dfJgd9LnpoppwR09o1CsY=; b=vTtjCFpPqDznNqzm6KE2UuOXr/+BOmtgURPwUnLuS4AFLMeJmbzzazxLqxkfsLDG1/ fQwtFnQGpp5Fbp0iHTdGX8fh3+8GR1JX0OJ3I0OKwnkIUpaKBtAKtPNFZAQSpzU0bdeH iEkNhFMged3PMaapyzZewMRsmdD4Nh+PC9XXMQRuaXJgYjU3vloEhwGLKN9bB6QUEbFh 7IHywjYVrvO7fv+6s4q3xP7qsMpT8d+E6+L8NzzJd7Bk04jwiZ7v6diVbz351KU7CMSs B53EOb9E963cx8jaai7F0wsrJcLiyt0BtXgTVo1O+36ATouvIvKn+Pb+QXrc6BKxTvFQ W/Ig== X-Gm-Message-State: AOAM531v6dPv3gR2/fDBwV4kIubiBTJANkKLtaxY+jvKdWpVI8RHa3E5 xw8HzF8NGgSQEzWpFUXrNnXweD/TS2tqdw== X-Google-Smtp-Source: ABdhPJwr5S7krxvxKnEqJyrPR1tIKEtG71IMeskEMu1DqU+ucsaLhpebcrO38xb5ggNbXUCVX8zvFg== X-Received: by 2002:a17:90b:4c8c:b0:1df:c760:e4af with SMTP id my12-20020a17090b4c8c00b001dfc760e4afmr7576996pjb.78.1654206545819; Thu, 02 Jun 2022 14:49:05 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 13/71] target/arm: Split out load/store primitives to sve_ldst_internal.h Date: Thu, 2 Jun 2022 14:47:55 -0700 Message-Id: <20220602214853.496211-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 127 +++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 107 +-------------------------- 2 files changed, 128 insertions(+), 106 deletions(-) create mode 100644 target/arm/sve_ldst_internal.h diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h new file mode 100644 index 0000000000..ef9117e84c --- /dev/null +++ b/target/arm/sve_ldst_internal.h @@ -0,0 +1,127 @@ +/* + * ARM SVE Load/Store Helpers + * + * Copyright (c) 2018-2022 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_SVE_LDST_INTERNAL_H +#define TARGET_ARM_SVE_LDST_INTERNAL_H + +#include "exec/cpu_ldst.h" + +/* + * Load one element into @vd + @reg_off from @host. + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); + +/* + * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). + * The controlling predicate is known to be true. + */ +typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, + target_ulong vaddr, uintptr_t retaddr); + +/* + * Generate the above primitives. + */ + +#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ +{ TYPEM val = HOST(host); *(TYPEE *)(vd + H(reg_off)) = val; } + +#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ +static inline void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ +{ TYPEM val = *(TYPEE *)(vd + H(reg_off)); HOST(host, val); } + +#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \ + intptr_t reg_off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPEM val = TLB(env, useronly_clean_ptr(addr), ra); \ + *(TYPEE *)(vd + H(reg_off)) = val; \ +} + +#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ +static inline void sve_##NAME##_tlb(CPUARMState *env, void *vd, \ + intptr_t reg_off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPEM val = *(TYPEE *)(vd + H(reg_off)); \ + TLB(env, useronly_clean_ptr(addr), val, ra); \ +} + +#define DO_LD_PRIM_1(NAME, H, TE, TM) \ + DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ + DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) + +DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) +DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) +DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) +DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) +DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) +DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) +DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) + +#define DO_ST_PRIM_1(NAME, H, TE, TM) \ + DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ + DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) + +DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) +DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) +DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) +DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) + +#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ + DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ + DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ + DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ + DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) + +#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ + DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ + DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ + DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ + DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) + +DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) +DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) +DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) +DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) +DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) + +DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) +DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) +DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) + +DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) +DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) +DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) + +DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) +DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) + +DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) +DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) + +#undef DO_LD_TLB +#undef DO_ST_TLB +#undef DO_LD_HOST +#undef DO_LD_PRIM_1 +#undef DO_ST_PRIM_1 +#undef DO_LD_PRIM_2 +#undef DO_ST_PRIM_2 + +#endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 3bdcd4ce9d..0c6dde00aa 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -21,12 +21,12 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" /* Return a value for NZCV as per the ARM PredTest pseudofunction. @@ -5301,111 +5301,6 @@ void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, * Load contiguous data, protected by a governing predicate. */ -/* - * Load one element into @vd + @reg_off from @host. - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_host_fn(void *vd, intptr_t reg_off, void *host); - -/* - * Load one element into @vd + @reg_off from (@env, @vaddr, @ra). - * The controlling predicate is known to be true. - */ -typedef void sve_ldst1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, - target_ulong vaddr, uintptr_t retaddr); - -/* - * Generate the above primitives. - */ - -#define DO_LD_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ \ - TYPEM val = HOST(host); \ - *(TYPEE *)(vd + H(reg_off)) = val; \ -} - -#define DO_ST_HOST(NAME, H, TYPEE, TYPEM, HOST) \ -static void sve_##NAME##_host(void *vd, intptr_t reg_off, void *host) \ -{ HOST(host, (TYPEM)*(TYPEE *)(vd + H(reg_off))); } - -#define DO_LD_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ - target_ulong addr, uintptr_t ra) \ -{ \ - *(TYPEE *)(vd + H(reg_off)) = \ - (TYPEM)TLB(env, useronly_clean_ptr(addr), ra); \ -} - -#define DO_ST_TLB(NAME, H, TYPEE, TYPEM, TLB) \ -static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off, \ - target_ulong addr, uintptr_t ra) \ -{ \ - TLB(env, useronly_clean_ptr(addr), \ - (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra); \ -} - -#define DO_LD_PRIM_1(NAME, H, TE, TM) \ - DO_LD_HOST(NAME, H, TE, TM, ldub_p) \ - DO_LD_TLB(NAME, H, TE, TM, cpu_ldub_data_ra) - -DO_LD_PRIM_1(ld1bb, H1, uint8_t, uint8_t) -DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) -DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) -DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) -DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) -DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) -DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) - -#define DO_ST_PRIM_1(NAME, H, TE, TM) \ - DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ - DO_ST_TLB(st1##NAME, H, TE, TM, cpu_stb_data_ra) - -DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) -DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) -DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) -DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) - -#define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ - DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ - DO_LD_HOST(ld1##NAME##_le, H, TE, TM, LD##_le_p) \ - DO_LD_TLB(ld1##NAME##_be, H, TE, TM, cpu_##LD##_be_data_ra) \ - DO_LD_TLB(ld1##NAME##_le, H, TE, TM, cpu_##LD##_le_data_ra) - -#define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ - DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \ - DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \ - DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \ - DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra) - -DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) -DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) -DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) -DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) -DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) - -DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) -DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) -DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) - -DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) -DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) -DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) - -DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) -DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) - -DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) -DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) - -#undef DO_LD_TLB -#undef DO_ST_TLB -#undef DO_LD_HOST -#undef DO_LD_PRIM_1 -#undef DO_ST_PRIM_1 -#undef DO_LD_PRIM_2 -#undef DO_ST_PRIM_2 - /* * Skip through a sequence of inactive elements in the guarding predicate @vg, * beginning at @reg_off bounded by @reg_max. Return the offset of the active From patchwork Thu Jun 2 21:47:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638462 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YE38Ne2A; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDfyn5qwMz9s0w for ; Fri, 3 Jun 2022 07:58:09 +1000 (AEST) Received: from localhost ([::1]:59644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwspT-0006oX-SR for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 17:58:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgp-0004hZ-Cf for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:11 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:45603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgm-00006r-61 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:10 -0400 Received: by mail-pf1-x432.google.com with SMTP id b135so5775806pfb.12 for ; Thu, 02 Jun 2022 14:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jaTWEUo9dEcM6jmweyaOFnw3wtRMGNYyznA/W1CTYmM=; b=YE38Ne2AkxHzJiKFoOsbogSXuTyLkxPIdtNAGRFpnDi/6vfnFBIfw3QuopPK1uJNd1 9MPLRlJerQOJOXweqHdd5Xtp/sXMYaFGC0BmmI74acCkQuI9jZHI1BXHGV4Nru4okG8a WMCmXVjXYVuQ/gKzRijrOeNIw9djtWjWQO5m8lx9/CwQruKGYw/6uBy4YhDnwaEYoRoL Uz85uAzuXqA0l14ct56TZeje54F6j0+7ekHnIeC2A62hwGL9R9t6f62GiIFkTi039oK3 o702noYelw2eBQudgiyTPXX+75RNJVT/kjMTjRVsK2jf71rlOv39XSV91z/1zMXxyBDj 3CiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jaTWEUo9dEcM6jmweyaOFnw3wtRMGNYyznA/W1CTYmM=; b=qDqVVop+Q745O/sZEAa4YviBZeQCN22X0HNFw7R5oA1Qo61X6eqgEh5XU7r0LoeniK kGp+IRiAStf9np2SRzKP+drCaRJ76oPD82fizfzR6JWV5ETwpm4E0Z9yguEkoMWBh0Fm 1lwfHqdFqag63wnjUYObECh+RIbBAAfxp8J754bUtOHvnNNOKh2qZhucv5WgtLXVQPtY LFml+InTDVI6SKnB1S/O+0oM7j9q/k/vWBop5kTP7kX7qJndbItBy16sQpFjAAq2kJYC 2gOUkYKreN0Bm/w1UdhYo76HaagNs9T2bB8YNqA3VHChydC2rSrVACfmIUW0gjpmBwkR lJAQ== X-Gm-Message-State: AOAM53298hXfidPMzsNy3/2cNnus31dj4yj+LxL6SQeNqsowcxi01iCH wOn2E7wS47deN9guZsAgrg8g3OixylvV9w== X-Google-Smtp-Source: ABdhPJyLw5LDta804Lw/h2d2libeAeAv9wRk3chofm97r3xhvTlQWtHnz16ujhKILEhHeziooTyYoQ== X-Received: by 2002:a05:6a00:2341:b0:51b:dd96:c7c1 with SMTP id j1-20020a056a00234100b0051bdd96c7c1mr1484030pfj.14.1654206546554; Thu, 02 Jun 2022 14:49:06 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 14/71] target/arm: Export sve contiguous ldst support functions Date: Thu, 2 Jun 2022 14:47:56 -0700 Message-Id: <20220602214853.496211-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 94 ++++++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 87 ++++++------------------------- 2 files changed, 111 insertions(+), 70 deletions(-) diff --git a/target/arm/sve_ldst_internal.h b/target/arm/sve_ldst_internal.h index ef9117e84c..b5c473fc48 100644 --- a/target/arm/sve_ldst_internal.h +++ b/target/arm/sve_ldst_internal.h @@ -124,4 +124,98 @@ DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) #undef DO_LD_PRIM_2 #undef DO_ST_PRIM_2 +/* + * Resolve the guest virtual address to info->host and info->flags. + * If @nofault, return false if the page is invalid, otherwise + * exit via page fault exception. + */ + +typedef struct { + void *host; + int flags; + MemTxAttrs attrs; +} SVEHostPage; + +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + +/* + * Analyse contiguous data, protected by a governing predicate. + */ + +typedef enum { + FAULT_NO, + FAULT_FIRST, + FAULT_ALL, +} SVEContFault; + +typedef struct { + /* + * First and last element wholly contained within the two pages. + * mem_off_first[0] and reg_off_first[0] are always set >= 0. + * reg_off_last[0] may be < 0 if the first element crosses pages. + * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] + * are set >= 0 only if there are complete elements on a second page. + * + * The reg_off_* offsets are relative to the internal vector register. + * The mem_off_first offset is relative to the memory address; the + * two offsets are different when a load operation extends, a store + * operation truncates, or for multi-register operations. + */ + int16_t mem_off_first[2]; + int16_t reg_off_first[2]; + int16_t reg_off_last[2]; + + /* + * One element that is misaligned and spans both pages, + * or -1 if there is no such active element. + */ + int16_t mem_off_split; + int16_t reg_off_split; + + /* + * The byte offset at which the entire operation crosses a page boundary. + * Set >= 0 if and only if the entire operation spans two pages. + */ + int16_t page_split; + + /* TLB data for the two pages. */ + SVEHostPage page[2]; +} SVEContLdSt; + +/* + * Find first active element on each page, and a loose bound for the + * final element on each page. Identify any single element that spans + * the page boundary. Return true if there are any active elements. + */ +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg, + intptr_t reg_max, int esz, int msize); + +/* + * Resolve the guest virtual addresses to info->page[]. + * Control the generation of page faults with @fault. Return false if + * there is no work to do, which can only happen with @fault == FAULT_NO. + */ +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr); + +#ifdef CONFIG_USER_ONLY +static inline void +sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, uint64_t *vg, + target_ulong addr, int esize, int msize, + int wp_access, uintptr_t retaddr) +{ } +#else +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr); +#endif + +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, uint64_t *vg, + target_ulong addr, int esize, int msize, + uint32_t mtedesc, uintptr_t ra); + #endif /* TARGET_ARM_SVE_LDST_INTERNAL_H */ diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 0c6dde00aa..8cd371e3e3 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -5341,16 +5341,9 @@ static intptr_t find_next_active(uint64_t *vg, intptr_t reg_off, * exit via page fault exception. */ -typedef struct { - void *host; - int flags; - MemTxAttrs attrs; -} SVEHostPage; - -static bool sve_probe_page(SVEHostPage *info, bool nofault, - CPUARMState *env, target_ulong addr, - int mem_off, MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) +bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, + target_ulong addr, int mem_off, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int flags; @@ -5406,59 +5399,13 @@ static bool sve_probe_page(SVEHostPage *info, bool nofault, return true; } - -/* - * Analyse contiguous data, protected by a governing predicate. - */ - -typedef enum { - FAULT_NO, - FAULT_FIRST, - FAULT_ALL, -} SVEContFault; - -typedef struct { - /* - * First and last element wholly contained within the two pages. - * mem_off_first[0] and reg_off_first[0] are always set >= 0. - * reg_off_last[0] may be < 0 if the first element crosses pages. - * All of mem_off_first[1], reg_off_first[1] and reg_off_last[1] - * are set >= 0 only if there are complete elements on a second page. - * - * The reg_off_* offsets are relative to the internal vector register. - * The mem_off_first offset is relative to the memory address; the - * two offsets are different when a load operation extends, a store - * operation truncates, or for multi-register operations. - */ - int16_t mem_off_first[2]; - int16_t reg_off_first[2]; - int16_t reg_off_last[2]; - - /* - * One element that is misaligned and spans both pages, - * or -1 if there is no such active element. - */ - int16_t mem_off_split; - int16_t reg_off_split; - - /* - * The byte offset at which the entire operation crosses a page boundary. - * Set >= 0 if and only if the entire operation spans two pages. - */ - int16_t page_split; - - /* TLB data for the two pages. */ - SVEHostPage page[2]; -} SVEContLdSt; - /* * Find first active element on each page, and a loose bound for the * final element on each page. Identify any single element that spans * the page boundary. Return true if there are any active elements. */ -static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, - uint64_t *vg, intptr_t reg_max, - int esz, int msize) +bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, uint64_t *vg, + intptr_t reg_max, int esz, int msize) { const int esize = 1 << esz; const uint64_t pg_mask = pred_esz_masks[esz]; @@ -5548,9 +5495,9 @@ static bool sve_cont_ldst_elements(SVEContLdSt *info, target_ulong addr, * Control the generation of page faults with @fault. Return false if * there is no work to do, which can only happen with @fault == FAULT_NO. */ -static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, - CPUARMState *env, target_ulong addr, - MMUAccessType access_type, uintptr_t retaddr) +bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, + CPUARMState *env, target_ulong addr, + MMUAccessType access_type, uintptr_t retaddr) { int mmu_idx = cpu_mmu_index(env, false); int mem_off = info->mem_off_first[0]; @@ -5606,12 +5553,12 @@ static bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault fault, return have_work; } -static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, - int esize, int msize, int wp_access, - uintptr_t retaddr) -{ #ifndef CONFIG_USER_ONLY +void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, + int esize, int msize, int wp_access, + uintptr_t retaddr) +{ intptr_t mem_off, reg_off, reg_last; int flags0 = info->page[0].flags; int flags1 = info->page[1].flags; @@ -5667,12 +5614,12 @@ static void sve_cont_ldst_watchpoints(SVEContLdSt *info, CPUARMState *env, } while (reg_off & 63); } while (reg_off <= reg_last); } -#endif } +#endif -static void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, - uint64_t *vg, target_ulong addr, int esize, - int msize, uint32_t mtedesc, uintptr_t ra) +void sve_cont_ldst_mte_check(SVEContLdSt *info, CPUARMState *env, + uint64_t *vg, target_ulong addr, int esize, + int msize, uint32_t mtedesc, uintptr_t ra) { intptr_t mem_off, reg_off, reg_last; From patchwork Thu Jun 2 21:47:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638471 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=MwxX3puf; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgCD1PcCz9s0w for ; Fri, 3 Jun 2022 08:08:56 +1000 (AEST) Received: from localhost ([::1]:54906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwszu-0006MG-9E for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:08:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgp-0004hy-Q7 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:11 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:53061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgm-0008U5-HP for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:11 -0400 Received: by mail-pj1-x1033.google.com with SMTP id gd1so6024314pjb.2 for ; Thu, 02 Jun 2022 14:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XuOHiX6D0El6nNEd2Jyo7d9eF8KMwz8jltCon2kVgiU=; b=MwxX3pufgmoBkSuklsbXMX4fKzczM0WS5VRsi27d15kggwaf9opVpHVEkLUoI2AeW2 LhX7WOd9KoTHsD9JTXYVtCFL/YS9ntRAMcsrxNoV/2L36eRONV7lSG2kR9x5fPdJ3PAo frizYBhAcOMG1JU4ruXGd4e14Htbpg1ddLS2kuzQbAhKYCZ6sS+y395UTv7Ll7XE3hH2 lPevEGg+0R494Y0FrlPANnxz1hCyuwzuVVekTGtMP/WNNhD2XMTKyLaSjiULzonzl9hi w6BDok25WjPLKDhETbOHiQ1mEA0VH30kC+AOS/2JKaoSU3ylQVaLrjXAVJoR6clqh2xm dSuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XuOHiX6D0El6nNEd2Jyo7d9eF8KMwz8jltCon2kVgiU=; b=2YrlzG4+ptjZi/R+4Hd+vdZJ0Izt82nOEnLocUH7PsyHx0r3J6LzXobehB03HIkP5L P7NAGl6XnNg86kfFipZ7LVDVHrug1yARIeTelCg8mq+C1L1aRlJU/+0Yo4+bEV58tYqW RnSJQxvPIWKHE10zJ2zc1vvKYY6TTEli4KMqqMzTgT/qgfm9wKgSS/jQ3Wi/ytf6oaUP el3Wsr4YSM1vzzXuESdlRLvj9Ci8MjyG6tb/bFZNIse1LVEt+xU4jUXGYBRDABLk4ip1 lPAmBCw/F0IcwrYTE8eI/fak7RsG12ZnH3rC7RmYKQOBwEFY1oE5OtyK6wX9uGRUQ+Xx yshA== X-Gm-Message-State: AOAM533TA+55UR93ZLW6XpQzjnuGVZQ3atWA/AQorzONOXEp70ymeRA6 hITgWZkQ/kRCaRa+nkUfE09TR5JtyNvx/Q== X-Google-Smtp-Source: ABdhPJzO2hhmoaxuW6Dnk8BHU6M2G/C/uhj/3o/2sFJpqxHSZ8d2YkUN3pZ2pCEa3K1AIHLTlbuhMg== X-Received: by 2002:a17:90a:10f:b0:1e3:3f45:796a with SMTP id b15-20020a17090a010f00b001e33f45796amr7406799pjb.136.1654206547562; Thu, 02 Jun 2022 14:49:07 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 15/71] target/arm: Move expand_pred_b to vec_internal.h Date: Thu, 2 Jun 2022 14:47:57 -0700 Message-Id: <20220602214853.496211-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Put the inline function near the array declaration. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 8 +++++++- target/arm/sve_helper.c | 9 --------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d63402042..d1a1ea4a66 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -50,8 +50,14 @@ #define H8(x) (x) #define H1_8(x) (x) -/* Data for expanding active predicate bits to bytes, for byte elements. */ +/* + * Expand active predicate bits to bytes, for byte elements. + */ extern const uint64_t expand_pred_b_data[256]; +static inline uint64_t expand_pred_b(uint8_t byte) +{ + return expand_pred_b_data[byte]; +} static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8cd371e3e3..e865c12527 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,15 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32_t words) return flags; } -/* - * Expand active predicate bits to bytes, for byte elements. - * (The data table itself is in vec_helper.c as MVE also needs it.) - */ -static inline uint64_t expand_pred_b(uint8_t byte) -{ - return expand_pred_b_data[byte]; -} - /* Similarly for half-word elements. * for (i = 0; i < 256; ++i) { * unsigned long m = 0; From patchwork Thu Jun 2 21:47:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=KNfZlP6y; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg6B1qVLz9s0w for ; Fri, 3 Jun 2022 08:04:34 +1000 (AEST) Received: from localhost ([::1]:48644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsvg-0001xf-4h for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:04:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgr-0004jc-K6 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:13 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:39778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgo-00007f-5q for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:12 -0400 Received: by mail-pf1-x42d.google.com with SMTP id y196so5796170pfb.6 for ; Thu, 02 Jun 2022 14:49:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVdCbtqKJB+BGb16fkMGEP1znoVx5B0GA093B8K9G20=; b=KNfZlP6yJZDFXACTPRfi4EbrMfgsEzutIG3+fbyxZpaeovls7niVdVVVFPRttkO2pP il04JEDcxu5V3N5cZVWv6D2fXZOo2XRamhbwInmkP/D9EXd29zLvLf5p9j9pdb8VnLD/ E0eLyUkhmHynlSVaT1ZokQIQ7viKhJM/69ttuE7JFVWKnkhkCl0RhocqBwyX3yk6a000 7Iz6nBXaEMSxCRQoT7QEfhQELIgrGBCoFXFJ2/Cb+wIP87rX2giACzYxO1ZBnSqbb+8X uudmtc0p3QLvNTTovmYjAvgi+DAUIYkD5ntN/uT1tHic0xZiQzfhr8OzxA1A0bmtQHfX lt4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVdCbtqKJB+BGb16fkMGEP1znoVx5B0GA093B8K9G20=; b=aV7Q83qKPw8xrjb12gO/7wBfXLGs2g9okdEM9gZyv7NzsSZI1ClBLjdlEowA8r3rGL E2j55FpaEzQr+tqvgYfJEKYHuBVP9G2lod+Bk87g4Ti4dAjLOFRw1b8DzWzy12j4Phfe rO2f9R0XNBMoirmbDLVyka/h7aKC5oGeY625qOu1I96mmRgQUP7SFCNKqm+shnbPt6Di hzmg+MZL1+sYEB56rBV185dW2c8nJatXhAP8XKmohPRRUG7QVpu1YDoudoXa10+usZu2 Fo1ibh5JFI3mwrZeMp03acMvNw7psx/tICDsKZCPxpaiNvSxs4/rCuafSLL/0F+aoO5N 7AKA== X-Gm-Message-State: AOAM531a+CYVygZzGM6DZ9pBmcXPpALw0gkEw02yuGCDC2u5/BQf25zU 38xqNIrRCuxmAoRRa9p037aYnIRwFi2dgg== X-Google-Smtp-Source: ABdhPJxijk1ucxea59Kl2mepk90PCk+ARkva2AN01ieXBptqQVHZ4NB4vawI4WlwK4CZAghJy27Tbg== X-Received: by 2002:a62:1784:0:b0:51b:bc40:28a7 with SMTP id 126-20020a621784000000b0051bbc4028a7mr7108669pfx.55.1654206548406; Thu, 02 Jun 2022 14:49:08 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 16/71] target/arm: Use expand_pred_b in mve_helper.c Date: Thu, 2 Jun 2022 14:47:58 -0700 Message-Id: <20220602214853.496211-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to do nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses the entire uint64_t result. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/mve_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 846962bf4c..403b345ea3 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -726,7 +726,7 @@ static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) { - uint16_t bmask = expand_pred_b_data[mask & 3]; + uint16_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } @@ -737,7 +737,7 @@ static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) { - uint32_t bmask = expand_pred_b_data[mask & 0xf]; + uint32_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } @@ -748,7 +748,7 @@ static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) { - uint64_t bmask = expand_pred_b_data[mask & 0xff]; + uint64_t bmask = expand_pred_b(mask); *d = (*d & ~bmask) | (r & bmask); } From patchwork Thu Jun 2 21:47:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638476 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lXrwu39I; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgGk2YDQz9s0w for ; Fri, 3 Jun 2022 08:11:58 +1000 (AEST) Received: from localhost ([::1]:37562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt2q-0005FG-Ds for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:11:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgs-0004lL-I2 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:15 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgo-00007w-NX for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:13 -0400 Received: by mail-pg1-x530.google.com with SMTP id e66so5779812pgc.8 for ; Thu, 02 Jun 2022 14:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lRGebQyqBWSguPRywmTvdJmhpPUXlvnLMmD10I0JmJc=; b=lXrwu39I4hZ8xZuBJ/xJTwzvbO4UwmhjQ9vsm3hMeSTwAjq+EqmXjZ8a63nkBt5tfC mdDrxLu4tYeH0tG+95j9ouedL7BAbzEmJw37MzLS4bwPlF7JtQsUApCGkDq+akCzpJOD JnzMoT51DP1J+zWt7gIHeKo+h2hxd0Ly3dnKltfs6KA7P+xe0d5DxCRsOpJZzhvlR65V r6Uz9MA7eHKI/rsIbfzSrsN3Y09oYcx4M8/QtVueg9VYILC0Tk8wgNkboR1oHjKSE6JQ ZiVc/w2L3eOPBEfbmv4qVoTKnVv/4MX5eCN1lJ2GyKWIktrzaQXCL7+MWdONQdpPDhvl tuQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lRGebQyqBWSguPRywmTvdJmhpPUXlvnLMmD10I0JmJc=; b=LtKwz+xjOIRgaKXZFIY9wuxyqesEHcF9uF+1PpYgftmnSg9kaWmdm74ytjTbaUtpd9 h4IAGXsNszL2fAmXzdSj0u9SN+2+niH/xJQbeoK2KIMtFmYMI5hMGyfNy/QW+WSP7KTn DvJdNn92haxU0dWoZrYYTPf3btSSzuzezlKj4t2Z1DcDLkvaTd2IZ8HV7hpJXBIEwXkJ TTlcq3JzV80IGq4YB8bK8S4nl+OvbHI1QmaLaZAUGEQ7UHCcW2CJ56MlYkE3bcuv+gGw 1tWG+neuy9gvAc8+XmnBW4Nno8GjyHPmxUG74njlgJjA3kRTm/IjDBdMVmInBwZNLe2W +EtQ== X-Gm-Message-State: AOAM531sZ526d/Bj7aar172bug1O5GFTHKedY7yRydABdlxxxPkCaP2B d7x2R31JoZ93Gy1Lzj9kkmxoz+XjuPywYA== X-Google-Smtp-Source: ABdhPJxoej2DycQ7y7ni5oRi0XCGIdCYKNium1tTkacfD6GbsvDxf6zQfkNlT9eMr/glCf7MU/QCQw== X-Received: by 2002:a65:44c2:0:b0:3fa:8a91:1ae9 with SMTP id g2-20020a6544c2000000b003fa8a911ae9mr5966968pgs.412.1654206549415; Thu, 02 Jun 2022 14:49:09 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 17/71] target/arm: Move expand_pred_h to vec_internal.h Date: Thu, 2 Jun 2022 14:47:59 -0700 Message-Id: <20220602214853.496211-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the data to vec_helper.c and the inline to vec_internal.h. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 7 +++++++ target/arm/sve_helper.c | 29 ----------------------------- target/arm/vec_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 29 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index d1a1ea4a66..1d527fadac 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -59,6 +59,13 @@ static inline uint64_t expand_pred_b(uint8_t byte) return expand_pred_b_data[byte]; } +/* Similarly for half-word elements. */ +extern const uint64_t expand_pred_h_data[0x55 + 1]; +static inline uint64_t expand_pred_h(uint8_t byte) +{ + return expand_pred_h_data[byte & 0x55]; +} + static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { uint64_t *d = vd + opr_sz; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index e865c12527..1654c0bbf9 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,35 +103,6 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, uint32_t words) return flags; } -/* Similarly for half-word elements. - * for (i = 0; i < 256; ++i) { - * unsigned long m = 0; - * if (i & 0xaa) { - * continue; - * } - * for (j = 0; j < 8; j += 2) { - * if ((i >> j) & 1) { - * m |= 0xfffful << (j << 3); - * } - * } - * printf("[0x%x] = 0x%016lx,\n", i, m); - * } - */ -static inline uint64_t expand_pred_h(uint8_t byte) -{ - static const uint64_t word[] = { - [0x01] = 0x000000000000ffff, [0x04] = 0x00000000ffff0000, - [0x05] = 0x00000000ffffffff, [0x10] = 0x0000ffff00000000, - [0x11] = 0x0000ffff0000ffff, [0x14] = 0x0000ffffffff0000, - [0x15] = 0x0000ffffffffffff, [0x40] = 0xffff000000000000, - [0x41] = 0xffff00000000ffff, [0x44] = 0xffff0000ffff0000, - [0x45] = 0xffff0000ffffffff, [0x50] = 0xffffffff00000000, - [0x51] = 0xffffffff0000ffff, [0x54] = 0xffffffffffff0000, - [0x55] = 0xffffffffffffffff, - }; - return word[byte & 0x55]; -} - /* Similarly for single word elements. */ static inline uint64_t expand_pred_s(uint8_t byte) { diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 17fb158362..26c373e522 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -127,6 +127,32 @@ const uint64_t expand_pred_b_data[256] = { 0xffffffffffffffff, }; +/* + * Similarly for half-word elements. + * for (i = 0; i < 256; ++i) { + * unsigned long m = 0; + * if (i & 0xaa) { + * continue; + * } + * for (j = 0; j < 8; j += 2) { + * if ((i >> j) & 1) { + * m |= 0xfffful << (j << 3); + * } + * } + * printf("[0x%x] = 0x%016lx,\n", i, m); + * } + */ +const uint64_t expand_pred_h_data[0x55 + 1] = { + [0x01] = 0x000000000000ffff, [0x04] = 0x00000000ffff0000, + [0x05] = 0x00000000ffffffff, [0x10] = 0x0000ffff00000000, + [0x11] = 0x0000ffff0000ffff, [0x14] = 0x0000ffffffff0000, + [0x15] = 0x0000ffffffffffff, [0x40] = 0xffff000000000000, + [0x41] = 0xffff00000000ffff, [0x44] = 0xffff0000ffff0000, + [0x45] = 0xffff0000ffffffff, [0x50] = 0xffffffff00000000, + [0x51] = 0xffffffff0000ffff, [0x54] = 0xffffffffffff0000, + [0x55] = 0xffffffffffffffff, +}; + /* Signed saturating rounding doubling multiply-accumulate high half, 8-bit */ int8_t do_sqrdmlah_b(int8_t src1, int8_t src2, int8_t src3, bool neg, bool round) From patchwork Thu Jun 2 21:48:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638473 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=aknP+xaE; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgCt54hGz9s0w for ; Fri, 3 Jun 2022 08:09:30 +1000 (AEST) Received: from localhost ([::1]:57264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt0S-0007z6-JP for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:09:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgs-0004lU-IO for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:15 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:42510) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgp-00008E-Iv for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:14 -0400 Received: by mail-pg1-x534.google.com with SMTP id d129so5786601pgc.9 for ; Thu, 02 Jun 2022 14:49:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gapMUzbWXEa1xXFszg2jbZqJLMbZQGkHBtGV0RlKTO8=; b=aknP+xaE3VnJiWAP98x59yW/zCR2tdQTtsmsSZCjiGVVxRGYADAk7ADq6BXE+eSWoP o4Fw7heXiEWSTz+rRAjSLzd6FCAU8kMsFgJs2Mkh1OG5kNZApnphwvcmoXg4wV9hx3c2 afNyFW3Ga9VOpYmEcpfKRaaB0sptYT6N/QrY3vLUTH0T6sM5VS7VVk+DU/LCF+jC35m9 pa8758VRpTSnxzu23ceXXr7mylhbSA01EzDLHNAQxCk5bLHz1QCWRW91eUoPLXxfJyPt oheU3m/P7qIAsGR2DtymLb+EppSmSmMJ1siyp68tiMJtMjxcLxM/PWEca4TsMmpUvWiB uJTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gapMUzbWXEa1xXFszg2jbZqJLMbZQGkHBtGV0RlKTO8=; b=5JnAzDTRCyLUdrDNOjxdzBWM2n6O+t3bzJBWPqA0w+I669KEgJ8IVmQUPxMgpCf8Je m0kodJuTBcoLlYjqjqIfaekHxGE+mqAROZm63dpviuEB5X2Ru5WZ9DRcdoCzEwHrbUi7 2gXx4OIsBDWAQqMoxMULpRdVEPxjnix/X7235zRm40l18Bi1qi1UHk3/O790VfQC26Mu FJJ5e6QGPixb3evULO9rW7SNeJ9FriY1f1wdK4UU8BeZnnIC2KQP8j5TiUxpnBeFioUg soervJz9qDMNRmGFI6PiG7XGxZRNP5olSpCKCf3ABLy5sg51H9eqEywwfRHkGGqR62Wv 9tpg== X-Gm-Message-State: AOAM531M/2E1Dh/VQwGWMaEVcgx7aFa3gquWgy9SJF7Ef4hQnpxFm1Zm JvWQqlN4t6lk2To238/hiOUGV1Rrp3/0sQ== X-Google-Smtp-Source: ABdhPJwXmnimFytrSLtgQhq0z9C0SeudfLzhYQK3ZG5TZjfdmz5P2OOGyZpCiGaJ3+LplYn2UPJLkw== X-Received: by 2002:a62:820a:0:b0:51b:d1f9:b45f with SMTP id w10-20020a62820a000000b0051bd1f9b45fmr3544959pfd.63.1654206550275; Thu, 02 Jun 2022 14:49:10 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH 18/71] target/arm: Export bfdotadd from vec_helper.c Date: Thu, 2 Jun 2022 14:48:00 -0700 Message-Id: <20220602214853.496211-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We will need this over in sme_helper.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 13 +++++++++++++ target/arm/vec_helper.c | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d527fadac..1f4ed80ff7 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -230,4 +230,17 @@ uint64_t pmull_h(uint64_t op1, uint64_t op2); */ uint64_t pmull_w(uint64_t op1, uint64_t op2); +/** + * bfdotadd: + * @sum: addend + * @e1, @e2: multiplicand vectors + * + * BFloat16 2-way dot product of @e1 & @e2, accumulating with @sum. + * The @e1 and @e2 operands correspond to the 32-bit source vector + * slots and contain two Bfloat16 values each. + * + * Corresponds to the ARM pseudocode function BFDotAdd. + */ +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2); + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 26c373e522..9a9c034e36 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2557,7 +2557,7 @@ DO_MMLA_B(gvec_usmmla_b, do_usmmla_b) * BFloat16 Dot Product */ -static float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) +float32 bfdotadd(float32 sum, uint32_t e1, uint32_t e2) { /* FPCR is ignored for BFDOT and BFMMLA. */ float_status bf_status = { From patchwork Thu Jun 2 21:48:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=FeyuXHtT; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg4h39FGz9s0w for ; Fri, 3 Jun 2022 08:03:16 +1000 (AEST) Received: from localhost ([::1]:43618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsuQ-0006u4-Bl for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:03:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgu-0004ml-8i for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:16 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:45770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgr-00008t-QQ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:15 -0400 Received: by mail-pj1-x1031.google.com with SMTP id w2-20020a17090ac98200b001e0519fe5a8so5868523pjt.4 for ; Thu, 02 Jun 2022 14:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vL9SSDiS59z0r3Skz7kY+nA3z0bl4IpSAevgPDF0S/k=; b=FeyuXHtTx+uWD07S5A0RQUT322tzQkEeATVNcn8UGx5BOcAkz6wdqUphYdt4GHVEX1 1JUH6eiDZx/2+s1NfhTRIhRIpRYhnUWbFZHDCvXOBz3Y3LPhkOm/iAxjCo3CA9n1oR3p d6rW3Kd9f1PeoGflJM9wqZ/4OOJSEMsDeaqu99OAQPeuMKshUN0pd+7xTc3duQ0hRROP qZ3OFfBkcBt04aFtUlPxOeeg/uEHUeYE67RYWNv7sCrID2XqRJQO2FqHdpzy9z4bwDKx MUQeBAQScZP7s1fIlVesaFTt6iocSRwksmkOe60kbKxBJrrblXCyG64I0Qozy3Hica7x Qm+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vL9SSDiS59z0r3Skz7kY+nA3z0bl4IpSAevgPDF0S/k=; b=skdQIbAc1l8UzsOLcQCtW3ql+wE3UIcFlt1lVKV1CVBUX63Gppr8TQG0ZBfbk9KJE7 r+cZW/5j/qQgpQXHOR+1yJLHcNtxeqSvzoIORY5g7pu3xwX1BbJaFVs9CdYfvK/SAPUV 460G89zdkumA9gD/NCvNzuS6wEvRB2KymmV9rY+NFxbWkFXa3YzLOrYsxQ6LX9EEnaqE rvYyQLFta30vEI86P6jym5mW6CNxx39UdQwH/dxBFtxNJz6FqxfGHSNYdm98VU9X2x5H uEjjmbRSKFT+WLtHAVCkMRtFk4oYYMf6eAl1dUUVEXlnXvkbRLaDXimtQGFx0XOxcPI7 Tecw== X-Gm-Message-State: AOAM533IVAjAExTcf80VRZm4lnTHSGXsa41HYY0g4ypl0+yMl1zvMTfK MbL/MeJkb/uenika3RDMQDT/C/2kZgZtQQ== X-Google-Smtp-Source: ABdhPJxpMA7I063WzQ2uGaq0sJd/cywVqQjyHFTC+B1tl1pPNP/oy44U21G1TYaa2yh2/hak2+F4zw== X-Received: by 2002:a17:902:d502:b0:161:bc5f:7b2d with SMTP id b2-20020a170902d50200b00161bc5f7b2dmr6834665plg.140.1654206551245; Thu, 02 Jun 2022 14:49:11 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 19/71] target/arm: Add isar_feature_aa64_sme Date: Thu, 2 Jun 2022 14:48:01 -0700 Message-Id: <20220602214853.496211-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be used for implementing FEAT_SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb37787c35..f6d114aad7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,11 @@ static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; } +static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; +} + static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && From patchwork Thu Jun 2 21:48:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638479 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Eno09yC5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgL84H4Dz9s0w for ; Fri, 3 Jun 2022 08:14:56 +1000 (AEST) Received: from localhost ([::1]:45314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt5h-0001zW-Dx for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:14:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgu-0004n3-I7 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:16 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41491) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgs-000090-8a for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:16 -0400 Received: by mail-pg1-x532.google.com with SMTP id e66so5779886pgc.8 for ; Thu, 02 Jun 2022 14:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IYMOwEB0ADTMl9SBwIXKgrIqkj0CMNexLOCc9Adz/Xk=; b=Eno09yC5hYVl0bcdjW7hCxXYmgIN1VrtcVyyaJ3LsCktujR7DgXOiYEynlTC3V+G/I gHBL9KY1NWxC+7g4p+cJbEYtCV3mj8HvZnssga+pSTApy3dMo4cLMJiRGFxjjnH/Zp/9 214vIkuxJLnnGxLpmTL77g/1TwhZebasBV1TilakGxaGrvFUIugaNiX3Gf8oVokG2voy BBnTS4QsPaVQGWCqHNZDKeoM0HNYH6jbTKJgW7p4kkOYG98f8bvZhdL1Po4CE51sY4Wr b4n/tHfh1ekXFQbow8Lgjaio2sWgmsEQGuRceTpKxRpcfkFoAk30Q5wN4ZV3kGhFwLlr tmnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IYMOwEB0ADTMl9SBwIXKgrIqkj0CMNexLOCc9Adz/Xk=; b=vSiQ4xaCUJZNa9lP5ti322cyqrQc8s+pl57jKxzJEQbw62yDnBUqD6fk2yx40ADuY4 Izds9e74HD+0qJXCtaq0Czsz9qsPh9d2YL9/OWX95a+j0rvCMTa3vmLWkXxb8mCBTNWQ SsPsh4F4iA+zo3NQ/cM+siD7bVHPyD5nEaWJQ9louE0X/hDGCFcEvGwHIsph1L5zQ7J5 Tg7lZCuyf8t+VSJItLd1oxuHWRrJeWsL23b5GrUSoC4UrqhQ79YeQZo5elPaxFEza0Mo FOePkWbLpSBQr7A8YLy5WaG5SuNkrj+vgI6K6t5qlYwoFkcCH7zux8hwKlCDlu6rQ560 x+tw== X-Gm-Message-State: AOAM532w4AdPmA2q6vWGATz2a7wwCCnqO8TjxjzwQCfncGMS9tanghFo 8meEOb8pL5v9/Iq+kLW5Uu95VXuA5SPHQw== X-Google-Smtp-Source: ABdhPJzVNXsNw57DZbxkYGQDOgNVMn7sLKbYZVK0jO3SRXExldkHzm4CEYyckM7PgK0pZYAEh7E+kQ== X-Received: by 2002:a05:6a02:19b:b0:3fa:3e63:15fb with SMTP id bj27-20020a056a02019b00b003fa3e6315fbmr6117770pgb.129.1654206551981; Thu, 02 Jun 2022 14:49:11 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 20/71] target/arm: Add ID_AA64SMFR0_EL1 Date: Thu, 2 Jun 2022 14:48:02 -0700 Message-Id: <20220602214853.496211-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This register is allocated from the existing block of id registers, so it is already RES0 for cpus that do not implement SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 25 +++++++++++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 9 +++++---- 3 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f6d114aad7..24c5266f35 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -966,6 +966,7 @@ struct ArchCPU { uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; + uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; } isar; uint64_t midr; @@ -2190,6 +2191,15 @@ FIELD(ID_AA64ZFR0, I8MM, 44, 4) FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) +FIELD(ID_AA64SMFR0, F32F32, 32, 1) +FIELD(ID_AA64SMFR0, B16F32, 34, 1) +FIELD(ID_AA64SMFR0, F16F32, 35, 1) +FIELD(ID_AA64SMFR0, I8I32, 36, 4) +FIELD(ID_AA64SMFR0, F64F64, 48, 1) +FIELD(ID_AA64SMFR0, I16I64, 52, 4) +FIELD(ID_AA64SMFR0, SMEVER, 56, 4) +FIELD(ID_AA64SMFR0, FA64, 63, 1) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) @@ -4190,6 +4200,21 @@ static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; } +static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); +} + +static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; +} + +static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cb44d528c0..48534db0bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7732,11 +7732,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64zfr0 }, - { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64smfr0 }, { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b3f635fc95..28001643c6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -682,13 +682,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ahcf->isar.id_aa64pfr0 = t; /* - * Before v5.1, KVM did not support SVE and did not expose - * ID_AA64ZFR0_EL1 even as RAZ. After v5.1, KVM still does - * not expose the register to "user" requests like this - * unless the host supports SVE. + * KVM began exposing the unallocated ID registers as RAZ in 4.15. + * Using SVE supported is an easy way to tell if these registers + * are exposed, since both of these depend on SVE anyway. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); } kvm_arm_destroy_scratch_host_vcpu(fdarray); From patchwork Thu Jun 2 21:48:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=K07nzk3f; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgGY4hSCz9s0w for ; Fri, 3 Jun 2022 08:11:49 +1000 (AEST) Received: from localhost ([::1]:36816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt2h-0004hd-N5 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:11:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgt-0004mS-NO for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:16 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:44685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgr-0008Vf-Gt for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:15 -0400 Received: by mail-pg1-x536.google.com with SMTP id u4so2827460pgk.11 for ; Thu, 02 Jun 2022 14:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FoWoKSqjjh68VSQj0A5P4qFwMda5yvhWWmestbQu+sY=; b=K07nzk3fzt1RoU69tILYMc49hbNKsxvDIX6uWYKwRhtbi7XidF+KFHASCiq1hwRB8i Pcp1fi5i7qg7gFwxCDM7RIxo4MsoE/fgJIb8LslwIpFCXs42Jjt716eBgYku7Pj3LCyN FnVXLpoae8+JBW1zz2gbOc6mYJye+TqKY2lewxHbUTo9e7d4U6lX62eX6TtmboS4mt42 yRLuLFe6xL1H6ILqfAWyWVGapgs9aqN2Wb3qfOuuLh0BIaDt9l9fOcVfrtjZbtHJ8ddU tjgScKaf15k3c0yLwlC8qOUWuGIeFv3oxY57qHM8+jIhKDE+NFjCtHfqtqTXCL+E6k5W d+aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FoWoKSqjjh68VSQj0A5P4qFwMda5yvhWWmestbQu+sY=; b=x8rqwTcz5+puW+j7y/3kNqRQp9eOm6hUgvWcYUq8C7P2sSNZkXbQUqqHh96TaftaAP jALwKHpzfYO4rwdFINBc4QXSlz9P0BnYy/+iSB9pg+VtoLvRT37HOmL5L/Of+hkqpjxi z68W6zVm+jpUS/QtD6xq6umGn+8HRPfXvSw0gplIjflBSLOX5MvvEaXRSgpISFukfK6g g4NV58lP6IyO4wIvuHLrGOocr+b4gSurx+qSM3eXHqTHrdujnGByDdog+jAGAy19Zyfs nfF+ntb9FE40BPEfb0UqWRtKxmjBs8HK/PPP6mxEa3X/I9gmXNHRKAms8v5htqw+Olyz Jjcw== X-Gm-Message-State: AOAM532+oPSYcrRBnVs/dfwzCONSyHDpKo4A/MUVZDHn6ZSkYRmDBlPL WATHHgVhkLBp4duUnDBvcHszC6KjAjIMnA== X-Google-Smtp-Source: ABdhPJy0dMvA0BDpQkdlWJRaHvF0YvaN8IZi4aekeJfS/S9mwIxMaowxGbWkeRlXiUBKsXciONU5CQ== X-Received: by 2002:a05:6a00:2403:b0:4fd:e84a:4563 with SMTP id z3-20020a056a00240300b004fde84a4563mr7201469pfh.60.1654206552747; Thu, 02 Jun 2022 14:49:12 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 21/71] target/arm: Implement TPIDR2_EL0 Date: Thu, 2 Jun 2022 14:48:03 -0700 Message-Id: <20220602214853.496211-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This register is part of SME, but isn't closely related to the rest of the extension. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 24c5266f35..245d144fa1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -474,6 +474,7 @@ typedef struct CPUArchState { }; uint64_t tpidr_el[4]; }; + uint64_t tpidr2_el0; /* The secure banks of these registers don't map anywhere */ uint64_t tpidrurw_s; uint64_t tpidrprw_s; diff --git a/target/arm/helper.c b/target/arm/helper.c index 48534db0bd..204c5cf849 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6283,6 +6283,35 @@ static const ARMCPRegInfo zcr_reginfo[] = { .writefn = zcr_write, .raw_writefn = raw_write }, }; +#ifdef TARGET_AARCH64 +static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el == 0) { + uint64_t sctlr = arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnTP2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + return hcr & HCR_TGE ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_TRAP; + } + } + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENTP2)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo sme_reginfo[] = { + { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, + .access = PL0_RW, .accessfn = access_tpidr2, + .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, +}; +#endif /* TARGET_AARCH64 */ + void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env = &cpu->env; @@ -8444,6 +8473,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } #ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_sme, cpu)) { + define_arm_cp_regs(cpu, sme_reginfo); + } if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } From patchwork Thu Jun 2 21:48:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YTtmezVt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgHQ1gMLz9s0w for ; Fri, 3 Jun 2022 08:12:34 +1000 (AEST) Received: from localhost ([::1]:40182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt3Q-00071T-89 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:12:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37094) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgv-0004oL-DC for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:17 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:41921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgs-0008VG-Bw for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:17 -0400 Received: by mail-pf1-x42e.google.com with SMTP id p8so5795319pfh.8 for ; Thu, 02 Jun 2022 14:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6xMWEOVCvEJI1KC6zgVAv9+GA3g0PTUVPfSZbthulxo=; b=YTtmezVtqWJQ2Djjac7C5I6VjZ0ID+vIeMTDTZtn9Dcwo4m0VA84XvFvHPvXHxGXKb jq0v0gsprUokXueTdTA/+V7uXF1tzIwca43UuW0/lPcZaqTzHGKfTkJIP27qRTu+GSAp a66D0mUNTGsmPYoTqYyBIANyCPtcjySDpZ3dRPmF6jGRyi/m7zfISyor/OxUY40gvvmn GHAo+fbMVOJLfgZTlh6TPit9urdk5vx9Pc0/nsAST52STLnQl4Z9712vgk5d21adxUNI 1q1Wa9TIk1zuA3uI+knygzfbiz0A2WuIo+DlznKk+T6dqsrtyJGw5Y8a4989Y2gIFoGP 9d2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6xMWEOVCvEJI1KC6zgVAv9+GA3g0PTUVPfSZbthulxo=; b=AWvwaDXrqjzztdfeEUYENItBtwHySUQ06wi4SGQTe+m86Q4XOoFZ1tIQbBqENPKLEr qR4ie+RQjTlbmSqqm44ZCE8CT/xq81yvX2J7aYinxmxcfFu162ecpAgvz+BqL/K35bg2 iLFbuDhHWbIqc+5reMm1qrK1JfbeoTBbV3O1FPtIfIzjULxKHMHljWkQOmcBko4xBfEb V7h2ZO4THvlBaj+OfT827vzCRo8+eQrHdt98CHJ+iR/FS2O66Y8chrY5jXjSscjJ+/cX Her6GXl+FgDMZI9S2WoipirjSK2riai8tkF4p8KlP0TYEtCNHW+pD+PbDp6Sgsb+ZN/H GXfA== X-Gm-Message-State: AOAM531ujur9JSmm3yAlBtTr64ndMdaPnRzs54h4trR9Sfz9uIKbZNkp sqQYoUS+Q/He9ewTUya0hE1GXI2UVxa5hQ== X-Google-Smtp-Source: ABdhPJzOthaaoFeUXbDQiAbAEyIbVclyURqGtx5hMxY2HPnCnRbSkFdeFQKWti/E9LbIKCLcASDlSQ== X-Received: by 2002:a63:f407:0:b0:3fa:91cf:270 with SMTP id g7-20020a63f407000000b003fa91cf0270mr6085708pgi.428.1654206553484; Thu, 02 Jun 2022 14:49:13 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 22/71] target/arm: Add SMEEXC_EL to TB flags Date: Thu, 2 Jun 2022 14:48:04 -0700 Message-Id: <20220602214853.496211-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 1 + 4 files changed, 56 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 245d144fa1..31f812eda7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1134,6 +1134,7 @@ void aarch64_sync_64_to_32(CPUARMState *env); int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); +int sme_exception_el(CPUARMState *env, int cur_el); /** * sve_vqm1_for_el: @@ -3272,6 +3273,7 @@ FIELD(TBFLAG_A64, ATA, 15, 1) FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) +FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index f473a21ed4..a492e4217b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -42,6 +42,7 @@ typedef struct DisasContext { bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ int sve_excp_el; /* SVE exception EL or 0 if enabled */ + int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; diff --git a/target/arm/helper.c b/target/arm/helper.c index 204c5cf849..98de2c797f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6222,6 +6222,55 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } +/* + * Return the exception level to which exceptions should be taken for SME. + * C.f. the ARM pseudocode function CheckSMEAccess. + */ +int sme_exception_el(CPUARMState *env, int el) +{ +#ifndef CONFIG_USER_ONLY + if (el <= 1 && !el_is_in_host(env, el)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { + case 1: + if (el != 0) { + break; + } + /* fall through */ + case 0: + case 2: + return 1; + } + } + + if (el <= 2 && arm_is_el2_enabled(env)) { + /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ + if (env->cp15.hcr_el2 & HCR_E2H) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { + case 1: + if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { + break; + } + /* fall through */ + case 0: + case 2: + return 2; + } + } else { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { + return 2; + } + } + } + + /* CPTR_EL3. Since EZ is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return 3; + } +#endif + return 0; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -13719,6 +13768,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d438fb89e7..8bbd1b7f07 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14608,6 +14608,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); + dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); From patchwork Thu Jun 2 21:48:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638485 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YtN47zOi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgRb16Qfz9s0w for ; Fri, 3 Jun 2022 08:19:39 +1000 (AEST) Received: from localhost ([::1]:55818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtAG-0000lv-T3 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:19:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37092) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgv-0004oK-Au for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:17 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:37379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgt-000059-9T for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:17 -0400 Received: by mail-pf1-x42f.google.com with SMTP id bo5so5798726pfb.4 for ; Thu, 02 Jun 2022 14:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X6UniaTwDbuA5UKJMjAhDBE/HQvImNJGoq3x6BiPqWc=; b=YtN47zOi6GR70z+u5XEwOInZdwUc+wonASgIGlrm8JbWLaUltBuSuqeC0uXCsNGSLO lDYGcFJ1AseqmYJKz5xZnI47fzK/t4O0C2k5fRs7G9eV2Yml+Ldmpsizz7lP0KjqOghQ 5uC4oTm5o078blBIRBMyPM+TFumYQp1qirSHmH0yakAEzMaQMpQ6JhtkBLoYQR9rPvgS 6Xa65U7JraT1XE1thgyD62gR6PUgaGgwMXT3n/GeX7MovkEgceKC36HVJUtJmWhHlrfe 2MguEOC0BzWuAzxxp5U4/RiTrGyGfVdqvMbLy6wcFN41YT2qCNDVRBrtkrUHExGaK78k kSKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X6UniaTwDbuA5UKJMjAhDBE/HQvImNJGoq3x6BiPqWc=; b=aUcmCNT6qth78upMJxRMb7gIBzdGcKLO2PReykg33HR52W0e7AqXRWjzB9g1k4zIUL 9pcHDUmGDDWAAqIQA2/jI1+aCaaCZWx64moATdNooxPvMWELZxTtlePyaRPAQ4dJxs2V C4hbvRnmHVZB66seVTGwlbDtQsDqV7rXHjfEX56W3y3DPlpNY3IPBlSSHETYl5tTtbK4 cjNrTLJUelYcjF9XZPNrU7IGxHSuFshKniPYGiu/ng/KF026YY1OwXPIAUQMVcKti7Qm iGGkLN9TTXLHWNO/HfcTnaLDxnM0c/yh/5e3WF1kT59OW9b46Y/3HRPL4mGt6whgwSdQ Gb7w== X-Gm-Message-State: AOAM530qBzgoPDxQSdNDrh7p8tDGeoFC60g1H46Q4RArYlrr0c2bygH2 76WOGwBcaviskehNwyWnV80vKTPd3V/YNQ== X-Google-Smtp-Source: ABdhPJxqWDENGl0TuEJhBEZmCJ2D2CnuNJdeKz84AM7E3aUjKx68M/hIGurqWSaumdYutXR2UajOsQ== X-Received: by 2002:a63:ce58:0:b0:3fc:6966:b614 with SMTP id r24-20020a63ce58000000b003fc6966b614mr6095175pgi.234.1654206554509; Thu, 02 Jun 2022 14:49:14 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 23/71] target/arm: Add syn_smetrap Date: Thu, 2 Jun 2022 14:48:05 -0700 Message-Id: <20220602214853.496211-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be used for raising various traps for SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/syndrome.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 0cb26dde7d..4792df0f0f 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -48,6 +48,7 @@ enum arm_exception_class { EC_AA64_SMC = 0x17, EC_SYSTEMREGISTERTRAP = 0x18, EC_SVEACCESSTRAP = 0x19, + EC_SMETRAP = 0x1d, EC_INSNABORT = 0x20, EC_INSNABORT_SAME_EL = 0x21, EC_PCALIGNMENT = 0x22, @@ -68,6 +69,13 @@ enum arm_exception_class { EC_AA64_BKPT = 0x3c, }; +typedef enum { + SME_ET_AccessTrap, + SME_ET_Streaming, + SME_ET_NotStreaming, + SME_ET_InactiveZA, +} SMEExceptionType; + #define ARM_EL_EC_SHIFT 26 #define ARM_EL_IL_SHIFT 25 #define ARM_EL_ISV_SHIFT 24 @@ -206,6 +214,11 @@ static inline uint32_t syn_sve_access_trap(void) return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; } +static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) +{ + return (EC_SMETRAP << ARM_EL_EC_SHIFT) | (!is_16bit * ARM_EL_IL) | etype; +} + static inline uint32_t syn_pactrap(void) { return EC_PACTRAP << ARM_EL_EC_SHIFT; From patchwork Thu Jun 2 21:48:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=MO/d19AC; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgN9029Cz9s0w for ; Fri, 3 Jun 2022 08:16:40 +1000 (AEST) Received: from localhost ([::1]:48842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt7P-0004WM-2s for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:16:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgw-0004qC-NO for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:43556) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgu-0000AC-Qa for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: by mail-pg1-x52f.google.com with SMTP id s68so5789327pgs.10 for ; Thu, 02 Jun 2022 14:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZXeHgaKxYRbNnut8rVp8kMGvsswCzp2UB1e+rQJPl1o=; b=MO/d19ACxCCoy6qsYYB+ai06R5Z1kKfPygOWzoX0b4fwX+iqTgUVSu9aCfolQkiDQ2 XWqxHKAYAum7J1SaQ/WjsgxLSUZfxYkhv+ONWGK+5FhdnTT4HRxxHkbr1Q7z6YREcOcd Tz1UQ5w/QWklzKDmbf+lJIimzLQTbvAj5KJW6gcqiWw9hKZx17QEWtTNaaHW5BkFpPP2 m53lbojSk/9TxRXIiQ5GaVDfOxUdGr1X10NA3y28ch8TlRnRuwkp9zxzZypV0UgjXfRu qt3HmWmi7or1h74gGABbkvSthE5B6bee84DnZCxCuhzxvGGIhQk9wSch+bSJu/iXEQte Nydg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZXeHgaKxYRbNnut8rVp8kMGvsswCzp2UB1e+rQJPl1o=; b=e3+q3Poxob2FrYmwbHSTq4EHfeFGKkQIoMOkH85/yEQcO9a6jRrArhXWYCe+h3SH9V 9nRzdyGzxy8wDsU2Wg5TZzkVWGI4Qca3CD6gZz4DaZ56slPkRc+spml3QJXVcGT6FMdk 7h/A5hiTbapL54r1yA4CPhuYj0Wsuk+HforOkD1El+SrxL1gB4+5M35solicDPJyHfMy U50ZAYOmcJpPvcZM5tS46sCPRRqwPLPydaQrOZg9Tv4mzRfqcMMp0YOTs1IQ6fPfXptO Ue6mSvKSx5VFLoTxfcG40Um0zBe+XQkh+PHstlRCTtcLaJAb1o+gPibw64ydrGyk+BSn ioIw== X-Gm-Message-State: AOAM531nQWr3FJMJhe81f0IYcdP4x1lf/96C4XsPutFnmErTK8Q/rQx4 muqRGfJj/QBwrgPQKn2kb9Vx1XIYTGy2vg== X-Google-Smtp-Source: ABdhPJxhlLa9P4+H9bKJ3aAfqnBks//dBiug8TiH5vdMQRHZbsfatR6Qk3BGhMeEylBffQazkVQARg== X-Received: by 2002:a05:6a00:170b:b0:51b:cf4b:9187 with SMTP id h11-20020a056a00170b00b0051bcf4b9187mr4038553pfc.15.1654206555248; Thu, 02 Jun 2022 14:49:15 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 24/71] target/arm: Add ARM_CP_SME Date: Thu, 2 Jun 2022 14:48:06 -0700 Message-Id: <20220602214853.496211-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be used for controlling access to SME cpregs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 5 +++++ target/arm/translate-a64.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index d9b678c2f1..d30758ee71 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -113,6 +113,11 @@ enum { ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16, ARM_CP_EL3_NO_EL2_KEEP = 1 << 17, ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18, + /* + * Flag: Access check for this sysreg is constrained by the + * ARM pseudocode function CheckSMEAccess(). + */ + ARM_CP_SME = 1 << 19, }; /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8bbd1b7f07..f51d80d816 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1186,6 +1186,22 @@ bool sve_access_check(DisasContext *s) return fp_access_check(s); } +/* + * Check that SME access is enabled, raise an exception if not. + * Note that this function corresponds to CheckSMEAccess and is + * only used directly for cpregs. + */ +static bool sme_access_check(DisasContext *s) +{ + if (s->sme_excp_el) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_AccessTrap, false), + s->sme_excp_el); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the @@ -1958,6 +1974,8 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; + } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { + return; } if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { From patchwork Thu Jun 2 21:48:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Rb/EeB/E; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgVV1hVDz9s0w for ; Fri, 3 Jun 2022 08:22:10 +1000 (AEST) Received: from localhost ([::1]:36362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtCi-0006ol-9I for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:22:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgw-0004qS-Qp for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:44776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgv-0008Tw-1v for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:18 -0400 Received: by mail-pl1-x631.google.com with SMTP id h1so5510463plf.11 for ; Thu, 02 Jun 2022 14:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0kEodHx06fEclTgSZQr1FM7FKwrQ5Md0/7IEVtNiVsE=; b=Rb/EeB/E2KaLKNbMwrl8y/jsEwm0gP3vyzOylYAyRD9YcCw1jKxvAbg0c58eGuOJE1 1CaIXgnMmCJyx84QQjlM/EWL9mJhz+JW730sQl6au1XJ5uKvrruOBtq/fX3BaCUn4okI FffM5mzDBx1qYsrqk/u6IV13Jw05Qvao9+ownGb9iMoGM1S3Ij0nL9izjYkXtwWYklS9 uTCa/xqtrlAP0sOPOO6e8LWt/KzP7lM1Prj4ppoV2PZaX61bSCJjRi4JAjko4EvEykLe TAC4RLvL89Ol8W2yxFKaEPa9vh/Aufz8icERDa5uzN2Dcu/9gapDI+Ejr7CADRR8gzCg k6ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0kEodHx06fEclTgSZQr1FM7FKwrQ5Md0/7IEVtNiVsE=; b=c6pwjWDIDZobLlAWMLA0vZXdNbLlwHs/ilWtw9BMHBCiICCH0uZZS0Rz5Php9oZ9Af QFt9BTzrFVFog7QluHYDNMRm5z7gRLEthRYsdpI96Y1dzjth3IRvy20+92R6AqMmZoGM ZK9iZO4MomFuOZx6C1iLeWHVybsvvZe6zr210zBrhbcOQqf91UaFzQoMRn6r5FIsUA7+ VZ8LVibPxKdNoaMfU+L9IzjBf7akv7rqDiyMI6RFCUDobNrmHZJ2hZYz01bPw7Mpeh0r Wuw4uhr9Wv/d2Z4Pka5b9ru3xgfHbU36uUCRheQL0SIsBgY12VejOYuVdjv1RRhs/Epa UWCg== X-Gm-Message-State: AOAM530/e6Hnw8yF9VDsffy0JZmoyaepCZPl3XO1Y13gCSxxLRs/hPmE AJI2IULkyeaXNVoCxb4te2Wdoz2TSDDmRA== X-Google-Smtp-Source: ABdhPJzCixKDV79G3JzZgkWZxDdNMS6D6nZu0M+DifgMNZqHqIPH1y9yhREH14W/WkMvHPM3uRwr1g== X-Received: by 2002:a17:90b:1e46:b0:1e6:826e:73ea with SMTP id pi6-20020a17090b1e4600b001e6826e73eamr6611583pjb.68.1654206556182; Thu, 02 Jun 2022 14:49:16 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 25/71] target/arm: Add SVCR Date: Thu, 2 Jun 2022 14:48:07 -0700 Message-Id: <20220602214853.496211-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This cpreg is used to access two new bits of PSTATE that are not visible via any other mechanism. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31f812eda7..31b764556c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -258,6 +258,7 @@ typedef struct CPUArchState { * nRW (also known as M[4]) is kept, inverted, in env->aarch64 * DAIF (exception masks) are kept in env->daif * BTYPE is kept in env->btype + * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; @@ -292,6 +293,7 @@ typedef struct CPUArchState { uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ + uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ uint64_t elr_el[4]; /* AArch64 exception link regs */ uint64_t sp_el[4]; /* AArch64 banked stack pointers */ @@ -1428,6 +1430,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define PSTATE_MODE_EL1t 4 #define PSTATE_MODE_EL0t 0 +/* PSTATE bits that are accessed via SVCR and not stored in SPRS_ELx. */ +FIELD(SVCR, SM, 0, 1) +FIELD(SVCR, ZA, 1, 1) + /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 98de2c797f..366420385a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6353,11 +6353,24 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK; + /* TODO: Side effects. */ + env->svcr = value; +} + static const ARMCPRegInfo sme_reginfo[] = { { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, .access = PL0_RW, .accessfn = access_tpidr2, .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, + { .name = "SVCR", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, + .access = PL0_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, svcr), + .writefn = svcr_write, .raw_writefn = raw_write }, }; #endif /* TARGET_AARCH64 */ From patchwork Thu Jun 2 21:48:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=lwPV3v2d; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgWs0Fy3z9s0w for ; Fri, 3 Jun 2022 08:23:21 +1000 (AEST) Received: from localhost ([::1]:39560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtDr-0000VO-3k for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh9-000584-M0 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:31 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:41489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgw-00007w-A9 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:31 -0400 Received: by mail-pg1-x530.google.com with SMTP id e66so5779812pgc.8 for ; Thu, 02 Jun 2022 14:49:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jxcguvnsju5QCxGIYXvo3WToRmgWIw+so5bs8Lrowps=; b=lwPV3v2dyW7D8viKYg8e4ChKZoCs9REUmOpvuc/h0WavZ9CJOqPMjWlbrR4A2WlGAo w71Urz5GyOwzvkRR66PycDqYjE2JAdIc6A9fYnHNSYyEdLbLtMFJmmtnnfknCmzIpIOj fiWs34M9Z7tVYrQxuvtps9Q/OiM0C5o82cH0wTZEmmYNuJW+T5a5XU1MsGemAmebeCWv asQsQgMzOM3KofYey+KpbvGVLqZYIlbXmWFWxIs4ENDm/igvjQYDX4h8YpF+kz0n4kdN +VGFyKa1rNRkHa1aQPUr84JYvitIqMCOeZuafIvYpzK51BMpOQHChkUNxmbziDz5wvqP VrAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jxcguvnsju5QCxGIYXvo3WToRmgWIw+so5bs8Lrowps=; b=SJJ9NZKZOPM3xharybcYbcB/e63OHe3Y9ECR49aZzkdKByBafpXcEPQejH8XuOgWSQ 5UbFwTx8PWM3UC9BPGqbXWKr6pmF2IfVPLWbEBTXtlKpwzjaXW9YlJ0tGMsnUHrmQkXu 0ji+hljm31JJxNwtAqm5YgPb5G8LKbnwpkucWuF9f8G+d1l/5+Ic7g/JbrmcMt3N5S7T Fw+n8Nrsgmu91P+yjjsKF27n8N7UWhVC/qhABCj3Etk7eNBZ/sKH6lEnHRN1+XphT7AN 7n/bCXGdGYKNOgUQEHm2uJLj4DZpd0nmBHGSDXc0Du7vhHKgCZnEeSFcNAfM87ZT/0iU YNwQ== X-Gm-Message-State: AOAM533ZLQDdf21XCrGSWZo+xSmwCMRohnbCT87dEjovevxpmBmUXTjq +fpQ84BRs4SCxgKRHE8EnJcJQhwdUTR3mw== X-Google-Smtp-Source: ABdhPJx8VPgKPfigfMJ66HlPvbQommXRDkCVXyJKMXrKEDErm04c70LYKF8tZDLbFE7uKT1tpuv4lg== X-Received: by 2002:a62:d10e:0:b0:51b:d711:b189 with SMTP id z14-20020a62d10e000000b0051bd711b189mr2908885pfg.40.1654206557103; Thu, 02 Jun 2022 14:49:17 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 26/71] target/arm: Add SMCR_ELx Date: Thu, 2 Jun 2022 14:48:08 -0700 Message-Id: <20220602214853.496211-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These cpregs control the streaming vector length and whether the full a64 instruction set is allowed while in streaming mode. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++-- target/arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 31b764556c..1ae1b7122b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -669,8 +669,8 @@ typedef struct CPUArchState { float_status standard_fp_status; float_status standard_fp_status_f16; - /* ZCR_EL[1-3] */ - uint64_t zcr_el[4]; + uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ + uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ } vfp; uint64_t exclusive_addr; uint64_t exclusive_val; @@ -1434,6 +1434,10 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) FIELD(SVCR, SM, 0, 1) FIELD(SVCR, ZA, 1, 1) +/* Fields for SMCR_ELx. */ +FIELD(SMCR, LEN, 0, 4) +FIELD(SMCR, FA64, 31, 1) + /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 366420385a..4149570b95 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5883,6 +5883,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) */ { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), + "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, @@ -6361,6 +6363,30 @@ static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->svcr = value; } +static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int cur_el = arm_current_el(env); + int old_len = sve_vqm1_for_el(env, cur_el); + int new_len; + + QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); + value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; + raw_write(env, ri, value); + + /* + * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage + * when SVL is widened (old values kept, or zeros). Choose to keep the + * current values for simplicity. But for QEMU internals, we must still + * apply the narrower SVL to the Zregs and Pregs -- see the comment + * above aarch64_sve_narrow_vq. + */ + new_len = sve_vqm1_for_el(env, cur_el); + if (new_len < old_len) { + aarch64_sve_narrow_vq(env, new_len + 1); + } +} + static const ARMCPRegInfo sme_reginfo[] = { { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, @@ -6371,6 +6397,21 @@ static const ARMCPRegInfo sme_reginfo[] = { .access = PL0_RW, .type = ARM_CP_SME, .fieldoffset = offsetof(CPUARMState, svcr), .writefn = svcr_write, .raw_writefn = raw_write }, + { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, + .access = PL1_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), + .writefn = smcr_write, .raw_writefn = raw_write }, + { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6, + .access = PL2_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]), + .writefn = smcr_write, .raw_writefn = raw_write }, + { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6, + .access = PL3_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), + .writefn = smcr_write, .raw_writefn = raw_write }, }; #endif /* TARGET_AARCH64 */ From patchwork Thu Jun 2 21:48:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=luK8tQFY; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgbK3N53z9s0w for ; Fri, 3 Jun 2022 08:26:19 +1000 (AEST) Received: from localhost ([::1]:46006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtGi-0004ok-Jt for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:26:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgy-0004sE-Q7 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:20 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:44685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgw-0008Vf-Vp for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:20 -0400 Received: by mail-pg1-x536.google.com with SMTP id u4so2827460pgk.11 for ; Thu, 02 Jun 2022 14:49:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oKx3qB6wck18vUMVl01RfDqyuqu9f6LE7LHxyySYjNc=; b=luK8tQFYY7IDXAysCP92Tgd5Afu+hV5r2kFhE5U/Z0Ln5Ek7g9O5oTjugRtsYPVFML BfqqX+i3oBakFEdpZxZ7vU0vk57wiKewk01l/BHBjqWdC8sL/+2kJL3KRO4HxcfSSkd2 EshIuzT+wE9FbyiXPtKR2buTmH/3oY+mfEVZ/xyOkW6sLMKwvd5SRL3xoGIbM1MmBQa6 iQJEFhk03aSF9vPaaC50PIjP2tO/WJG/+UNEqktDapK2TZOjlt5sJ8srLmNAgImidNuY QQBIqCSo63o9AeY+Pq3dwOx77dE1FVA88yOaR/h/DsUbZfOeENqdjaps2rhrl/tIJo0K qCHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oKx3qB6wck18vUMVl01RfDqyuqu9f6LE7LHxyySYjNc=; b=oWGnvY8Mz3lx6SFlcBjkgJZ1z8yOLNXi+ADQqkyV71sZNSqTqV0h1oKj1VGT0sh1NM z7Hiydu51moorxH567HZ5dZE+Wq89N6LjF91dT0pUez1ZZMirofxZAs8kZzik4wCQHkD YVoXeK1KartGiCcf+q3xx6RvzmvCUO94y5ZYur+MpixQ4yCOMDp44tStsUqAvDHIyC9y 9IzY/ShSWMwOUAunjf441PxdtE/lXWKPiiKEryIm/7GiX0qFTf//vsKjdAsJzstIZCyT 1s8/WJhrdWrkKl6Hf+v0ZSmgdteYUneDdGcvCCKgYyu7dKGagVc+Jad+3W+Ul7mshRju PvDA== X-Gm-Message-State: AOAM531KAMGsIIJg8ciiTFtl6MsNIUNZEe2neqKWuAwHLrgtsHz3M/uo ddRt3a7Wp8A0fc7zIehH2snvZ/oUGc+3sQ== X-Google-Smtp-Source: ABdhPJxMzH7qu39P3gmOvpbkrmdWnA/kkkOK+F6RxMBg4vC8NC/gRLA8PlGvDJUeqU30v6W0QQJ3Fg== X-Received: by 2002:a05:6a02:204:b0:3fc:1d96:db11 with SMTP id bh4-20020a056a02020400b003fc1d96db11mr6091167pgb.168.1654206558046; Thu, 02 Jun 2022 14:49:18 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 27/71] target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2 Date: Thu, 2 Jun 2022 14:48:09 -0700 Message-Id: <20220602214853.496211-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement the streaming mode identification register, and the two streaming priority registers. For QEMU, they are all RES0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4149570b95..f852fd7644 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6355,6 +6355,18 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -6412,6 +6424,27 @@ static const ARMCPRegInfo sme_reginfo[] = { .access = PL3_RW, .type = ARM_CP_SME, .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), .writefn = smcr_write, .raw_writefn = raw_write }, + { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6, + .access = PL1_RW, .accessfn = access_aa64_tid1, + /* + * IMPLEMENTOR = 0 (software) + * REVISION = 0 (implementation defined) + * SMPS = 0 (no streaming execution priority in QEMU) + * AFFINITY = 0 (streaming sve mode not shared with other PEs) + */ + .type = ARM_CP_CONST, .resetvalue = 0, }, + /* + * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. + */ + { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, + .access = PL1_RW, .accessfn = access_esm, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, + .access = PL2_RW, .accessfn = access_esm, + .type = ARM_CP_CONST, .resetvalue = 0 }, }; #endif /* TARGET_AARCH64 */ From patchwork Thu Jun 2 21:48:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638488 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=JVUkaiVd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgSh43Xjz9s0w for ; Fri, 3 Jun 2022 08:20:36 +1000 (AEST) Received: from localhost ([::1]:58916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtBC-0002st-Ar for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:20:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsgz-0004tu-Q5 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:21 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:37473) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgx-00006q-Jw for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:21 -0400 Received: by mail-pg1-x534.google.com with SMTP id i185so5804360pge.4 for ; Thu, 02 Jun 2022 14:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQ6mvuDTnZBD5iD1SP6A6OjgNUDJxGksfDsQZ9X7HOg=; b=JVUkaiVdrkR7r5S/WRFOT/bKqM8nlWXClR4wnbxL/oWTC7i+t2c1tSicz5Bqu8RFSx V9FofpmM5WA4QuuTfDz25bVKFkCE4ISHPSdETnhLEinXlGqn1KSr5VGfMgvxdj8EVHdy FtL49w+gotM6HUXYZhAENEfi7569PURtPjp8+GDC0+GwQIpVXX04vH8IZX8arJXKHpuA dyJGmnJLi0VbZ2jRFlQKOBiNHoHchTuhoB8qtBK2ScqDyyGDpdwsT+Pl2pRw+uKdDPo9 I9OcSx1QzQP+FC/D01bpVd+oPVXG0IkKVuUeCA37pKRiUP0gaL0QPQGpOlXSEL0rme5x Z06w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UQ6mvuDTnZBD5iD1SP6A6OjgNUDJxGksfDsQZ9X7HOg=; b=hmGReYVs8xIMZYc03lQkcZcMi4/D4/vmhk4eAzArezYDJn/mUJt/dM/ngmRy/NUGjJ 4lJZkwncQTe5E6oNIULc7ezahp0ltgqBtsjfQ5f2y3Kn8/MZ1uIIZq4SDB4tEwyN+2Jq s5aSqV/Ejm/n+MVFMp5hlwTTjG4f8Jx3QaGnpudOzWDmUVSjhE3jVnpzUPxhHt+UbCjU USMp5QjD4EC458qR2a6WD2H7FOBAb+8IO7c0cGiKJCUhI1BOeBIjz67X9/eH9g7fKGS/ yLaQCKu3i7I0H5CQFZZ1WL90zi/zfecj6rQXXlRsnYlX0i4Ihqw+0uqo3GZjSfXL1p0P Xk/Q== X-Gm-Message-State: AOAM530JlfeH8WoGLsPu0hURdtwkDpRTcNjzApLtzTXJNSGC0/VHD54O Phb4pF9VK6HtoEldYgEWTHVnHyFpLm8zjg== X-Google-Smtp-Source: ABdhPJxLNOMu3b5JvWBp3OsTm19iGaihRhBg25SsUA23GN8AQX5uVyEohnygDVbHcNfyJGF4PC2owQ== X-Received: by 2002:a05:6a00:e8e:b0:518:287c:ce82 with SMTP id bo14-20020a056a000e8e00b00518287cce82mr7038046pfb.4.1654206558854; Thu, 02 Jun 2022 14:49:18 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 28/71] target/arm: Add PSTATE.{SM,ZA} to TB flags Date: Thu, 2 Jun 2022 14:48:10 -0700 Message-Id: <20220602214853.496211-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These are required to determine if various insns are allowed to issue. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/translate.h | 4 ++++ target/arm/helper.c | 4 ++++ target/arm/translate-a64.c | 2 ++ 4 files changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1ae1b7122b..9bd8058afe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3284,6 +3284,8 @@ FIELD(TBFLAG_A64, TCMA, 16, 2) FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) +FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) +FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index a492e4217b..fbd6713572 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -101,6 +101,10 @@ typedef struct DisasContext { bool align_mem; /* True if PSTATE.IL is set */ bool pstate_il; + /* True if PSTATE.SM is set. */ + bool pstate_sm; + /* True if PSTATE.ZA is set. */ + bool pstate_za; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index f852fd7644..3edecb56b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13857,6 +13857,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + DP_TBFLAG_A64(flags, PSTATE_SM, 1); + } + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } sctlr = regime_sctlr(env, stage1); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f51d80d816..fdc035ad9a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14635,6 +14635,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ata = EX_TBFLAG_A64(tb_flags, ATA); dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); + dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); + dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; From patchwork Thu Jun 2 21:48:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638492 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=BVtm5eeG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgXy44WZz9s0w for ; Fri, 3 Jun 2022 08:24:18 +1000 (AEST) Received: from localhost ([::1]:41552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtEm-0001p1-Jx for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:24:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh2-0004wq-Nf for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:24 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:50698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgz-0000Cg-4x for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:23 -0400 Received: by mail-pj1-x1035.google.com with SMTP id e24so6052240pjt.0 for ; Thu, 02 Jun 2022 14:49:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uyp8xWq7ZkrFhvOvNlw2bvzAu/rqhqAIEZWhdZkOs7M=; b=BVtm5eeGApIAbjg/i8dZ9jQ452nDcr5Z15h3U5/iYtH3VsT7eGJqv4xKaKeAi/KnPD vGij/PFScAWjkaVpl6HAEnjmJkvbP2PWPfrTCitHOYgMJ+9QIj7KDuH2ZLeMYoyNZVE/ wUGM3JBIZrADkcCmJ2exRCPY+QtTYn/BzFM7EC5VVv1PKdxUPtHrOM3YuuxOYydwyX0t /4Dda5lZd9LLk/76iI0ypyGq4nQ4B8pGtmny25OyQVuSEdkvtAgNQQcZWqoAP/W8TfjD K/YBgo3I0IeuDHO32QUpNCJvKJhkhat3bJwIKWWAemLR0bEJUOCxiar8KiTKCP1g27Vp j1dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uyp8xWq7ZkrFhvOvNlw2bvzAu/rqhqAIEZWhdZkOs7M=; b=SRy9iadmThsAYPXuCoKF9patc81VhFEVaOb2WKkJfIfHk8q3O+e3Y6LnZR3UTHJyjG 1zrzo4yzaes0dAxDLnbwd2I8xYKCR3hbqeyFFq5XbdWABlgEPek2eI+vvL/EwBbCWAma l05QHBMU5Ap7I8Aj2H28CYSLyUgaD7pNRzSBlU70LxctlE4LhVJNfA3y84hQNC+nLSDn zr48uhev1zvb6C8icT74/3IdxGF0hv2dVZTT46RnzaTNFKzZ6hWstU/n6BLY8lK517Ot rrpDfGMv9rOG+V9eTQCKJ6E7IZQareo6L7x1eBIQNOiV9lbE1lNKIFaiFlieabwp3n7k 8lWw== X-Gm-Message-State: AOAM531ySGMiewhGQKmXBsLJa69UpnhV5u0GeF4vPjjuASZYl2w5+QEX tVG3jWgVZHTtlug0as7mPZC+0rQVY11dxA== X-Google-Smtp-Source: ABdhPJxSWdPSdjoAn1c08tVR+tQ67hy7+71s/z1olt9v50ygkpla4WE6h2PQE9BX2kx2lGakPJWlVA== X-Received: by 2002:a17:902:8602:b0:162:eaf:3630 with SMTP id f2-20020a170902860200b001620eaf3630mr7221759plo.118.1654206559784; Thu, 02 Jun 2022 14:49:19 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 29/71] target/arm: Add the SME ZA storage to CPUARMState Date: Thu, 2 Jun 2022 14:48:11 -0700 Message-Id: <20220602214853.496211-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++++ target/arm/machine.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9bd8058afe..1bc7de1da1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -694,6 +694,14 @@ typedef struct CPUArchState { } keys; uint64_t scxtnum_el[4]; + + /* + * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, + * as we do with vfp.zregs[]. Because this is so large, keep this toward + * the end of the reset area, to keep the offsets into the rest of the + * structure smaller. + */ + ARMVectorReg zarray[ARM_MAX_VQ * 16]; #endif #if defined(CONFIG_USER_ONLY) diff --git a/target/arm/machine.c b/target/arm/machine.c index 285e387d2c..d9dff6576d 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -167,6 +167,39 @@ static const VMStateDescription vmstate_sve = { VMSTATE_END_OF_LIST() } }; + +static const VMStateDescription vmstate_za_row = { + .name = "cpu/sme/za_row", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), + VMSTATE_END_OF_LIST() + } +}; + +static bool za_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + + /* + * When ZA storage is disabled, its contents are discarded. + * It will be zeroed when ZA storage is re-enabled. + */ + return FIELD_EX64(cpu->env.svcr, SVCR, ZA); +} + +static const VMStateDescription vmstate_za = { + .name = "cpu/sme", + .version_id = 1, + .minimum_version_id = 1, + .needed = za_needed, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0, + vmstate_za_row, ARMVectorReg), + VMSTATE_END_OF_LIST() + } +}; #endif /* AARCH64 */ static bool serror_needed(void *opaque) @@ -887,6 +920,9 @@ const VMStateDescription vmstate_arm_cpu = { #endif &vmstate_serror, &vmstate_irq_line_state, +#ifdef TARGET_AARCH64 + &vmstate_za, +#endif NULL } }; From patchwork Thu Jun 2 21:48:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=w+WMTH86; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDg9s5Mhzz9s0w for ; Fri, 3 Jun 2022 08:07:44 +1000 (AEST) Received: from localhost ([::1]:53432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwsyj-0005Ed-EZ for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:07:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh2-0004wp-Nw for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:24 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:36688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsgz-0000D8-VL for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:24 -0400 Received: by mail-pg1-x52f.google.com with SMTP id y187so5807471pgd.3 for ; Thu, 02 Jun 2022 14:49:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f4EFi0X8pC0ZHJX0LpV/2RPhRHjmGcoeXQX/e/CTo/k=; b=w+WMTH86vRXjCFIru5pdgadHYsK3I/Qzd5WBxZy70NVn4EPMuYJQqcWiyvxfP5TrWJ uE0nCwUfowzEk9j0ujnzWEnq1t+E/9ka+MWzvKHdEiNblYw7wIH6NzCD6QhBZZ8C5gGC Y3E6k/Nc8bP5gwKzrkXgo0SZy8fsWsOhPcYS3t2Ppwc9lWGRH5kTjpWcumTX4QV2J7iq APPMDG2SLkUeTW+lLTsmZTQbUGIgb61SlbjMuGpqMeMokcV47/l9U7INul/TdOovwdMM YJnI/v/AR/4T4Wh9uMjx0qdZU1JELe/rRkVHXymB7FXKylooLA8sH79+RZntkwUluFAt zkXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f4EFi0X8pC0ZHJX0LpV/2RPhRHjmGcoeXQX/e/CTo/k=; b=dm3ikUHqq0bVD576yM3r5NBc4D8A1PrD0GfSubTrhjUR8/sqWKw71Pc6Mjw1+5gZyQ pJ9xIzq3bs9JIyjiI3e3hxTOUqHkYvy8vhL/GpiSoUPN5zQPFyatcr5LPRZ67h8Y1Bso embpjftFPThDVP1MFsOJQ/VgGVsySKJec9sDH+rRDzVPQfv9mVnVZNmQErZPnurC0+vx uIxNTImN88xtz10QeOpxB1PPkGpB56ZqkO0kTJnedcrYQbWWGEITuzi9W5NHLztvj2tH TRLOuowgfC0lWlJfXMt3CexVXKtlGpQIU6y05VNGMKH7XQ8gKU+QyvLAxKjLBq2qEgHU S7NA== X-Gm-Message-State: AOAM5319Gz+xJc+amjA0hLxpNeqF97fpdGcObab2l1h06Fk34UtWMtsS c3AquJz6p/M5NokPhZdmitHrULRR9hejZw== X-Google-Smtp-Source: ABdhPJytYulq18Bf0EbQO7dZqJgfo1qVwPoHgRgCJqJ83CB6LuUkvrjRNNs6VAO26ADjkOcBxVARoA== X-Received: by 2002:a05:6a00:2289:b0:51b:d392:1f46 with SMTP id f9-20020a056a00228900b0051bd3921f46mr3391260pfe.20.1654206560683; Thu, 02 Jun 2022 14:49:20 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 30/71] target/arm: Implement SMSTART, SMSTOP Date: Thu, 2 Jun 2022 14:48:12 -0700 Message-Id: <20220602214853.496211-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These two instructions are aliases of MSR (immediate). Use the two helpers to properly implement svcr_write. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper-sme.h | 21 +++++++++++++ target/arm/helper.h | 1 + target/arm/helper.c | 6 ++-- target/arm/sme_helper.c | 60 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 24 +++++++++++++++ target/arm/meson.build | 1 + 7 files changed, 111 insertions(+), 3 deletions(-) create mode 100644 target/arm/helper-sme.h create mode 100644 target/arm/sme_helper.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1bc7de1da1..b65e370b70 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1106,6 +1106,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); void aarch64_add_sve_properties(Object *obj); void aarch64_add_pauth_properties(Object *obj); +void arm_reset_sve_state(CPUARMState *env); /* * SVE registers are encoded in KVM's memory in an endianness-invariant format. diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h new file mode 100644 index 0000000000..3bd48c235f --- /dev/null +++ b/target/arm/helper-sme.h @@ -0,0 +1,21 @@ +/* + * AArch64 SME specific helper definitions + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1334e0c42..5bca7255f1 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1020,6 +1020,7 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" +#include "helper-sme.h" #endif #include "helper-mve.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 3edecb56b6..5328676deb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6370,9 +6370,9 @@ static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK; - /* TODO: Side effects. */ - env->svcr = value; + helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); + helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); + arm_rebuild_hflags(env); } static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c new file mode 100644 index 0000000000..c34d1b2e6b --- /dev/null +++ b/target/arm/sme_helper.c @@ -0,0 +1,60 @@ +/* + * ARM SME Operations + * + * Copyright (c) 2022 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/helper-proto.h" + +/* ResetSVEState */ +void arm_reset_sve_state(CPUARMState *env) +{ + memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); + memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); + vfp_set_fpcr(env, 0x0800009f); +} + +void helper_set_pstate_sm(CPUARMState *env, uint32_t i) +{ + if (i == FIELD_EX64(env->svcr, SVCR, SM)) { + return; + } + env->svcr ^= R_SVCR_SM_MASK; + arm_reset_sve_state(env); +} + +void helper_set_pstate_za(CPUARMState *env, uint32_t i) +{ + if (i == FIELD_EX64(env->svcr, SVCR, ZA)) { + return; + } + env->svcr ^= R_SVCR_ZA_MASK; + + /* + * ResetSMEState. + * + * SetPSTATE_ZA zeros on enable and disable. It would appear that we + * can zero this only on enable: while disabled, the storage is + * inaccessible and the value does not matter. We're not saving the + * storage in vmstate when disabled either. + */ + if (i) { + memset(env->zarray, 0, sizeof(env->zarray)); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fdc035ad9a..40f2e53983 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1761,6 +1761,30 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, } break; + case 0x1b: /* SVCR* */ + if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { + goto do_unallocated; + } + if (sme_access_check(s)) { + bool i = crm & 1; + bool changed = false; + + if ((crm & 2) && i != s->pstate_sm) { + gen_helper_set_pstate_sm(cpu_env, tcg_constant_i32(i)); + changed = true; + } + if ((crm & 4) && i != s->pstate_za) { + gen_helper_set_pstate_za(cpu_env, tcg_constant_i32(i)); + changed = true; + } + if (changed) { + gen_rebuild_hflags(s); + } else { + s->base.is_jmp = DISAS_NEXT; + } + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/target/arm/meson.build b/target/arm/meson.build index 50f152214a..02c91f72bb 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -47,6 +47,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'mte_helper.c', 'pauth_helper.c', 'sve_helper.c', + 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', )) From patchwork Thu Jun 2 21:48:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=WHTZ1Ajz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgfK0kLCz9s0w for ; Fri, 3 Jun 2022 08:28:57 +1000 (AEST) Received: from localhost ([::1]:55656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtJH-0002yo-5j for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:28:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh3-0004xL-4l for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:25 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:52095) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh0-0000DL-Rp for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:24 -0400 Received: by mail-pj1-x102b.google.com with SMTP id cx11so6028962pjb.1 for ; Thu, 02 Jun 2022 14:49:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iCOG6DsXO7r1GwfN6wKfqvV2SzATr8uc1yKAbhFIADk=; b=WHTZ1AjzKSx6vBe8d+WassEtCMBWyrCv8R6MB+aGns5aLIh5dmWbrYAqAlEBvrNUf2 fZrLPelzQtSjTOWqIP9zHrBzt4d9bDw5tVqB+kGZ//G1jWb0PebijjU0rbE4CcqndRVK Jz1U3/zO9I2nRWkLlJFUfgYdYg1GhxPiYLK0kQJROvJjh0WU7cXcfKHBECrtUBA/vQFv 6gsFuzPg8uJN6Zi4InFl3v21YNIZpwCusaO90FjClSqlYvupr6vC94a4zdL5ioHTeo/b ZxUzDwnwJm3BTu/iF1xEOMALbgLkz+fQAU+9RQeSpYMGvS1nEt66xSCxlzv6bKaQDqVD 5U+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iCOG6DsXO7r1GwfN6wKfqvV2SzATr8uc1yKAbhFIADk=; b=Fu2W4BSeSuQc+8xwCWjJEvDWZEJYM84Ut3t9nQsIiFT68b6hUHFzozY4kad06/XrnJ ToCdDokHVQA88uMO5MQaqxNtbyYY9jZ4C714cp9uCR8iXS6IZTjFfBedwwk2zhvaPRYs aggwZHQ758ICV0Mn+MZfJWZt57uc+jxwLhPz8B6fEFLqfx/yohkmuIkIsbcOvR2Y6cet 8lggkzAmX0P6EfL+bZ1cwydhROFSZT31W47mDG1rQ8HFOhX7j7VzTYtxusDNFGVQf7df Jn2/z4vumRam5YrP8+9jz9F9aMxUHONdC7vFxhVa3zlgEkxY9axwOQKe5xuAYa5jjcOb SmEg== X-Gm-Message-State: AOAM531mNiDw0A1Evz5ennS9wJqWHJxi3WMWd/zatZb0WfZAkPFA50Rp OqAVPfEjH+VNtM/0K7yFWsZoLZY1XY4BZA== X-Google-Smtp-Source: ABdhPJxZQnwkKD+vVPMuPQ+WYUk4Wo3w8AxT2upjENfULfMQCIUX2Af7F9ocbnB9sfbvAeMqYe+WrA== X-Received: by 2002:a17:903:288:b0:15f:a13:dfd5 with SMTP id j8-20020a170903028800b0015f0a13dfd5mr7035089plr.55.1654206561568; Thu, 02 Jun 2022 14:49:21 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 31/71] target/arm: Move error for sve%d property to arm_cpu_sve_finalize Date: Thu, 2 Jun 2022 14:48:13 -0700 Message-Id: <20220602214853.496211-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Keep all of the error messages together. This does mean that when setting many sve length properties we'll only generate one error, but we only really need one. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 51c5d8d4bc..e18f585fa7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -487,8 +487,13 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) "using only sve properties.\n"); } else { error_setg(errp, "cannot enable sve%d", vq * 128); - error_append_hint(errp, "This CPU does not support " - "the vector length %d-bits.\n", vq * 128); + if (vq_supported) { + error_append_hint(errp, "This CPU does not support " + "the vector length %d-bits.\n", vq * 128); + } else { + error_append_hint(errp, "SVE not supported by KVM " + "on this host\n"); + } } return; } else { @@ -606,12 +611,6 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "cannot enable %s", name); - error_append_hint(errp, "SVE not supported by KVM on this host\n"); - return; - } - cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value); cpu->sve_vq_init |= 1 << (vq - 1); } From patchwork Thu Jun 2 21:48:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638487 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=S/2QUKzL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgST4QZQz9s0w for ; Fri, 3 Jun 2022 08:20:25 +1000 (AEST) Received: from localhost ([::1]:57918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtB0-0002C1-Mg for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:20:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh4-0004zq-Tv for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:26 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:54151) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh1-0008Tv-8p for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:26 -0400 Received: by mail-pj1-x1034.google.com with SMTP id a10so6007407pju.3 for ; Thu, 02 Jun 2022 14:49:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OfdXIFbJWIlpAFLLIFA1bOTv8f8qnwiGd4/gzGRW5Ho=; b=S/2QUKzLpj7rQDmKwrBHIVqkBuvrWTiQsQ3iikuA9v7O9WXUcL3xbMZfiDuar06ZaN BY9oxBPtP5rMY1+m2R7cntIQVZOBhjGjl7QEom8CP5SJkIWGZwbVbGsEcAMRCX1e7W7C RyOKVJQltDJ0FKnOEgXDk5pyxcKN4TL98ub0sTKQGnh8qSvG4guQRnOT4Jqovj3by+v2 6TJAFeTR9Ovksch4IK31gDhDldc9IMnmYr3QXRoNBw1vAk+D/NMv21138NJzqiy4Ra+a bM5cB73OLCvBmBf0luPmnBGxcA4RDwQAn/K00zAZKWaslgn9+OQcOK7U2Tp5uCF/JjS8 wLpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OfdXIFbJWIlpAFLLIFA1bOTv8f8qnwiGd4/gzGRW5Ho=; b=IPNQv6jY+FSDFIpWL9frOB7qWgGOcyz2QwrywPzHtYnqYpojdgm3kd32ROAFvt4JrK jXY4Oa9bcsHRNaT5/8E/j8dHRIZvgFWD/MBVXf0lW6EybEr+Cnxa4kvEIXvN3cjDAQjR LGhgM8w2ZsNd1re0JJ2RtsWYlDCccpQXuK/vlhhr4KZWfHAUVp78uqvKksNYWaJ5PsqF +riLtqc8HnjkKxE01IMXrNXk1GsTMNgy2smKjaNVT27cvFvPQkhDUG30nozvt/w3rTib k5MUiNGk4krtunJV4olLClZ/AwKA8mbYvlGKe6a8Sao+c1+gZeN5nrAfMHlUqsLvL4ce F69Q== X-Gm-Message-State: AOAM5330RsHXyFvrxtFJDExWuZnTKa3hE6KNRt9oKppXeIekl5WvNcb2 1O4rOedtR+3XpqfH99dP5z5c8DlH48QtLg== X-Google-Smtp-Source: ABdhPJz6F97uEBEyAqbaECf05n8B71cnsGf+Ry9FLzwzkR98z3eHs+FI/aaLBtdVQ0GASHX87iTQrQ== X-Received: by 2002:a17:902:ccc4:b0:156:5d37:b42f with SMTP id z4-20020a170902ccc400b001565d37b42fmr7001379ple.157.1654206562436; Thu, 02 Jun 2022 14:49:22 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 32/71] target/arm: Create ARMVQMap Date: Thu, 2 Jun 2022 14:48:14 -0700 Message-Id: <20220602214853.496211-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Pull the three sve_vq_* values into a structure. This will be reused for SME. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 29 ++++++++++++++--------------- target/arm/cpu64.c | 22 +++++++++++----------- target/arm/helper.c | 2 +- target/arm/kvm64.c | 2 +- 4 files changed, 27 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b65e370b70..9408d36b8a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -793,6 +793,19 @@ typedef enum ARMPSCIState { typedef struct ARMISARegisters ARMISARegisters; +/* + * In map, each set bit is a supported vector length of (bit-number + 1) * 16 + * bytes, i.e. each bit number + 1 is the vector length in quadwords. + * + * While processing properties during initialization, corresponding init bits + * are set for bits in sve_vq_map that have been set by properties. + * + * Bits set in supported represent valid vector lengths for the CPU type. + */ +typedef struct { + uint32_t map, init, supported; +} ARMVQMap; + /** * ARMCPU: * @env: #CPUARMState @@ -1041,21 +1054,7 @@ struct ArchCPU { uint32_t sve_default_vq; #endif - /* - * In sve_vq_map each set bit is a supported vector length of - * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector - * length in quadwords. - * - * While processing properties during initialization, corresponding - * sve_vq_init bits are set for bits in sve_vq_map that have been - * set by properties. - * - * Bits set in sve_vq_supported represent valid vector lengths for - * the CPU type. - */ - uint32_t sve_vq_map; - uint32_t sve_vq_init; - uint32_t sve_vq_supported; + ARMVQMap sve_vq; /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e18f585fa7..0a2f4f3170 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -355,8 +355,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least one * vector length must be enabled. */ - uint32_t vq_map = cpu->sve_vq_map; - uint32_t vq_init = cpu->sve_vq_init; + uint32_t vq_map = cpu->sve_vq.map; + uint32_t vq_init = cpu->sve_vq.init; uint32_t vq_supported; uint32_t vq_mask = 0; uint32_t tmp, vq, max_vq = 0; @@ -369,14 +369,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (kvm_enabled()) { if (kvm_arm_sve_supported()) { - cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu)); - vq_supported = cpu->sve_vq_supported; + cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported = cpu->sve_vq.supported; } else { assert(!cpu_isar_feature(aa64_sve, cpu)); vq_supported = 0; } } else { - vq_supported = cpu->sve_vq_supported; + vq_supported = cpu->sve_vq.supported; } /* @@ -534,7 +534,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq = max_vq; - cpu->sve_vq_map = vq_map; + cpu->sve_vq.map = vq_map; } static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, @@ -595,7 +595,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value = false; } else { - value = extract32(cpu->sve_vq_map, vq - 1, 1); + value = extract32(cpu->sve_vq.map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } @@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value); - cpu->sve_vq_init |= 1 << (vq - 1); + cpu->sve_vq.map = deposit32(cpu->sve_vq.map, vq - 1, 1, value); + cpu->sve_vq.init |= 1 << (vq - 1); } static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -973,7 +973,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -1022,7 +1022,7 @@ static void aarch64_a64fx_initfn(Object *obj) /* The A64FX supports only 128, 256 and 512 bit vector lengths */ aarch64_add_sve_properties(obj); - cpu->sve_vq_supported = (1 << 0) /* 128bit */ + cpu->sve_vq.supported = (1 << 0) /* 128bit */ | (1 << 1) /* 256bit */ | (1 << 3); /* 512bit */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 5328676deb..2e7669180f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6291,7 +6291,7 @@ uint32_t sve_vqm1_for_el(CPUARMState *env, int el) len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + len = 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1)); return len; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 28001643c6..0ac9f0b802 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -818,7 +818,7 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs) static int kvm_arm_sve_set_vls(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq_map }; + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map }; struct kvm_one_reg reg = { .id = KVM_REG_ARM64_SVE_VLS, .addr = (uint64_t)&vls[0], From patchwork Thu Jun 2 21:48:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xSMA/M0k; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgdV55wwz9s0w for ; Fri, 3 Jun 2022 08:28:14 +1000 (AEST) Received: from localhost ([::1]:52550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtIa-0000sb-P6 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:28:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh5-00051i-Uf for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:27 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:50688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh3-0000Dk-0N for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:27 -0400 Received: by mail-pj1-x102a.google.com with SMTP id e24so6052335pjt.0 for ; Thu, 02 Jun 2022 14:49:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fwPtvhYNG8jCnQ1cI9YW7usJn3JNHfnrq4zhCHsHE5Y=; b=xSMA/M0k2HFgDdT5Zb9zPO5UXFa+VR6KG9aJ+cpopgoKzZk8P8fYjGtShrxcPWTnXV Fo5TMtWUkyh6Xxuvz6UjZhLPDlwi5h/CBgFyVJPrgmOMmA4AVBk09JN9SujYbTB8pc0q jMY6bygiH4TkGXJaY5a/bEyivgiLNCHbQzZYyD19b5iWjII5EQpDEPYesE4xMIONBskt z5P6LYqksu8d2IA0ZNLESqEpFH4RtXbaudEBTy+aX+eL8ndM9UlCkrZXMUyCZaHDRyO5 qve0x+PfRwoSfWaTzWh+lNaIbotfsJrwgmvmYeUkecmL9HD03HgfiK4Wm++nKycxpQ79 /SPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fwPtvhYNG8jCnQ1cI9YW7usJn3JNHfnrq4zhCHsHE5Y=; b=gx478GluW3Q6MCL2WyS9uvqJK6b2JzFyLwclPtpswfKUv+6TKk+ymhCjAg2dp+ilcm J7lQ92keu93NFfxlBu/NAjRf+QZoEAwgqRYX/aHE91cUauKkWj3xCQh3GwmNeB4spphm QYK3zItjgCSh+dsAUw60DfLzFIWV+mJHL6jcsb8XtvlzWjBtyWvZYlloNm6LvO/7xQEv kGtQrjIguyEHqtp6ez051V+biHAw5JLV0FxF3U4F/JzIkWXl01InTgEKhwD5IccLZAvG B5dwKgM145KAGkL37in7yqX2fYwbPK7wlealBRnlkzXTxm+tZN/Ptv5gI4qA9XleOgX5 Vq3Q== X-Gm-Message-State: AOAM531YcF9/eaV07shc0yTXuWXslMN3+K9qJYBADvQbncfuO1nztHqN KiWF6JBY0Rk8jUAMMvdgd5/GonFlRTHA8g== X-Google-Smtp-Source: ABdhPJwsSvo7HUl1ztYByNR+gD2lKfgk3Agi0GhPF9gXamXqS562Cgm/RcHjIcYDFakiu9eZ1tlCIQ== X-Received: by 2002:a17:902:e94e:b0:158:91e6:501 with SMTP id b14-20020a170902e94e00b0015891e60501mr6981799pll.29.1654206563365; Thu, 02 Jun 2022 14:49:23 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 33/71] target/arm: Generalize cpu_arm_{get,set}_vq Date: Thu, 2 Jun 2022 14:48:15 -0700 Message-Id: <20220602214853.496211-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rename from cpu_arm_{get,set}_sve_vq, and take the ARMVQMap as the opaque parameter. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0a2f4f3170..dcec0a6559 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -579,15 +579,15 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, } /* - * Note that cpu_arm_get/set_sve_vq cannot use the simpler - * object_property_add_bool interface because they make use - * of the contents of "name" to determine which bit on which - * to operate. + * Note that cpu_arm_{get,set}_vq cannot use the simpler + * object_property_add_bool interface because they make use of the + * contents of "name" to determine which bit on which to operate. */ -static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu = ARM_CPU(obj); + ARMVQMap *vq_map = opaque; uint32_t vq = atoi(&name[3]) / 128; bool value; @@ -595,15 +595,15 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value = false; } else { - value = extract32(cpu->sve_vq.map, vq - 1, 1); + value = extract32(vq_map->map, vq - 1, 1); } visit_type_bool(v, name, &value, errp); } -static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { - ARMCPU *cpu = ARM_CPU(obj); + ARMVQMap *vq_map = opaque; uint32_t vq = atoi(&name[3]) / 128; bool value; @@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, return; } - cpu->sve_vq.map = deposit32(cpu->sve_vq.map, vq - 1, 1, value); - cpu->sve_vq.init |= 1 << (vq - 1); + vq_map->map = deposit32(vq_map->map, vq - 1, 1, value); + vq_map->init |= 1 << (vq - 1); } static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -691,6 +691,7 @@ static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, void aarch64_add_sve_properties(Object *obj) { + ARMCPU *cpu = ARM_CPU(obj); uint32_t vq; object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); @@ -698,8 +699,8 @@ void aarch64_add_sve_properties(Object *obj) for (vq = 1; vq <= ARM_MAX_VQ; ++vq) { char name[8]; sprintf(name, "sve%d", vq * 128); - object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, - cpu_arm_set_sve_vq, NULL, NULL); + object_property_add(obj, name, "bool", cpu_arm_get_vq, + cpu_arm_set_vq, NULL, &cpu->sve_vq); } #ifdef CONFIG_USER_ONLY From patchwork Thu Jun 2 21:48:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=k/0rUhe9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgr80gdlz9s0w for ; Fri, 3 Jun 2022 08:37:27 +1000 (AEST) Received: from localhost ([::1]:43998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtRV-00067a-TC for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:37:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37604) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwshD-0005E8-6e for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:35 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:34462) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh3-0000EF-UP for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:34 -0400 Received: by mail-pl1-x62e.google.com with SMTP id n8so5549382plh.1 for ; Thu, 02 Jun 2022 14:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7xdazpoc98KTxU+Hkap6hV74hgs0EjjQuCmdWfoKk1g=; b=k/0rUhe93OnFpqfx96UKtFrthpyt5fraiPax6W4qdLrQZM0Vndxhk3/P8nSZ542XRO ySBOBL7OuHgSkho2UceHuQhS7cJajsl/gXcPWhtbC7k36B/DndU5+fExikfHhZnXBeYM RW0/PKDllXKL2gxYVZ5ZTx/H0T9RYiZR6pIaCCag1DsBtUouH3pjvjpzgX2XLFCw6zGX L3kmayLpNdhdptNLDLTJCbRFs80y4MxxyrJ8DZck/ls9/B8ZqBCcCy7sOVkw2svFX1W4 /HF6YT782uNIo6MXhz+uGQryI4v4WHEvrUiJccdrweIpTXUVNbrijNr/KD3Ev8bnpkNE Zb1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7xdazpoc98KTxU+Hkap6hV74hgs0EjjQuCmdWfoKk1g=; b=mmlLRSfH7STEPjZooxZ7v6CaHNE1jZe60Eb/00ripSjhVZp5EV0tTy7yQYWDtmz12x ymab3qFNMsgu7r75BfBxUcJ3Cvr/VVV2I5XZqVJa3Vcmll/ZaH95vZTtHwBP5lVyOlsI yi0JtUhdz5pdU/zlhWfiFy5R/QIDTIOFB3cwxbqykvhdIB2MhroSJHHSd8fqWQ5ZkdKa EXHb01lypwZOYqCUPEy1+BYM71ek0PqmFr+TiNlfMgAFf1Va4/oSN82KuhFzh0pO9QyB fO8VvU76TXXCzp5Ghyp20LF/tTWIcWgyaLT6RAvxpp3ZJaowotRXpAS9tf14/D017ogE xr4w== X-Gm-Message-State: AOAM530BnQ3wsrx4dEZJiS39hFzPDAr2aFvlydRXX2SP0xVsN3/YEHHn jdkwICufy6ogfODQfGOMhvdoxoI308jQkw== X-Google-Smtp-Source: ABdhPJwyFl5WTALLYrl4raJlXdGUb0bYw390ow3vYx6qDhjwdmJPPmhj4MWYvrPD44f3UBwvZfN4Sg== X-Received: by 2002:a17:90b:1e47:b0:1e6:7d04:2f4 with SMTP id pi7-20020a17090b1e4700b001e67d0402f4mr7336195pjb.93.1654206564595; Thu, 02 Jun 2022 14:49:24 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 34/71] target/arm: Generalize cpu_arm_{get, set}_default_vec_len Date: Thu, 2 Jun 2022 14:48:16 -0700 Message-Id: <20220602214853.496211-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rename from cpu_arm_{get,set}_sve_default_vec_len, and take the pointer to default_vq from opaque. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dcec0a6559..c5bfc3d082 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -638,11 +638,11 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) #ifdef CONFIG_USER_ONLY /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ -static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) { - ARMCPU *cpu = ARM_CPU(obj); + uint32_t *ptr_default_vq = opaque; int32_t default_len, default_vq, remainder; if (!visit_type_int32(v, name, &default_len, errp)) { @@ -651,7 +651,7 @@ static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, /* Undocumented, but the kernel allows -1 to indicate "maximum". */ if (default_len == -1) { - cpu->sve_default_vq = ARM_MAX_VQ; + *ptr_default_vq = ARM_MAX_VQ; return; } @@ -675,15 +675,15 @@ static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, return; } - cpu->sve_default_vq = default_vq; + *ptr_default_vq = default_vq; } -static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) { - ARMCPU *cpu = ARM_CPU(obj); - int32_t value = cpu->sve_default_vq * 16; + uint32_t *ptr_default_vq = opaque; + int32_t value = *ptr_default_vq * 16; visit_type_int32(v, name, &value, errp); } @@ -706,8 +706,9 @@ void aarch64_add_sve_properties(Object *obj) #ifdef CONFIG_USER_ONLY /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ object_property_add(obj, "sve-default-vector-length", "int32", - cpu_arm_get_sve_default_vec_len, - cpu_arm_set_sve_default_vec_len, NULL, NULL); + cpu_arm_get_default_vec_len, + cpu_arm_set_default_vec_len, NULL, + &cpu->sve_default_vq); #endif } From patchwork Thu Jun 2 21:48:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Y1TVtzgy; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgGW05Yqz9s0w for ; Fri, 3 Jun 2022 08:11:46 +1000 (AEST) Received: from localhost ([::1]:36454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt2e-0004ST-M9 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:11:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37498) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh8-00055U-44 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:30 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:33772) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh4-0000EW-Mx for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:29 -0400 Received: by mail-pl1-x629.google.com with SMTP id s12so5581228plp.0 for ; Thu, 02 Jun 2022 14:49:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cptDVDAPnRISvdNMPdFhnZ4KpjGI4FllpSb5JTC9nVk=; b=Y1TVtzgysdjXS8v9yyvcN78l81+LL6z7BGRlj9F5cg5qsk1GNXd+E6ownjs58Y4ATt oLXNXrAsSXavZ4x456Nl65F+52vgQHmfVgnPz/tvESferiWGle47qMoHRTq6ZL+CU0Wd bycl/zoS5ngKT8a7CaBWsZqzaEMqpJAEmcdie62oPPW4lYJk13WZrxrJ7ovEEajt0TSs ZRYEjAbTKeEVkoP6aWObiG3TDnQ80oZApAo8+P9tzK0hHCHgxYP3ZvLtmx/5FlRtJWWh 7h9NCO/VVuPMcbcwOBPiry+cNO23+9Jz/283BJIt/joB3G4TxA3qkaNOHKliRP9oSdzQ R41Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cptDVDAPnRISvdNMPdFhnZ4KpjGI4FllpSb5JTC9nVk=; b=v7ztF3dy4mk5+jKo1yzCcmgiZAgJ8bDGvwJJ7MVt/7COCAplXnc8Hw33MxJmtbutWu raTRd3Jlw3Q+mgJc5i6AECm5r0MHNhhbEtNCuVQStbvoyBT2F6J73o6f0ohkLGkElBNL INBwyPI8AEfxYrEpzWAV/qgDsub667lTpCHc1C1pNJizmLz+crfj/vgtGo7pjw+gV4Ub xJpLmLJiK5WDiqMtOVUOlqbh2bJI+s8Fmm6KfSd6/FxaJZscAa+uHjhKTie3DlgzdhQw yJw+Hyq6Wp6M4UqD/fsMWf8x/gCdn16bUYcSa3RaiQznrx2i8svJ+j/kLc1YsKqy7LcR +rbw== X-Gm-Message-State: AOAM532t204qijAjBxWI05RsY3d5N0M6ptVO6jIj3x4p44260nR9IB+l JbhOzAIORNBllmhfUubSGupmdV6Ka+VUlA== X-Google-Smtp-Source: ABdhPJyYhE0UTJyeVkvvKEx0p4hn/qKUQUSIkkCuzh6W/0URakaIfJRNpW1UuP2U36ocZ5lIWH7UKg== X-Received: by 2002:a17:903:41c6:b0:164:1050:49ac with SMTP id u6-20020a17090341c600b00164105049acmr6983047ple.138.1654206565342; Thu, 02 Jun 2022 14:49:25 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 35/71] target/arm: Move arm_cpu_*_finalize to internals.h Date: Thu, 2 Jun 2022 14:48:17 -0700 Message-Id: <20220602214853.496211-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Drop the aa32-only inline fallbacks, and just use a couple of ifdefs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 ------ target/arm/internals.h | 3 +++ target/arm/cpu.c | 2 ++ 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9408d36b8a..3999152f1a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -205,14 +205,8 @@ typedef struct { #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 -static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } -static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } -static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } #endif typedef struct ARMVectorReg { diff --git a/target/arm/internals.h b/target/arm/internals.h index 8bac570475..756301b536 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1309,6 +1309,9 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif #ifdef CONFIG_USER_ONLY diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..b5276fa944 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1421,6 +1421,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) { Error *local_err = NULL; +#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err != NULL) { @@ -1440,6 +1441,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } } +#endif if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); From patchwork Thu Jun 2 21:48:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638478 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=d0rKmwUv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgKw457Mz9s0w for ; Fri, 3 Jun 2022 08:14:43 +1000 (AEST) Received: from localhost ([::1]:44824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwt5U-0001et-83 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:14:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh8-00056J-Pj for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:31 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:44705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh4-00005u-TA for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:30 -0400 Received: by mail-pf1-x433.google.com with SMTP id g205so5773136pfb.11 for ; Thu, 02 Jun 2022 14:49:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iaX51RzKkNkmjJGOwJXKVNsxoyHghI2U9FbxI6i+VnE=; b=d0rKmwUvB6yPZwyGwCyJfXCSzA9YcAC8VhLaIRccw6LtWR1VfuxiBIswfCO1W2wl53 Zu58g3SMNM0rIkgsd2A2e7/5EKjAgkl4u/C2Qcz7t7FrGlXwWYUmXcBRiXXOM4cs0Vat oC2+etbWcV1kevfEjBfLYFRExTUTO5lpWI2A0LX6QiZwIKSUHPKgJB3f+Y+UVj8y1Qbj qW5OK3FU4ON+wfssG9p5zbG0QP51yl3PNQF3Ekn2ltZtDPSzRpadvvLIR+6P5MV6Zwqd INiRNECn/6MQg3jboaFxSu2/8Nj3VxDRUFARvTjOGbA3qVW3CxruJdYtQ96QnAyzvrNv itmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iaX51RzKkNkmjJGOwJXKVNsxoyHghI2U9FbxI6i+VnE=; b=DwSjp50LHPwxHMFd36feZU+e+ZQ/d7TuKtfdqtjTB8XymqFa4I3C5wQ/UCLJeH1/h3 O7KY5aTX78VRkovFEnNmx77eZedaBSmCANAAmpWridTm6xp5vHzcxSLz9J9Il046ghQx JsmeOY35y+BA/7/6qxOCYmmSLMYIa7QZQSSlhAwHhgJXAuPIhu130qKEKYDOK73iBjjs CkbIa8UAj16fvEhvLT1BLmgITM5cCYZHzOhuuvz6GW3WCijhicV/fpEhwYUu2eXkUocu taCI/BYKPj5z45yZhjqEASsTga/TfApc1dgIspID1wJYm+c8KPtjrOM+BsBBG1Wob6vK vVeA== X-Gm-Message-State: AOAM531vpxlUQsAz39MVhREV9YLq1/FpBAVS/K8b/rlqzizPxLK30hgG d7D44JJpRfsVSK42EoKazQTWViO0ugFF/w== X-Google-Smtp-Source: ABdhPJyOYfwVB1iJ8TrB8eYkmDcTeq7eRUC8ZCWWzgz6ULgkvTPidb6PHSRQzH3vE85476IWooOKQQ== X-Received: by 2002:a63:86c3:0:b0:3fb:de4b:4de1 with SMTP id x186-20020a6386c3000000b003fbde4b4de1mr5891328pgd.198.1654206566071; Thu, 02 Jun 2022 14:49:26 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 36/71] target/arm: Unexport aarch64_add_*_properties Date: Thu, 2 Jun 2022 14:48:18 -0700 Message-Id: <20220602214853.496211-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These functions are not used outside cpu64.c, so make them static. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 --- target/arm/cpu64.c | 4 ++-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3999152f1a..60f84ba033 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1097,8 +1097,6 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); -void aarch64_add_sve_properties(Object *obj); -void aarch64_add_pauth_properties(Object *obj); void arm_reset_sve_state(CPUARMState *env); /* @@ -1130,7 +1128,6 @@ static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } -static inline void aarch64_add_sve_properties(Object *obj) { } #endif void aarch64_sync_32_to_64(CPUARMState *env); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c5bfc3d082..9ae9be6698 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -689,7 +689,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v, } #endif -void aarch64_add_sve_properties(Object *obj) +static void aarch64_add_sve_properties(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); uint32_t vq; @@ -752,7 +752,7 @@ static Property arm_cpu_pauth_property = static Property arm_cpu_pauth_impdef_property = DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); -void aarch64_add_pauth_properties(Object *obj) +static void aarch64_add_pauth_properties(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); From patchwork Thu Jun 2 21:48:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638500 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cxnVdPAo; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDglV5DCvz9s0w for ; Fri, 3 Jun 2022 08:33:25 +1000 (AEST) Received: from localhost ([::1]:35406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtNZ-0008WJ-Tq for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:33:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsh9-00058c-OV for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:31 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:40582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh7-0000F5-Bg for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:31 -0400 Received: by mail-pj1-x1031.google.com with SMTP id n13-20020a17090a394d00b001e30a60f82dso10608719pjf.5 for ; Thu, 02 Jun 2022 14:49:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/vO3Yto/XnsTJAh/EMBZYKjobNaPPy/x1NLNYISgx84=; b=cxnVdPAoEYngXlGBzq26iAozhPorMjLhqugxLL897SRao+LQCtXQX1IfOhfkfaNgHs jYyeHzaeRCXl9Wu3rssmwTLq675aBaWmJLIBTHokDhO/BqJIa0sQAfhp2/o3m+aT6lSs tTQ3ANsQQrOtJWC0ek27SscxVLWhUgaNvr/wXgRa9MCdN6HyRMCL5eny4oyNFD1a4Q52 pL/URiZs5Ch1YuVPxxVbsUtPng42I83112+CMy4O6Z9sIIWqRmoE5OJ+tqI+oYCfGHui XQVpfpRwmRCqNUBOrPGUKHttFXm/C0uq4Tb42l3Vw/1+nKWlzajBf2TgrmuVH5Yx1Ok1 ZFPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/vO3Yto/XnsTJAh/EMBZYKjobNaPPy/x1NLNYISgx84=; b=chnMyWFd6dMmwwCrZGuVauMGoRDDmQQJfsC9fkYXKOVoGkdAIZ5q1Ue0rDLFP1iUQ4 KPN7ivib/J4oCnIIfXrEEse/Lw6m4rmrSCtApQrHbkODhYTFcZZkZRFmq2P4mx2lfNDw k6TbXQ0E99UnojRr6GxNkduB2zzfukeiJpHwguoccnUXnElhgrTJA0NjFS+j29CE4/0Q 7+uR5VZka+z8JtMuDXPUgEq0mduuX5IntKpbPpLeq41BZiOH1ZwBFQGCG2HD2h6dG9VW 2+aoYMsq6eqsd/kJpqH0HTRANnBwZ3TRealkBHrsOuo+mtCGwHwwhrBm+0+HrlWfY4Im 7vhw== X-Gm-Message-State: AOAM533/6B4jaJOCBmvlOZImQspOnDs4jdfpJv2VwyPg1lswpuKM7ajN nfkVMy8iHYlCjwxfCD9W2hWBmORmnpzulg== X-Google-Smtp-Source: ABdhPJzPLXo6nTrCihK2nWjCv74ZOy1gabx6sdPRIbpqc/7usWY+6Mi3SLe5izMolAc8mC5bpWgSOQ== X-Received: by 2002:a17:90a:64c5:b0:1e6:a230:2a71 with SMTP id i5-20020a17090a64c500b001e6a2302a71mr2448171pjm.49.1654206566934; Thu, 02 Jun 2022 14:49:26 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 37/71] target/arm: Add cpu properties for SME Date: Thu, 2 Jun 2022 14:48:19 -0700 Message-Id: <20220602214853.496211-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point for bugs. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 + target/arm/internals.h | 1 + target/arm/cpu.c | 14 +++-- target/arm/cpu64.c | 114 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 124 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 60f84ba033..d74c06e2f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1046,9 +1046,11 @@ struct ArchCPU { #ifdef CONFIG_USER_ONLY /* Used to set the default vector length at process start. */ uint32_t sve_default_vq; + uint32_t sme_default_vq; #endif ARMVQMap sve_vq; + ARMVQMap sme_vq; /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 756301b536..7e160d1349 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1310,6 +1310,7 @@ int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b5276fa944..75295a14a3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1122,11 +1122,13 @@ static void arm_cpu_initfn(Object *obj) #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 /* - * The linux kernel defaults to 512-bit vectors, when sve is supported. - * See documentation for /proc/sys/abi/sve_default_vector_length, and - * our corresponding sve-default-vector-length cpu property. + * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. + * These values were chosen to fit within the default signal frame. + * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, + * and our corresponding cpu property. */ cpu->sve_default_vq = 4; + cpu->sme_default_vq = 2; # endif #else /* Our inbound IRQ and FIQ lines */ @@ -1429,6 +1431,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) return; } + arm_cpu_sme_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + arm_cpu_pauth_finalize(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9ae9be6698..aaf2c243d6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -589,10 +589,13 @@ static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name, ARMCPU *cpu = ARM_CPU(obj); ARMVQMap *vq_map = opaque; uint32_t vq = atoi(&name[3]) / 128; + bool sve = vq_map == &cpu->sve_vq; bool value; - /* All vector lengths are disabled when SVE is off. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { + /* All vector lengths are disabled when feature is off. */ + if (sve + ? !cpu_isar_feature(aa64_sve, cpu) + : !cpu_isar_feature(aa64_sme, cpu)) { value = false; } else { value = extract32(vq_map->map, vq - 1, 1); @@ -636,8 +639,80 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) cpu->isar.id_aa64pfr0 = t; } +void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +{ + uint32_t vq_map = cpu->sme_vq.map; + uint32_t vq_init = cpu->sme_vq.init; + uint32_t vq_supported = cpu->sme_vq.supported; + uint32_t vq; + + if (vq_map == 0) { + if (!cpu_isar_feature(aa64_sme, cpu)) { + cpu->isar.id_aa64smfr0 = 0; + return; + } + + /* TODO: KVM will require limitations via SMCR_EL2. */ + vq_map = vq_supported & ~vq_init; + + if (vq_map == 0) { + vq = ctz32(vq_supported) + 1; + error_setg(errp, "cannot disable sme%d", vq * 128); + error_append_hint(errp, "All SME vector lengths are disabled.\n"); + error_append_hint(errp, "With SME enabled, at least one " + "vector length must be enabled.\n"); + return; + } + } else { + if (!cpu_isar_feature(aa64_sme, cpu)) { + vq = 32 - clz32(vq_map); + error_setg(errp, "cannot enable sme%d", vq * 128); + error_append_hint(errp, "SME must be enabled to enable " + "vector lengths.\n"); + error_append_hint(errp, "Add sme=on to the CPU property list.\n"); + return; + } + /* TODO: KVM will require limitations via SMCR_EL2. */ + } + + cpu->sme_vq.map = vq_map; +} + +static bool cpu_arm_get_sme(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu_isar_feature(aa64_sme, cpu); +} + +static void cpu_arm_set_sme(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint64_t t; + + t = cpu->isar.id_aa64pfr1; + t = FIELD_DP64(t, ID_AA64PFR1, SME, value); + cpu->isar.id_aa64pfr1 = t; +} + +static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu_isar_feature(aa64_sme, cpu) && + cpu_isar_feature(aa64_sme_fa64, cpu); +} + +static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint64_t t; + + t = cpu->isar.id_aa64smfr0; + t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value); + cpu->isar.id_aa64smfr0 = t; +} + #ifdef CONFIG_USER_ONLY -/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ +/* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */ static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -663,7 +738,11 @@ static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v, * and is the maximum architectural width of ZCR_ELx.LEN. */ if (remainder || default_vq < 1 || default_vq > 512) { - error_setg(errp, "cannot set sve-default-vector-length"); + ARMCPU *cpu = ARM_CPU(obj); + const char *which = + (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); + + error_setg(errp, "cannot set %s-default-vector-length", which); if (remainder) { error_append_hint(errp, "Vector length not a multiple of 16\n"); } else if (default_vq < 1) { @@ -712,6 +791,31 @@ static void aarch64_add_sve_properties(Object *obj) #endif } +static void aarch64_add_sme_properties(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t vq; + + object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme); + object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64, + cpu_arm_set_sme_fa64); + + for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) { + char name[8]; + sprintf(name, "sme%d", vq * 128); + object_property_add(obj, name, "bool", cpu_arm_get_vq, + cpu_arm_set_vq, NULL, &cpu->sme_vq); + } + +#ifdef CONFIG_USER_ONLY + /* Mirror linux /proc/sys/abi/sme_default_vector_length. */ + object_property_add(obj, "sme-default-vector-length", "int32", + cpu_arm_get_default_vec_len, + cpu_arm_set_default_vec_len, NULL, + &cpu->sme_default_vq); +#endif +} + void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { int arch_val = 0, impdef_val = 0; @@ -976,9 +1080,11 @@ static void aarch64_max_initfn(Object *obj) #endif cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); + cpu->sme_vq.supported = SVE_VQ_POW2_MAP; aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); + aarch64_add_sme_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); From patchwork Thu Jun 2 21:48:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ZgosxLuu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgbk2Ycgz9s0w for ; Fri, 3 Jun 2022 08:26:42 +1000 (AEST) Received: from localhost ([::1]:48096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtH6-0006Je-95 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:26:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwshA-0005AX-PK for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:32 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:38803) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh7-0008Uu-L3 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:32 -0400 Received: by mail-pj1-x1034.google.com with SMTP id v11-20020a17090a4ecb00b001e2c5b837ccso10610722pjl.3 for ; Thu, 02 Jun 2022 14:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WhJvn7lta1l85O0X30U0sb1LNyfda1dipXteH4TF7HU=; b=ZgosxLuuS454bCUZqRWGQ/vjx886IWWL9b+2MM5eIiSKYiRmBtVyIpj9cT+F4pk4Dv pL0uT8SOVNUjfifkmo90DyBsEQQp3YrZ3LwSZADRtJctV5/x89xiONlTmdCT2aAC6HDE 63Vd0HOeI9Z0JL4zLE8BNDeK/mooJr+VQIWUXze3Mm8mQ2c4qV5w32OB+rtEkn7IXHri Ti/NmV1aUtExCNehxnR+TRaLpj0sm2opHYpF0ukwRNSbOWxHvHuKPF+SwoL1i6P5Qrz9 AEHQPvQ7VikI2hHltfaZaEQsAjj6p3RokizZrW5G+aIfqxM920cSrfALF3aY6D/f9TK0 x/gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WhJvn7lta1l85O0X30U0sb1LNyfda1dipXteH4TF7HU=; b=axu6eJwvu//sCpPK00+W4+6WCAqUwJQmw8+q12nltmbJTV3IXwuMOHx3KmnGH8h4dt w27I04ZfWs+Lr5FKRpKIlQZr+MfCsnMkmTniA2vaJ9aTiDOiC7GrazqLn5IRPcuP9hZ+ bm8LkJNq9z3w9C901FkwI1RpXi1TqsSW+XokojuNULelPOhWRgp3rjLWxfpMOLTgZ5Dk SIwqQL/9AtQ7DUZl4GD5tXZ5+Sh59NaLp2tbE90JEuows/3NX65rD931h/z87u4aI3vS xAhNDg4cU1tJ1JEiwUwHiMvnflurAn0IgtdUP6X74YftCa8nxeBPfp0W4heRcSsGB64J M6jQ== X-Gm-Message-State: AOAM531DKP17ohVlix8a7DmEGknDGPbCQYOHkLaMsOe9w0hlIU99OMuw optPQmafpCG5ZisARkuPIIglOTs+UxttpA== X-Google-Smtp-Source: ABdhPJx1nEf/jfxJN4YdyugQ0ld78xSTm+nclM5Bowt/sFm54MLW827m7KqIeTQGmuQzPClMv+yMvA== X-Received: by 2002:a17:903:18a:b0:166:ba97:8b19 with SMTP id z10-20020a170903018a00b00166ba978b19mr1719240plg.62.1654206567847; Thu, 02 Jun 2022 14:49:27 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 38/71] target/arm: Introduce sve_vqm1_for_el_sm Date: Thu, 2 Jun 2022 14:48:20 -0700 Message-Id: <20220602214853.496211-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When Streaming SVE mode is enabled, the size is taken from SMCR_ELx instead of ZCR_ELx. The format is shared, but the set of vector lengths is not. Further, Streaming SVE does not require any particular length to be supported. Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM to the new function. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++-- target/arm/helper.c | 32 +++++++++++++++++++++++++------- 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d74c06e2f0..e41a75a3a3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1140,13 +1140,18 @@ int sve_exception_el(CPUARMState *env, int cur_el); int sme_exception_el(CPUARMState *env, int cur_el); /** - * sve_vqm1_for_el: + * sve_vqm1_for_el_sm: * @env: CPUARMState * @el: exception level + * @sm: streaming mode * - * Compute the current SVE vector length for @el, in units of + * Compute the current vector length for @el & @sm, in units of * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. + * If @sm, compute for SVL, otherwise NVL. */ +uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); + +/* Likewise, but using @sm = PSTATE.SM. */ uint32_t sve_vqm1_for_el(CPUARMState *env, int el); static inline bool is_a64(CPUARMState *env) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2e7669180f..cb78d2354a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6276,23 +6276,41 @@ int sme_exception_el(CPUARMState *env, int el) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_vqm1_for_el(CPUARMState *env, int el) +uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) { ARMCPU *cpu = env_archcpu(env); - uint32_t len = cpu->sve_max_vq - 1; + uint64_t *cr = env->vfp.zcr_el; + uint32_t map = cpu->sve_vq.map; + uint32_t len = ARM_MAX_VQ - 1; + + if (sm) { + cr = env->vfp.smcr_el; + map = cpu->sme_vq.map; + } if (el <= 1 && !el_is_in_host(env, el)) { - len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len = MIN(len, 0xf & (uint32_t)cr[1]); } if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { - len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len = MIN(len, 0xf & (uint32_t)cr[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len = MIN(len, 0xf & (uint32_t)cr[3]); } - len = 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1)); - return len; + map &= MAKE_64BIT_MASK(0, len + 1); + if (map != 0) { + return 31 - clz32(map); + } + + /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ + assert(sm); + return ctz32(cpu->sme_vq.map); +} + +uint32_t sve_vqm1_for_el(CPUARMState *env, int el) +{ + return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Thu Jun 2 21:48:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CxkQgTgD; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgp24m32z9s0w for ; Fri, 3 Jun 2022 08:35:38 +1000 (AEST) Received: from localhost ([::1]:39384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtPk-0002oi-NY for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:35:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwshB-0005Bs-4M for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:33 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:44661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsh8-0000FO-3c for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:49:32 -0400 Received: by mail-pj1-x1029.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so5871690pjb.3 for ; Thu, 02 Jun 2022 14:49:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vIa3IKSRhaxqBOPG/jC3fFgT7YknLf0taajsFi5iMbc=; b=CxkQgTgDspiCl6evqzvPC5yvHEv0VHs/h01QaGsfqfhxlD4VVrRyTad1kbeuDLI53m 9MRIx1YDMIBs6ua6wXZi8TA2e6BdvTYAt1FabKkug8VC1EM8NfHL28F87O64ukcMJ6zw cAwWi9e2dAIc7nzazVeDcBzpUZnBAut/OCXES2ewALjVzGIFl3wkLrf3IkK6IlFNRr3w wGp21w+bt/2QojUKt0jVYRa3erloOEZujl27LxtX4dU5hyT2gruUo82uyX08ihyO03mq gXIjnFrrqWiFmUhz/4WK4hxJw7SUuWwKpDqc2HDNTauMF62oTTLr/M19bI8wS5pzZLw8 Ywog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vIa3IKSRhaxqBOPG/jC3fFgT7YknLf0taajsFi5iMbc=; b=3TQE1Duh/qQe54aX5ePCqtXV2CEeUcCkOJK8b2Snus7ZXC+AkUDcGUYXIgTAy0CYoV XrTpLObfenwm+8qpFdk18kEPB559tfETTrA48EsDN3dEEdht+vB8Cs7axUHJPutk8eHw 41D9pRFYb7GXpT8NVgtWqvFZsDYSRGdvKmiF4TlcjzITgbT9B9SOJqVPn1pO8rhalmsf S7iNCqi4ZSRhXmORWTGWcEGRCYco65yNcbeVKaazx56eL/6XSKGXtIAgCVzYaZPfpKp2 VNKTgNXr7IZC2y7B2PqFAT2WaNSGH8vFPhU8XaJfFFtb8y9ZZwBRDGypV5Ud1VqoFCXl KPwg== X-Gm-Message-State: AOAM530EWrMUZxdWTlbt2vQyFteBy85DzF3c7ws5ABqfbhPJ91tn/abQ JfSYyCYm+lq9tZh2M1cfnb0g0EyaUwNnCg== X-Google-Smtp-Source: ABdhPJxf9x3DC/GAbMPopAD3M7cnSE7Be+7M3wfvDxQel2FJMnufSzY1aof7SPmrRuUJglx/DN8IJQ== X-Received: by 2002:a17:90b:1d08:b0:1e3:2a4f:6935 with SMTP id on8-20020a17090b1d0800b001e32a4f6935mr20021139pjb.174.1654206568670; Thu, 02 Jun 2022 14:49:28 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id bf7-20020a170902b90700b00163c6ac211fsm3988760plb.111.2022.06.02.14.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:49:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 39/71] target/arm: Add SVL to TB flags Date: Thu, 2 Jun 2022 14:48:21 -0700 Message-Id: <20220602214853.496211-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We need SVL separate from VL for RDSVL at al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/translate.h | 1 + target/arm/helper.c | 8 +++++++- target/arm/translate-a64.c | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e41a75a3a3..0c32c3afaa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) +FIELD(TBFLAG_A64, SVL, 24, 4) /* * Helpers for using the above. @@ -3337,6 +3338,17 @@ static inline int sve_vq_cached(CPUARMState *env) return EX_TBFLAG_A64(env->hflags, VL) + 1; } +/** + * sme_vq_cached + * @env: the cpu context + * + * Return the SVL cached within env->hflags, in units of quadwords. + */ +static inline int sme_vq_cached(CPUARMState *env) +{ + return EX_TBFLAG_A64(env->hflags, SVL) + 1; +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/translate.h b/target/arm/translate.h index fbd6713572..1330281f8b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -44,6 +44,7 @@ typedef struct DisasContext { int sve_excp_el; /* SVE exception EL or 0 if enabled */ int sme_excp_el; /* SME exception EL or 0 if enabled */ int vl; /* current vector length in bytes */ + int svl; /* current streaming vector length in bytes */ /* Flag indicating that exceptions from secure mode are routed to EL3. */ bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ diff --git a/target/arm/helper.c b/target/arm/helper.c index cb78d2354a..c9db12d524 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13874,7 +13874,13 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); } if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_exception_el(env, el)); + int sme_el = sme_exception_el(env, el); + + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); + if (sme_el == 0) { + /* Similarly, do not compute SVL if SME is disabled. */ + DP_TBFLAG_A64(flags, SVL, sve_vqm1_for_el_sm(env, el, true)); + } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 40f2e53983..b1d2840819 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14652,6 +14652,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; + dc->svl = (EX_TBFLAG_A64(tb_flags, SVL) + 1) * 16; dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE); dc->bt = EX_TBFLAG_A64(tb_flags, BT); dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE); From patchwork Thu Jun 2 21:48:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=fM7kWSPo; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgS10HkHz9s0w for ; Fri, 3 Jun 2022 08:19:59 +1000 (AEST) Received: from localhost ([::1]:57430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtAa-0001rl-H7 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:19:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsk5-0001H8-LF for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:36 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:40598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk3-0000qT-Pi for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:33 -0400 Received: by mail-pj1-x1035.google.com with SMTP id n13-20020a17090a394d00b001e30a60f82dso10614059pjf.5 for ; Thu, 02 Jun 2022 14:52:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nRiBuDw8xOiappiLJwDebAsj0dPMzIOBq+w1XQpJT0Q=; b=fM7kWSPoPsOpsNcgXm2pQIidO50rUK9XXznyD7PbsOGHl2ri9C4h932bt2AAdjwJHP Pff9LXc5xtJLRLmkqRuHh6eFiD3sr6EgwA5EKLsZB1hojTq5R1CY2P2TSryPF+cjyn6N QfUSF0GRm5QkmQ3KrJiUNrQK2PwT4YgFiiczm9kmCGBrpR/MDKzz5tfUSv7wygHwDLbj VUYPa3PJnDUJn68f7CxWKg+SNYz6/+a76102ZH8iUst0KUi58rklTh7nkAKkTdpN+vaU CG8uDk+a8N3PRiMxO3dIZv9kHHPEE03CE1yFzAdwfFOXhaV2AoZ7qM6Xsf4RW4xhdft/ bssg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nRiBuDw8xOiappiLJwDebAsj0dPMzIOBq+w1XQpJT0Q=; b=NgmlZ/YDQDCNO/yZHm9XrA5ivabp3l8DXEHtALkoCxrGDkQvulhs0SeskDZIAQhIOX 5eYNafj2Us4yUZiTAHlevsuEo3cvQvRfLFNcIVNy/nJjHL8n0zZtK0f3S6Aeg0SIAtbb CVXXArdZeAPFNnVquUQW8yOw66DyX22fJ/9Cc6ecCVseABrwjbuyigwZ0RQ8nc/0cyNo VM4rNWm7+gqB1MT7v5+BB72zexysPO5MYYh5ykN2Xqh6tSmfj+tnJrUoGMQaCmKSWIa9 P3trnygBJGy5wBs1XRXc2zuttJYklNoMkD5sEmRpYc2o0MjnRjIDxhWNCwZCpAWEI6Qj TwSQ== X-Gm-Message-State: AOAM532d1rDcuMGTPLtTNIGN1bUNUTUtf6lQiV3EjYWAA5JxNheUI2nM jWq2uT9rikgRryk1UGAxzrYjH9fWEJzN9A== X-Google-Smtp-Source: ABdhPJxt62E0QDlOekV45NJINGmdXI8PdTQ+PGyYHVW2J1ollTwYfF4RP9tCbB8e0vFw1v6u6Z/SjA== X-Received: by 2002:a17:902:7b8b:b0:166:332f:2490 with SMTP id w11-20020a1709027b8b00b00166332f2490mr6853007pll.68.1654206750287; Thu, 02 Jun 2022 14:52:30 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 40/71] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h Date: Thu, 2 Jun 2022 14:48:22 -0700 Message-Id: <20220602214853.496211-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We will need these functions in translate-sme.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 38 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 36 ------------------------------------ 2 files changed, 38 insertions(+), 36 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index dbc917ee65..f0970c6b8c 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -107,6 +107,44 @@ static inline int vec_full_reg_size(DisasContext *s) return s->vl; } +/* + * Return the offset info CPUARMState of the predicate vector register Pn. + * Note for this purpose, FFR is P16. + */ +static inline int pred_full_reg_offset(DisasContext *s, int regno) +{ + return offsetof(CPUARMState, vfp.pregs[regno]); +} + +/* Return the byte size of the whole predicate register, VL / 64. */ +static inline int pred_full_reg_size(DisasContext *s) +{ + return s->vl >> 3; +} + +/* + * Round up the size of a register to a size allowed by + * the tcg vector infrastructure. Any operation which uses this + * size may assume that the bits above pred_full_reg_size are zero, + * and must leave them the same way. + * + * Note that this is not needed for the vector registers as they + * are always properly sized for tcg vectors. + */ +static inline int size_for_gvec(int size) +{ + if (size <= 8) { + return 8; + } else { + return QEMU_ALIGN_UP(size, 16); + } +} + +static inline int pred_gvec_reg_size(DisasContext *s) +{ + return size_for_gvec(pred_full_reg_size(s)); +} + bool disas_sve(DisasContext *, uint32_t); void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 67761bf2cc..62b5f3040c 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -100,42 +100,6 @@ static inline int msz_dtype(DisasContext *s, int msz) * Implement all of the translator functions referenced by the decoder. */ -/* Return the offset info CPUARMState of the predicate vector register Pn. - * Note for this purpose, FFR is P16. - */ -static inline int pred_full_reg_offset(DisasContext *s, int regno) -{ - return offsetof(CPUARMState, vfp.pregs[regno]); -} - -/* Return the byte size of the whole predicate register, VL / 64. */ -static inline int pred_full_reg_size(DisasContext *s) -{ - return s->vl >> 3; -} - -/* Round up the size of a register to a size allowed by - * the tcg vector infrastructure. Any operation which uses this - * size may assume that the bits above pred_full_reg_size are zero, - * and must leave them the same way. - * - * Note that this is not needed for the vector registers as they - * are always properly sized for tcg vectors. - */ -static int size_for_gvec(int size) -{ - if (size <= 8) { - return 8; - } else { - return QEMU_ALIGN_UP(size, 16); - } -} - -static int pred_gvec_reg_size(DisasContext *s) -{ - return size_for_gvec(pred_full_reg_size(s)); -} - /* Invoke an out-of-line helper on 2 Zregs. */ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn, int rd, int rn, int data) From patchwork Thu Jun 2 21:48:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CWKhqRzo; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgtC3vlRz9s0w for ; Fri, 3 Jun 2022 08:39:14 +1000 (AEST) Received: from localhost ([::1]:48064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtTC-0000Og-RY for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:39:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsk9-0001IB-1e for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:37 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:45777) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk4-0000rf-KW for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:34 -0400 Received: by mail-pj1-x102a.google.com with SMTP id w2-20020a17090ac98200b001e0519fe5a8so5873332pjt.4 for ; Thu, 02 Jun 2022 14:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rJ9jQIVXgPW88TErZyxfJAphrMIXEeDwD7105AVfBkg=; b=CWKhqRzoztu9sfKpoafhnPVyKzgXn+P7p7DbyllQXjCOEjrH4C3ANZXGe7myOntxkK woQwAnimkp986a+AsqC41Oe1Cbvk+hbWzJ6TjjjgJF90EeTayaQI10Y9RsCWsVjAK5jc QHkVZdOyNWMdHfwtudPabqmcFBkp+GcxgZPFR7Y4HNDtZo6FvxKiTRRGE+XiXBcrH5SF Esz9kz4eNS5If5xQac3xGCIyzxFxJlLDYHIunLweDkHapT4yn8QCzgfI9zxCS2EhYL1+ +5S7X2JgqhSA7kKND8XJGMMFQ0IoRM2acMjIgYCJNrSk0c0B6ZHXvr/12Hau0ucjPwML w0Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rJ9jQIVXgPW88TErZyxfJAphrMIXEeDwD7105AVfBkg=; b=Pmc22OYmzJRh1z3GyTTKrwZ+Ys1M8vWczOfuVqMkNePWENbjegNoq4Ian99IneRazC u1qAgOyRqk1+Fl0+Zx+kXtjQXYatpaQZM6CL4CzlhcsL7VIJkFxkFCXPnKdAsHPLLHS5 QMuaogOs5FB0fzDxmJkXqMZYGG7FGC0sNK/BSh7K7sHoG9Z5fkxCBO16TPd7qZg6K6dp YOg6QUO8DAxrzb0ge72eh8nwDaeNDZ1OjLWfjcAhLaO9OwRWSj2hYFdLSKJIGpoXdo4I EblH0mVw6jrmpOqJpLELj4FQ8EvYYEmmXPInae4/dJOh9ZgVmeGXnaWDqkMOU6EmFFTM hCSg== X-Gm-Message-State: AOAM532Jf0cc4y+G1xNEkb8OEFTjuDLlQdL3cQe1IifZIi1Nt9SlhFM2 N6aK5vxsjkyjUSpipJzQ6SDrzGT2sduGMw== X-Google-Smtp-Source: ABdhPJwgC9q4rK9+XHcPYnMVp4UzQotMDmwFYHqltqCQ4Don3KpSbJCQHg7AAkHZJ+rsav9BP8eGTQ== X-Received: by 2002:a17:90b:1bc5:b0:1e3:3c67:37bf with SMTP id oa5-20020a17090b1bc500b001e33c6737bfmr7470973pjb.87.1654206751124; Thu, 02 Jun 2022 14:52:31 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 41/71] target/arm: Add infrastructure for disas_sme Date: Thu, 2 Jun 2022 14:48:23 -0700 Message-Id: <20220602214853.496211-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 1 + target/arm/sme.decode | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 7 ++++++- target/arm/translate-sme.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 ++ 5 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 target/arm/sme.decode create mode 100644 target/arm/translate-sme.c diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f0970c6b8c..789b6e8e78 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -146,6 +146,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) } bool disas_sve(DisasContext *, uint32_t); +bool disas_sme(DisasContext *, uint32_t); void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); diff --git a/target/arm/sme.decode b/target/arm/sme.decode new file mode 100644 index 0000000000..c25c031a71 --- /dev/null +++ b/target/arm/sme.decode @@ -0,0 +1,20 @@ +# AArch64 SME instruction descriptions +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b1d2840819..8a38fbc33b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14814,7 +14814,12 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ + case 0x0: + if (!disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; case 0x2: diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c new file mode 100644 index 0000000000..786c93fb2d --- /dev/null +++ b/target/arm/translate-sme.c @@ -0,0 +1,35 @@ +/* + * AArch64 SME translation + * + * Copyright (c) 2022 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-gvec-desc.h" +#include "translate.h" +#include "exec/helper-gen.h" +#include "translate-a64.h" +#include "fpu/softfloat.h" + + +/* + * Include the generated decoder. + */ + +#include "decode-sme.c.inc" diff --git a/target/arm/meson.build b/target/arm/meson.build index 02c91f72bb..c47d86c609 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,5 +1,6 @@ gen = [ decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), + decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), @@ -50,6 +51,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sme_helper.c', 'translate-a64.c', 'translate-sve.c', + 'translate-sme.c', )) arm_softmmu_ss = ss.source_set() From patchwork Thu Jun 2 21:48:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vx6g0IZu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgfs4cQrz9s0w for ; Fri, 3 Jun 2022 08:29:25 +1000 (AEST) Received: from localhost ([::1]:57662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtJj-0004Ni-Lz for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:29:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsk9-0001IX-3V for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:37 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:53078) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk5-0000ro-Bd for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:35 -0400 Received: by mail-pj1-x1034.google.com with SMTP id gd1so6030206pjb.2 for ; Thu, 02 Jun 2022 14:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=orbPdGKIoXyfvbiJ9veEa2tppV+gjslAnbSW8+tgomc=; b=vx6g0IZudHgJI9GRs8sMX0oX432N84HoW4nk5z/PV+n0SmlIrzIc1e6BvB5xm6hGF/ ZuPuWMgreV97MSx8qwZiuYueqXQGrzgjLET0B+7GgnOsUiy6NHBAEdJn+z3RQsvHwaHv k5okSifveyL+cSSoyheJ0F21TROuyxtXrnIUzqLq5OdD1qrlnvYv62aP74FvTHGcnhVI ZmWVq1mfUD60CSC3I+VEWWb5I/1Oyri7JRfMNhz4JbY2JPpq0uSUfVpu6BpHDORbY9Zd NV/LnxAU/F3yUT6CGzpAgY8Uy6/J1n1UF+QKTSM5FkBYDxyeg7ycIE6Hkol4TMBPHG0j 2/IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=orbPdGKIoXyfvbiJ9veEa2tppV+gjslAnbSW8+tgomc=; b=HXqgYm6+92J7eh9HPYxv8aX6Alne9mvQnUbljH7CyrdkvffPHFOOVnFXSMMNdw+FUd Hs8/mrWaeCRmHu22VzoapLFqH6y6m7GJdKsICDDGfS+bBhoSf4sgGkTQ5BvxD2eOb0av E0laC2B/+6EzsbQ3bC9Hc38SWe4iDEdbSPGUMB3vW0M/5Tu13lR4jvAy0iIGrJOewroI 034RAU+xlgZUczgYV7I+rLRhJ9czT6YohqcXXMbyjnAsAzlwNBECEQrSgDRGCtgXROzd jW/eoPxsrT4yIRpQ37HubjMyddA0wZJ3n6PUI47x6rB59jFjmuw+Dw2K+ats8/uDlAyw 2MBA== X-Gm-Message-State: AOAM533E4qEdgcGf8uSxkk8adjE+WEofT5p2ippssyZFWGQg9Jr1+Njx 9HDOLqJbJMEQhxvZCEAOXF4tRU6u7Yehcw== X-Google-Smtp-Source: ABdhPJwfBhThBYhlBSbtppTSTfzW0t5yzw2HlD0z0Qx6uS2YZcyqo1hiT9STGdjb5f94/5JhEct5lQ== X-Received: by 2002:a17:903:120e:b0:15e:84d2:4bbb with SMTP id l14-20020a170903120e00b0015e84d24bbbmr6686666plh.165.1654206751872; Thu, 02 Jun 2022 14:52:31 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 42/71] target/arm: Trap AdvSIMD usage when Streaming SVE is active Date: Thu, 2 Jun 2022 14:48:24 -0700 Message-Id: <20220602214853.496211-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_SIMD is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++ target/arm/translate.h | 3 ++ target/arm/sme-fa64.decode | 89 ++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 42 ++++++++++++++++++ target/arm/translate-a64.c | 41 +++++++++++++++++- target/arm/translate-vfp.c | 13 ++++++ target/arm/translate.c | 1 + target/arm/meson.build | 1 + 8 files changed, 194 insertions(+), 2 deletions(-) create mode 100644 target/arm/sme-fa64.decode diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c32c3afaa..899ecb7c82 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3256,6 +3256,11 @@ FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 10, 1) +/* + * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. + * This requires an SME trap from AArch32 mode when using NEON. + */ +FIELD(TBFLAG_A32, SME_TRAP_SIMD, 11, 1) /* * Bit usage when in AArch32 state, for M-profile only. @@ -3293,6 +3298,7 @@ FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) FIELD(TBFLAG_A64, SVL, 24, 4) +FIELD(TBFLAG_A64, SME_TRAP_SIMD, 28, 1) /* * Helpers for using the above. diff --git a/target/arm/translate.h b/target/arm/translate.h index 1330281f8b..775297aa40 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -106,6 +106,9 @@ typedef struct DisasContext { bool pstate_sm; /* True if PSTATE.ZA is set. */ bool pstate_za; + /* True if AdvSIMD insns should raise an SME Streaming exception. */ + bool sme_trap_simd; + bool sme_trap_this_insn; /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ bool mve_no_pred; /* diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode new file mode 100644 index 0000000000..4c2569477d --- /dev/null +++ b/target/arm/sme-fa64.decode @@ -0,0 +1,89 @@ +# AArch64 SME allowed instruction decoding +# +# Copyright (c) 2022 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +# These patterns are taken from Appendix E1.1 of DDI0616 A.a, +# Arm Architecture Reference Manual Supplement, +# The Scalable Matrix Extension (SME), for Armv9-A + +{ + [ + OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] + OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] + OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] + OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] + OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] + OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] + OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] + ] + FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations +} + +{ + [ + OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar) + OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16) + OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar) + OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16) + ] + FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations +} + +FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store +FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions + +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions +# We don't actually need to include these, as the default is OK. +# -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations +# --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers +# --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal) +# --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) +# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) +# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm) + +FAIL 0000 0100 --1- ---- 1010 ---- ---- ---- # ADR +FAIL 0000 0100 --1- ---- 1011 -0-- ---- ---- # FTSSEL, FEXPA +FAIL 0000 0101 --10 0001 100- ---- ---- ---- # COMPACT +FAIL 0010 0101 --01 100- 1111 000- ---0 ---- # RDFFR, RDFFRS +FAIL 0010 0101 --10 1--- 1001 ---- ---- ---- # WRFFR, SETFFR +FAIL 0100 0101 --0- ---- 1011 ---- ---- ---- # BDEP, BEXT, BGRP +FAIL 0100 0101 000- ---- 0110 1--- ---- ---- # PMULLB, PMULLT (128b result) +FAIL 0110 0100 --1- ---- 1110 01-- ---- ---- # FMMLA, BFMMLA +FAIL 0110 0101 --0- ---- 0000 11-- ---- ---- # FTSMUL +FAIL 0110 0101 --01 0--- 100- ---- ---- ---- # FTMAD +FAIL 0110 0101 --01 1--- 001- ---- ---- ---- # FADDA +FAIL 0100 0101 --0- ---- 1001 10-- ---- ---- # SMMLA, UMMLA, USMMLA +FAIL 0100 0101 --1- ---- 1--- ---- ---- ---- # SVE2 string/histo/crypto instructions +FAIL 1000 010- -00- ---- 10-- ---- ---- ---- # SVE2 32-bit gather NT load (vector+scalar) +FAIL 1000 010- -00- ---- 111- ---- ---- ---- # SVE 32-bit gather prefetch (vector+imm) +FAIL 1000 0100 0-1- ---- 0--- ---- ---- ---- # SVE 32-bit gather prefetch (scalar+vector) +FAIL 1000 010- -01- ---- 1--- ---- ---- ---- # SVE 32-bit gather load (vector+imm) +FAIL 1000 0100 0-0- ---- 0--- ---- ---- ---- # SVE 32-bit gather load byte (scalar+vector) +FAIL 1000 0100 1--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load half (scalar+vector) +FAIL 1000 0101 0--- ---- 0--- ---- ---- ---- # SVE 32-bit gather load word (scalar+vector) +FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar) +FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm) +FAIL 1010 010- -10- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar) +FAIL 1010 010- -100 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm) +FAIL 1100 010- ---- ---- ---- ---- ---- ---- # SVE 64-bit gather load/prefetch +FAIL 1110 010- -00- ---- 001- ---- ---- ---- # SVE2 64-bit scatter NT store (vector+scalar) +FAIL 1110 010- -10- ---- 001- ---- ---- ---- # SVE2 32-bit scatter NT store (vector+scalar) +FAIL 1110 010- ---- ---- 1-0- ---- ---- ---- # SVE scatter store (scalar+32-bit vector) +FAIL 1110 010- ---- ---- 101- ---- ---- ---- # SVE scatter store (misc) diff --git a/target/arm/helper.c b/target/arm/helper.c index c9db12d524..7396be4352 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6273,6 +6273,32 @@ int sme_exception_el(CPUARMState *env, int el) return 0; } +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ +static bool sme_fa64(CPUARMState *env, int el) +{ + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { + return false; + } + + if (el <= 1 && !el_is_in_host(env, el)) { + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { + return false; + } + } + if (el <= 2 && arm_is_el2_enabled(env)) { + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { + return false; + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { + return false; + } + } + + return true; +} + /* * Given that SVE is enabled, return the vector length for EL. */ @@ -13834,6 +13860,21 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, DP_TBFLAG_ANY(flags, PSTATE__IL, 1); } + /* + * The SME exception we are testing for is raised via + * AArch64.CheckFPAdvSIMDEnabled(), and for AArch32 this is called + * when EL1 is using A64 or EL2 using A64 and !TGE. + * See AArch32.CheckAdvSIMDOrFPEnabled(). + */ + if (el == 0 + && FIELD_EX64(env->svcr, SVCR, SM) + && (!arm_is_el2_enabled(env) + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) + && arm_el_is_aa64(env, 1) + && !sme_fa64(env, el)) { + DP_TBFLAG_A32(flags, SME_TRAP_SIMD, 1); + } + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -13883,6 +13924,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } if (FIELD_EX64(env->svcr, SVCR, SM)) { DP_TBFLAG_A64(flags, PSTATE_SM, 1); + DP_TBFLAG_A64(flags, SME_TRAP_SIMD, !sme_fa64(env, el)); } DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a38fbc33b..029c0a917c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1155,7 +1155,7 @@ static void do_vec_ld(DisasContext *s, int destidx, int element, * unallocated-encoding checks (otherwise the syndrome information * for the resulting exception will be incorrect). */ -static bool fp_access_check(DisasContext *s) +static bool fp_access_check_only(DisasContext *s) { if (s->fp_excp_el) { assert(!s->fp_access_checked); @@ -1169,6 +1169,20 @@ static bool fp_access_check(DisasContext *s) return true; } +static bool fp_access_check(DisasContext *s) +{ + if (!fp_access_check_only(s)) { + return false; + } + if (s->sme_trap_this_insn) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, false), + default_exception_el(s)); + return false; + } + return true; +} + /* Check that SVE access is enabled. If it is, return true. * If not, emit code to generate an appropriate exception and return false. */ @@ -1994,7 +2008,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, default: g_assert_not_reached(); } - if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { + if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { return; @@ -14530,6 +14544,23 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) } } +/* + * Include the generated SME FA64 decoder. + */ + +#include "decode-sme-fa64.c.inc" + +static bool trans_OK(DisasContext *s, arg_OK *a) +{ + return true; +} + +static bool trans_FAIL(DisasContext *s, arg_OK *a) +{ + s->sme_trap_this_insn = true; + return true; +} + /** * is_guarded_page: * @env: The cpu environment @@ -14662,6 +14693,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA); + dc->sme_trap_simd = EX_TBFLAG_A64(tb_flags, SME_TRAP_SIMD); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; @@ -14813,6 +14845,11 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } } + if (s->sme_trap_simd) { + s->sme_trap_this_insn = false; + disas_sme_fa64(s, insn); + } + switch (extract32(insn, 25, 4)) { case 0x0: if (!disas_sme(s, insn)) { diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 40a513b822..476868622f 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -224,6 +224,19 @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) return false; } + /* + * Note that rebuild_hflags_a32 has already accounted for being in EL0 + * and the higher EL in A64 mode, etc. Unlike A64 mode, there do not + * appear to be any insns which touch VFP which are allowed. + */ + if (s->sme_trap_simd) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_Streaming, + s->base.pc_next - s->pc_curr == 2), + default_exception_el(s)); + return false; + } + if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 87a899d638..a286024bad 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9365,6 +9365,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN); dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE); } + dc->sme_trap_simd = EX_TBFLAG_A32(tb_flags, SME_TRAP_SIMD); } dc->cp_regs = cpu->cp_regs; dc->features = env->features; diff --git a/target/arm/meson.build b/target/arm/meson.build index c47d86c609..07bd9f3c0f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ gen = [ decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), + decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'), decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), From patchwork Thu Jun 2 21:48:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=YdFphnRl; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgWP48Mcz9s0w for ; Fri, 3 Jun 2022 08:22:57 +1000 (AEST) Received: from localhost ([::1]:37950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtDT-0007rV-LD for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:22:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwsk9-0001IO-31 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:37 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:53079) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk6-0000s0-0D for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:36 -0400 Received: by mail-pj1-x1035.google.com with SMTP id gd1so6030225pjb.2 for ; Thu, 02 Jun 2022 14:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kOf3bIlPmmzxnCo3oo6dl2Yq5IfQQ5VBzpADjTzwQdM=; b=YdFphnRlGHxBWuiWUjrcCe6DV8Kydbww5mcgMeo3Iy0bLrf7SA5ffCA/dyeEttwrfQ 8G/5aM0IykSrgtpBYdFpyxVFLJhR0ONq9jCbHgZ5RfMUB17veC+g3CntOOA6EdDX+Zev N1dSuq15jA8IdlEJKh2Tf2mUZgRXruOvWgnAQnRfAa5UnMFAFAsPqA6TKWTvqzgOU78r hpNVj4x4e15sAXNMo2H407FEpFTPByUT3ToUoFv787iXJBTCEfO6egfTDFY2oVmpElJT lz5gGq5ah1XLAp+e+f9SCFHGDYZ8YC4KPD+NI/GjZvMtLD4sikuR9u7PiCwaGIBm2rOX PJWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kOf3bIlPmmzxnCo3oo6dl2Yq5IfQQ5VBzpADjTzwQdM=; b=OX1Q4aKaiHwTrvxGlMeuQ1sO3ueL55oEBfHcJffhFjL78kaKhujzCIRXf0vMpBq0jo yrUljsWYU/yHdO52uSNzEMbwaolUQ3XJq/r3mgk/dO7maE8jkuPg0o7rg1eNvC0FJF6O WEJfUf2WAOsUMD91V7kwfxyZVR25sApsH2wwM9KSqK0/BvPeXP/nQh7mzYfFjDftIdPI 5kqOQs+jPg3mAJDSLpKQDblm7TIyHv26QIYsIJnSQYwBm5w5CzUcG7M7VpAEz+WOHhqG /KXKxG77JXKpiRFZAh7EbWGPxNDpjoQZBeE/CJjD6BVIh5m0eSOVRNqxwlGdc674wh6f Escg== X-Gm-Message-State: AOAM530K3cBFYC977dDYhL0qIXrbLg/oeAhRwhw41a4sTSt7pGzfIc5P bCYpugETvhz8/pMy2JRogDqTZXn792HvJQ== X-Google-Smtp-Source: ABdhPJyoI9WdFiLkKoY5UL6t9FTFB95sffVS3Tf08uyWgqG3MZhb02SxciKfSbOYpeAEU+iTHGHiog== X-Received: by 2002:a17:90b:1a81:b0:1e0:3314:2447 with SMTP id ng1-20020a17090b1a8100b001e033142447mr41781599pjb.121.1654206752672; Thu, 02 Jun 2022 14:52:32 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 43/71] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL Date: Thu, 2 Jun 2022 14:48:25 -0700 Message-Id: <20220602214853.496211-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 1 + target/arm/sve.decode | 5 ++++- target/arm/translate-a64.c | 15 +++++++++++++++ target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 789b6e8e78..6bd1b2eb4b 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -29,6 +29,7 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +bool sme_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/sve.decode b/target/arm/sve.decode index a54feb2f61..bbdaac6ac7 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 ### SVE Bitwise Shift - Unpredicated Group diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 029c0a917c..222f93d42d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1216,6 +1216,21 @@ static bool sme_access_check(DisasContext *s) return true; } +/* Note that this function corresponds to CheckSMEEnabled. */ +bool sme_enabled_check(DisasContext *s) +{ + /* + * Note that unlike sve_excp_el, we have not constrained sme_excp_el + * to be zero when fp_excp_el has priority. This is because we need + * sme_excp_el by itself for cpregs access checks. + */ + if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) { + s->fp_access_checked = true; + return sme_access_check(s); + } + return fp_access_check_only(s); +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 62b5f3040c..13bdd027a5 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) return true; } +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * s->svl); + } + return true; +} + static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) return true; } +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 rd = cpu_reg_sp(s, a->rd); + TCGv_i64 rn = cpu_reg_sp(s, a->rn); + tcg_gen_addi_i64(rd, rn, a->imm * (s->svl / 8)); + } + return true; +} + static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { if (!dc_isar_feature(aa64_sve, s)) { @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a) return true; } +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_enabled_check(s)) { + TCGv_i64 reg = cpu_reg(s, a->rd); + tcg_gen_movi_i64(reg, a->imm * s->svl); + } + return true; +} + /* *** SVE Compute Vector Address Group */ From patchwork Thu Jun 2 21:48:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Ug29dcRh; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgxM3dv1z9s0w for ; Fri, 3 Jun 2022 08:41:59 +1000 (AEST) Received: from localhost ([::1]:56262 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtVs-00060H-9s for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:41:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38280) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskD-0001Un-2H for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:41 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:45587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk8-0000sL-MT for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:40 -0400 Received: by mail-pl1-x62c.google.com with SMTP id q18so5509233pln.12 for ; Thu, 02 Jun 2022 14:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s3jNY3UkHfmIkcwzioHwZsMLqfT+fqIVUcaYJ3PqXa4=; b=Ug29dcRh+NQvOHPfisITUC11YFeXMnhVV2YnflbwhY/tkYv8AHsuEnU85lT6TMttem uuUOqU0feSicrJH1WUjwsTAWQIo7GXmpvISY2PgYZcIb7Lx/gAmdYFsuFdqyM7SufJyQ hdPD4gFApphD46l/snmrA6XEvHCmnb4DgFLD3cjx9VXvD0Wp6QvncN3AJhWluEO197S+ wvginT5YFdOv2o+FED4VMjtqKYxRVPZZJCyantLiUxN/BqSezHxJFL5AnzGAMh9Pgyb6 TjabZz3+XnmrzBu/qcY/1ENlLVKG2Yn939PFrG+vRXx/t3wrd2RcHnIEE8f3OESYkcCY A+4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s3jNY3UkHfmIkcwzioHwZsMLqfT+fqIVUcaYJ3PqXa4=; b=4SHRCUyeCTE7LamvAxz3x9F/CYM1QCtrYOZX/SiYfzHn1duL0qBa/Tld5VNm7lAIcY KTg3VJTWIjkvGqMJ+IC9t6yMSKvZ0XZysO3Jb+lSDzXeJoXb1tq6toWVofFqgLlNiJut Vl70m7TCyJJz/eLp6C0gHEtdGy8PZy6JDdmWnlH7XAghaaj0sbjlvo4c9M2nU3Vvfxx1 W/YQyzfVHGZ7j6J/gN7CAu3iYl+qk0bacUuzcLy+w1kTd4QEe8LGI2DxRRWu2vM7f45X nvHcinNmHQd8Wix1Jxkbcqo9OXGrQKxF/K8jjpsd3hG0at1gSm38+8pXMyy2bno7pgn1 xSUQ== X-Gm-Message-State: AOAM533y8E2JjaF8NtEcJkqZyTYPfShZRMCs6RWLblfJc4tS4tma/k59 Xpo1zWFgkqOJT2dfMhl9JDObFBwojuBoyA== X-Google-Smtp-Source: ABdhPJyOXYj7sIeCmZ7KqhyFkMzalvmywISHy7PrmAcL1Mx+zgZqFw/+NGQCk73YuVp6nZFuoyh2qA== X-Received: by 2002:a17:90b:1642:b0:1e0:96b:c3f2 with SMTP id il2-20020a17090b164200b001e0096bc3f2mr7543108pjb.228.1654206753432; Thu, 02 Jun 2022 14:52:33 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 44/71] target/arm: Implement SME ZERO Date: Thu, 2 Jun 2022 14:48:26 -0700 Message-Id: <20220602214853.496211-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/translate-a64.h | 1 + target/arm/sme.decode | 4 ++++ target/arm/sme_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-a64.c | 15 +++++++++++++++ target/arm/translate-sme.c | 13 +++++++++++++ 6 files changed, 60 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 3bd48c235f..c4ee1f09e4 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -19,3 +19,5 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) + +DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 6bd1b2eb4b..ec5d580ba0 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -30,6 +30,7 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); +bool sme_za_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); diff --git a/target/arm/sme.decode b/target/arm/sme.decode index c25c031a71..6e4483fdce 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -18,3 +18,7 @@ # # This file is processed by scripts/decodetree.py # + +### SME Misc + +ZERO 11000000 00 001 00000000000 imm:8 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index c34d1b2e6b..4172b788f9 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -58,3 +58,28 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) memset(env->zarray, 0, sizeof(env->zarray)); } } + +void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) +{ + uint32_t i; + + /* + * Special case clearing the entire ZA space. + * This falls into the CONSTRAINED UNPREDICTABLE zeroing of any + * parts of the ZA storage outside of SVL. + */ + if (imm == 0xff) { + memset(env->zarray, 0, sizeof(env->zarray)); + return; + } + + /* + * Recall that ZAnH.D[m] is spread across ZA[n+8*m]. + * Unless SVL == ARM_MAX_VQ, each row is discontiguous. + */ + for (i = 0; i < svl; i++) { + if (imm & (1 << (i % 8))) { + memset(&env->zarray[i], 0, svl); + } + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 222f93d42d..660c5dbf5b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1231,6 +1231,21 @@ bool sme_enabled_check(DisasContext *s) return fp_access_check_only(s); } +/* Note that this function corresponds to CheckSMEAndZAEnabled. */ +bool sme_za_enabled_check(DisasContext *s) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (!s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false), + default_exception_el(s)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 786c93fb2d..d526c74456 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -33,3 +33,16 @@ */ #include "decode-sme.c.inc" + + +static bool trans_ZERO(DisasContext *s, arg_ZERO *a) +{ + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (sme_za_enabled_check(s)) { + gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + tcg_constant_i32(s->svl)); + } + return true; +} From patchwork Thu Jun 2 21:48:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Xwb9WB+n; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgp04HRJz9s0w for ; Fri, 3 Jun 2022 08:35:36 +1000 (AEST) Received: from localhost ([::1]:39226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtPg-0002i4-Rv for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:35:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38260) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskC-0001TT-LU for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:40 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:40598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk8-0000qT-Mk for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:40 -0400 Received: by mail-pj1-x1035.google.com with SMTP id n13-20020a17090a394d00b001e30a60f82dso10614059pjf.5 for ; Thu, 02 Jun 2022 14:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=POeVk+hfEvx7ltKdq2kmOTkuXQTiT662Cy9z7ypTMh0=; b=Xwb9WB+ntDolt1+5X0Tctwokhg2QmqTDTLmRhqP4htV20G7pMwB2302Z+WmRF9Oz2A +9XYDGGyLrX+HsDNNWNiU/M0lzdyEHSIDY/9xQMQ0pTVZQQf9r/uvcPBBRxCyowbhWZC 3vwa/fjLr2nTlMy5AWl3aXBO03Ov4R7a6YmbAjBpa6Uv0ynMIO0IYQG9g1YVl9PNVknP OyVlXhBfN+ugkpW/GYGLx+olaR2n05V2usZYDkVS4Sg6lHLPN8A57mgulBOh/ndSrBAz 467aCoGJeG0yntBFNreA5t0shry4ShuP5+g4Sds8La+hMLxqaBZh6hnfubo/i6XtmV4R dCpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=POeVk+hfEvx7ltKdq2kmOTkuXQTiT662Cy9z7ypTMh0=; b=UtiU5p/RnOaCjS0qfqRlJf/blHlr5QNmnDNP4wSRNaXhqR9jDQijy2ZyAPKH/Jugdp iZwuv86tWaiOF7dNgcc3w/mVhNtzLTNVtyAbRXdZnCIHoboO17RisYb0YisYt2x5kEVy 2r5diEJHbaB0NXghzRjLpSBBBbZ+FT1yM/h8QBsll+pdm/X7ozr98snZBqHiOhDaXoWh Cfvka9U9uaXs5z8DFBXOeabP0+VZKgLcZV1QNp6dMh8CXb06nWmX9Qoz2cLywqe8qQsZ e4mWVcdLYdt5AzYts2ENM5KAeKb2YT+6aJJgPTWd3CIO7gCc1ujvcXGu9TTJC3IP12/c NPuw== X-Gm-Message-State: AOAM5313K9k5dW+/OH8LHUf55bjU6qnShWxW1KGauRO2NcogXT0J9Xje KCHsFdryecg7x4z1aAJ6N/Dlrlu3mARL4A== X-Google-Smtp-Source: ABdhPJzk1qVuw2bW9keoYc/oBACw166SZ3465Zue2FExdZkoE4Xh/ZNFtCUitbPrm+AwEsB7G6Yleg== X-Received: by 2002:a17:903:485:b0:163:e1be:52b3 with SMTP id jj5-20020a170903048500b00163e1be52b3mr6790785plb.134.1654206754301; Thu, 02 Jun 2022 14:52:34 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 45/71] target/arm: Implement SME MOVA Date: Thu, 2 Jun 2022 14:48:27 -0700 Message-Id: <20220602214853.496211-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We can reuse the SVE functions for implementing moves to/from horizontal tile slices, but we need new ones for moves to/from vertical tile slices. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 11 ++++ target/arm/helper-sve.h | 2 + target/arm/translate-a64.h | 9 +++ target/arm/translate.h | 5 ++ target/arm/sme.decode | 15 +++++ target/arm/sme_helper.c | 110 ++++++++++++++++++++++++++++++++++++- target/arm/sve_helper.c | 12 ++++ target/arm/translate-a64.c | 21 +++++++ target/arm/translate-sme.c | 105 +++++++++++++++++++++++++++++++++++ 9 files changed, 289 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index c4ee1f09e4..600346e08c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -21,3 +21,14 @@ DEF_HELPER_FLAGS_2(set_pstate_sm, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(set_pstate_za, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_3(sme_zero, TCG_CALL_NO_RWG, void, env, i32, i32) + +DEF_HELPER_FLAGS_4(sme_mova_avz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zav_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_avz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zav_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_avz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zav_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_avz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zav_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_avz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_mova_zav_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index dc629f851a..ab0333400f 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -325,6 +325,8 @@ DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_sel_zpzz_q, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_addp_zpzz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index ec5d580ba0..c341c95582 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -31,6 +31,7 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, bool sve_access_check(DisasContext *s); bool sme_enabled_check(DisasContext *s); bool sme_za_enabled_check(DisasContext *s); +bool sme_smza_enabled_check(DisasContext *s); TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int log2_size); @@ -147,6 +148,14 @@ static inline int pred_gvec_reg_size(DisasContext *s) return size_for_gvec(pred_full_reg_size(s)); } +/* Return a newly allocated pointer to the predicate register. */ +static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + return ret; +} + bool disas_sve(DisasContext *, uint32_t); bool disas_sme(DisasContext *, uint32_t); diff --git a/target/arm/translate.h b/target/arm/translate.h index 775297aa40..d03afd0034 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -159,6 +159,11 @@ static inline int plus_2(DisasContext *s, int x) return x + 2; } +static inline int plus_12(DisasContext *s, int x) +{ + return x + 12; +} + static inline int times_2(DisasContext *s, int x) { return x * 2; diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 6e4483fdce..241b4895b7 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -22,3 +22,18 @@ ### SME Misc ZERO 11000000 00 001 00000000000 imm:8 + +### SME Move into/from Array + +%mova_rs 13:2 !function=plus_12 +&mova esz rs pg zr za_imm v:bool to_vec:bool + +MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=0 rs=%mova_rs +MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \ + &mova to_vec=0 rs=%mova_rs esz=4 + +MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=1 rs=%mova_rs +MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ + &mova to_vec=1 rs=%mova_rs esz=4 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 4172b788f9..8b73474eb0 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,8 +19,10 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" +#include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "qemu/int128.h" +#include "vec_internal.h" /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -83,3 +85,109 @@ void helper_sme_zero(CPUARMState *env, uint32_t imm, uint32_t svl) } } } + +#define DO_MOVA_A(NAME, TYPE, H) \ +void HELPER(NAME)(void *za, void *vn, void *vg, uint32_t desc) \ +{ \ + int i, oprsz = simd_oprsz(desc); \ + for (i = 0; i < oprsz; ) { \ + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)za = *(TYPE *)(vn + H(i)); \ + } \ + za += sizeof(ARMVectorReg) * sizeof(TYPE); \ + i += sizeof(TYPE); \ + pg >>= sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +#define DO_MOVA_Z(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *za, void *vg, uint32_t desc) \ +{ \ + int i, oprsz = simd_oprsz(desc); \ + for (i = 0; i < oprsz; ) { \ + uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ + do { \ + if (pg & 1) { \ + *(TYPE *)(vd + H(i)) = *(TYPE *)za; \ + } \ + za += sizeof(ARMVectorReg) * sizeof(TYPE); \ + i += sizeof(TYPE); \ + pg >>= sizeof(TYPE); \ + } while (i & 15); \ + } \ +} + +DO_MOVA_A(sme_mova_avz_b, uint8_t, H1) +DO_MOVA_A(sme_mova_avz_h, uint16_t, H2) +DO_MOVA_A(sme_mova_avz_s, uint32_t, H4) + +DO_MOVA_Z(sme_mova_zav_b, uint8_t, H1) +DO_MOVA_Z(sme_mova_zav_h, uint16_t, H2) +DO_MOVA_Z(sme_mova_zav_s, uint32_t, H4) + +void HELPER(sme_mova_avz_d)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 8; + uint8_t *pg = vg; + uint64_t *n = vn; + uint64_t *a = za; + + /* + * Note that the rows of the ZAV.D tile are 8 absolute rows apart, + * so while the address arithmetic below looks funny, it is right. + */ + for (i = 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] = n[i]; + } + } +} + +void HELPER(sme_mova_zav_d)(void *vd, void *za, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 8; + uint8_t *pg = vg; + uint64_t *d = vd; + uint64_t *a = za; + + for (i = 0; i < oprsz; i++) { + if (pg[H1_2(i)] & 1) { + d[i] = a[i * sizeof(ARMVectorReg)]; + } + } +} + +void HELPER(sme_mova_avz_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 16; + uint16_t *pg = vg; + Int128 *n = vn; + Int128 *a = za; + + /* + * Note that the rows of the ZAV.Q tile are 16 absolute rows apart, + * so while the address arithmetic below looks funny, it is right. + */ + for (i = 0; i < oprsz; i++) { + if (pg[H2(i)] & 1) { + a[i * sizeof(ARMVectorReg)] = n[i]; + } + } +} + +void HELPER(sme_mova_zav_q)(void *za, void *vn, void *vg, uint32_t desc) +{ + int i, oprsz = simd_oprsz(desc) / 16; + uint16_t *pg = vg; + Int128 *n = vn; + Int128 *a = za; + + for (i = 0; i < oprsz; i++, za += sizeof(ARMVectorReg)) { + if (pg[H2(i)] & 1) { + n[i] = a[i * sizeof(ARMVectorReg)]; + } + } +} diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 1654c0bbf9..9a26f253e0 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3565,6 +3565,18 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm, } } +void HELPER(sve_sel_zpzz_q)(void *vd, void *vn, void *vm, + void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 16; + Int128 *d = vd, *n = vn, *m = vm; + uint16_t *pg = vg; + + for (i = 0; i < opr_sz; i += 1) { + d[i] = (pg[H2(i)] & 1 ? n : m)[i]; + } +} + /* Two operand comparison controlled by a predicate. * ??? It is very tempting to want to be able to expand this inline * with x86 instructions, e.g. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 660c5dbf5b..2b4baa2684 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1246,6 +1246,27 @@ bool sme_za_enabled_check(DisasContext *s) return true; } +/* Note that this function corresponds to CheckStreamingSVEAndZAEnabled. */ +bool sme_smza_enabled_check(DisasContext *s) +{ + if (!sme_enabled_check(s)) { + return false; + } + if (!s->pstate_sm) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_NotStreaming, false), + default_exception_el(s)); + return false; + } + if (!s->pstate_za) { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_smetrap(SME_ET_InactiveZA, false), + default_exception_el(s)); + return false; + } + return true; +} + /* * This utility function is for doing register extension with an * optional shift. You will likely want to pass a temporary for the diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d526c74456..d2a7232491 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -35,6 +35,54 @@ #include "decode-sme.c.inc" +static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, + int tile_index, bool vertical) +{ + int tile = tile_index >> (4 - esz); + int index = esz == MO_128 ? 0 : extract32(tile_index, 0, 4 - esz); + int pos, len, offset; + TCGv_i32 t_index; + TCGv_ptr addr; + + /* Resolve tile.size[index] to an untyped ZA slice index. */ + t_index = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(t_index, cpu_reg(s, rs)); + tcg_gen_addi_i32(t_index, t_index, index); + + len = ctz32(s->svl) - esz; + pos = esz; + offset = tile; + + /* + * Horizontal slice. Index row N, column 0. + * The helper will iterate by the element size. + */ + if (!vertical) { + pos += ctz32(sizeof(ARMVectorReg)); + offset *= sizeof(ARMVectorReg); + } + offset += offsetof(CPUARMState, zarray); + + tcg_gen_deposit_z_i32(t_index, t_index, pos, len); + tcg_gen_addi_i32(t_index, t_index, offset); + + /* + * Vertical tile slice. Index row 0, column N. + * The helper will iterate by the row spacing in the array. + * Need to adjust addressing for elements smaller than uint64_t for BE. + */ + if (HOST_BIG_ENDIAN && vertical && esz < MO_64) { + tcg_gen_xori_i32(t_index, t_index, 8 - (1 << esz)); + } + + addr = tcg_temp_new_ptr(); + tcg_gen_ext_i32_ptr(addr, t_index); + tcg_temp_free_i32(t_index); + tcg_gen_add_ptr(addr, addr, cpu_env); + + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -46,3 +94,60 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) } return true; } + +static bool trans_MOVA(DisasContext *s, arg_MOVA *a) +{ + static gen_helper_gvec_4 * const h_fns[5] = { + gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h, + gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d, + gen_helper_sve_sel_zpzz_q + }; + static gen_helper_gvec_3 * const avz_fns[5] = { + gen_helper_sme_mova_avz_b, gen_helper_sme_mova_avz_h, + gen_helper_sme_mova_avz_s, gen_helper_sme_mova_avz_d, + gen_helper_sme_mova_avz_q, + }; + static gen_helper_gvec_3 * const zav_fns[5] = { + gen_helper_sme_mova_zav_b, gen_helper_sme_mova_zav_h, + gen_helper_sme_mova_zav_s, gen_helper_sme_mova_zav_d, + gen_helper_sme_mova_zav_q, + }; + + TCGv_ptr t_za, t_zr, t_pg; + TCGv_i32 t_desc; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_zr = vec_full_reg_ptr(s, a->zr); + t_pg = pred_full_reg_ptr(s, a->pg); + + t_desc = tcg_constant_i32(simd_desc(s->svl, s->svl, 0)); + + if (a->v) { + /* Vertical slice -- use sme mova helpers. */ + if (a->to_vec) { + zav_fns[a->esz](t_za, t_zr, t_pg, t_desc); + } else { + avz_fns[a->esz](t_zr, t_za, t_pg, t_desc); + } + } else { + /* Horizontal slice -- reuse sve sel helpers. */ + if (a->to_vec) { + h_fns[a->esz](t_zr, t_za, t_zr, t_pg, t_desc); + } else { + h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); + } + } + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_zr); + tcg_temp_free_ptr(t_pg); + + return true; +} From patchwork Thu Jun 2 21:48:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638512 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ozilF+ub; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh1466CNz9s0w for ; Fri, 3 Jun 2022 08:45:11 +1000 (AEST) Received: from localhost ([::1]:37930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtYy-00047E-5K for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:45:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskE-0001b0-TK for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:43 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:45784) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwsk8-0000sf-Ru for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:42 -0400 Received: by mail-pj1-x1031.google.com with SMTP id w2-20020a17090ac98200b001e0519fe5a8so5873444pjt.4 for ; Thu, 02 Jun 2022 14:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5ZzL8eNwZ6dBHRMmV56sbr0xTmiAeYrckiJr08uE6wo=; b=ozilF+ub4zkh/ZUjyHsF9Z4ggyWQh/dcfqF2pKsLdkTzxMaL1jXmhBYigOcvz52xXI zAMElZHN0mQNP0b9w4FuncPAyqt2o1n4KmKkEVdWjiGtY1L3JJnxugpZ26ly0A3WuqbC Ho8v0oHo2SBY/vfmvm95p+MsrqKbDKLRRNPrkYQ26xOFzBctd+QLhhsNPB9ji+raGBZJ mJH0MlZq93SkRhIPvzsoLVSGxRl1b/DCg4091or1wNfKPwl9LWEuJP2fkvAwvisbR7To aeFmDOsm9we7gyTI2nMqCYjJiIwVksmI3FzgC81PmTzmV+Kwk7ee0EHZM+eDvhF3RDcn rLPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5ZzL8eNwZ6dBHRMmV56sbr0xTmiAeYrckiJr08uE6wo=; b=oSUHMysPAMMP83xGbASD95AIqc8XsTKSs8EFtNLRnsSrJqFn3qBS+uOf0UF2gzcobe tUHB+uUtgzgE1l5D11+HKy9LKg3XJBf33cBE7dVmiRKqaYzbdbtnPJsgxXu82hNPL+h6 2vuZEiLI4qcjgyTpVTFyq9hrXZ934MaBXJND3+apOYLpiNCdnTwE6+j/LJqP/S79BZy0 Cz4NvjepE/jI4/fv1xB8zEycESbfHTSdLfHKeO/U8fCWDpKkETF8PmpCQ9+u3bWmdBN0 ivCpWLaAw+RDLAk7xhl4otLEbh5DaPKjPdMRDIQQW5mPszBcp/TPqnohsAbmM84Cwzy7 PBcQ== X-Gm-Message-State: AOAM532mOnR7zW3bOIfYjrWpi5MXySqu0rqu5/J1OMrup13vh53wWbhX ew/rt8CbMwDYT2ItvXHNBJdc7wcv8FPJWA== X-Google-Smtp-Source: ABdhPJzsbCu+jtMKdpWfcrBCpiiLMywvkBvGtP0Xp80TRfNVNM/tQpX2atSK/iXskLNJgSBznbHtsA== X-Received: by 2002:a17:90a:df91:b0:1e3:4dc8:46e7 with SMTP id p17-20020a17090adf9100b001e34dc846e7mr14516162pjv.106.1654206755287; Thu, 02 Jun 2022 14:52:35 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 46/71] target/arm: Implement SME LD1, ST1 Date: Thu, 2 Jun 2022 14:48:28 -0700 Message-Id: <20220602214853.496211-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We cannot reuse the SVE functions for LD[1-4] and ST[1-4], because those functions accept only a Zreg register number. For SME, we want to pass a pointer into ZA storage. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 82 +++++ target/arm/sme.decode | 9 + target/arm/sme_helper.c | 615 +++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 69 +++++ 4 files changed, 775 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 600346e08c..5cca01f372 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -32,3 +32,85 @@ DEF_HELPER_FLAGS_4(sme_mova_avz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zav_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_avz_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sme_mova_zav_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sme_ld1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_ld1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_ld1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1b_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1b_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1h_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1h_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1s_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1s_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1d_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1d_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_st1q_be_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) +DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 241b4895b7..900e3f2a07 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -37,3 +37,12 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=1 rs=%mova_rs MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \ &mova to_vec=1 rs=%mova_rs esz=4 + +### SME Memory + +&ldst esz rs pg rn rm za_imm v:bool st:bool + +LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst rs=%mova_rs +LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ + &ldst esz=4 rs=%mova_rs diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 8b73474eb0..b32c8435cb 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -19,10 +19,14 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" #include "qemu/int128.h" #include "vec_internal.h" +#include "sve_ldst_internal.h" /* ResetSVEState */ void arm_reset_sve_state(CPUARMState *env) @@ -191,3 +195,614 @@ void HELPER(sme_mova_zav_q)(void *za, void *vn, void *vg, uint32_t desc) } } } + +/* + * Clear elements in a tile slice comprising len bytes. + */ + +typedef void ClearFn(void *ptr, size_t off, size_t len); + +static void clear_horizontal(void *ptr, size_t off, size_t len) +{ + memset(ptr + off, 0, len); +} + +static void clear_vertical_b(void *vptr, size_t off, size_t len) +{ + uint8_t *ptr = vptr; + size_t i; + + for (i = 0; i < len; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] = 0; + } +} + +static void clear_vertical_h(void *vptr, size_t off, size_t len) +{ + uint16_t *ptr = vptr; + size_t i; + + for (i = 0; i < len / 2; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] = 0; + } +} + +static void clear_vertical_s(void *vptr, size_t off, size_t len) +{ + uint32_t *ptr = vptr; + size_t i; + + for (i = 0; i < len / 4; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] = 0; + } +} + +static void clear_vertical_d(void *vptr, size_t off, size_t len) +{ + uint64_t *ptr = vptr; + size_t i; + + for (i = 0; i < len / 8; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] = 0; + } +} + +static void clear_vertical_q(void *vptr, size_t off, size_t len) +{ + Int128 *ptr = vptr, zero = int128_zero(); + size_t i; + + for (i = 0; i < len / 16; ++i) { + ptr[(i + off) * sizeof(ARMVectorReg)] = zero; + } +} + +/* + * Copy elements from an array into a tile slice comprising len bytes. + */ + +typedef void CopyFn(void *dst, const void *src, size_t len); + +static void copy_horizontal(void *dst, const void *src, size_t len) +{ + memcpy(dst, src, len); +} + +static void copy_vertical_b(void *vdst, const void *vsrc, size_t len) +{ + const uint8_t *src = vsrc; + uint8_t *dst = vdst; + size_t i; + + for (i = 0; i < len; ++i) { + dst[i * sizeof(ARMVectorReg)] = src[i]; + } +} + +static void copy_vertical_h(void *vdst, const void *vsrc, size_t len) +{ + const uint16_t *src = vsrc; + uint16_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 2; ++i) { + dst[i * sizeof(ARMVectorReg)] = src[i]; + } +} + +static void copy_vertical_s(void *vdst, const void *vsrc, size_t len) +{ + const uint32_t *src = vsrc; + uint32_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 4; ++i) { + dst[i * sizeof(ARMVectorReg)] = src[i]; + } +} + +static void copy_vertical_d(void *vdst, const void *vsrc, size_t len) +{ + const uint64_t *src = vsrc; + uint64_t *dst = vdst; + size_t i; + + for (i = 0; i < len / 8; ++i) { + dst[i * sizeof(ARMVectorReg)] = src[i]; + } +} + +static void copy_vertical_q(void *vdst, const void *vsrc, size_t len) +{ + const Int128 *src = vsrc; + Int128 *dst = vdst; + size_t i; + + for (i = 0; i < len / 16; ++i) { + dst[i * sizeof(ARMVectorReg)] = src[i]; + } +} + +/* + * Host and TLB primitives for vertical tile slice addressing. + */ + +#define DO_LD(NAME, TYPE, HOST, TLB) \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + TYPE val = HOST(host); \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \ +} \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ + intptr_t off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPE val = TLB(env, useronly_clean_ptr(addr), ra); \ + *(TYPE *)(za + off * sizeof(ARMVectorReg)) = val; \ +} + +#define DO_ST(NAME, TYPE, HOST, TLB) \ +static inline void sme_##NAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \ + HOST(host, val); \ +} \ +static inline void sme_##NAME##_v_tlb(CPUARMState *env, void *za, \ + intptr_t off, target_ulong addr, uintptr_t ra) \ +{ \ + TYPE val = *(TYPE *)(za + off * sizeof(ARMVectorReg)); \ + TLB(env, useronly_clean_ptr(addr), val, ra); \ +} + +/* + * FIXME: The ARMVectorReg elements are stored in host-endian 64-bit units. + * We do not have a defined ordering of the 64-bit units for host-endian + * 128-bit quantities. For now, just leave the host words in little-endian + * order and hope for the best. + */ +#define DO_LDQ(HNAME, VNAME, BE, HOST, TLB) \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ +{ \ + uint64_t val0 = HOST(host), val1 = HOST(host + 8); \ + uint64_t *ptr = za + off; \ + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ +} \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); \ +} \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + uint64_t val0 = TLB(env, useronly_clean_ptr(addr), ra); \ + uint64_t val1 = TLB(env, useronly_clean_ptr(addr + 8), ra); \ + uint64_t *ptr = za + off; \ + ptr[0] = BE ? val1 : val0, ptr[1] = BE ? val0 : val1; \ +} \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \ +} + +#define DO_STQ(HNAME, VNAME, BE, HOST, TLB) \ +static inline void HNAME##_host(void *za, intptr_t off, void *host) \ +{ \ + uint64_t *ptr = za + off; \ + HOST(host, ptr[BE]); \ + HOST(host + 1, ptr[!BE]); \ +} \ +static inline void VNAME##_v_host(void *za, intptr_t off, void *host) \ +{ \ + HNAME##_host(za, off * sizeof(ARMVectorReg), host); \ +} \ +static inline void HNAME##_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + uint64_t *ptr = za + off; \ + TLB(env, useronly_clean_ptr(addr), ptr[BE], ra); \ + TLB(env, useronly_clean_ptr(addr + 8), ptr[!BE], ra); \ +} \ +static inline void VNAME##_v_tlb(CPUARMState *env, void *za, intptr_t off, \ + target_ulong addr, uintptr_t ra) \ +{ \ + HNAME##_tlb(env, za, off * sizeof(ARMVectorReg), addr, ra); \ +} + +DO_LD(ld1b, uint8_t, ldub_p, cpu_ldub_data_ra) +DO_LD(ld1h_be, uint16_t, lduw_be_p, cpu_lduw_be_data_ra) +DO_LD(ld1h_le, uint16_t, lduw_le_p, cpu_lduw_le_data_ra) +DO_LD(ld1s_be, uint32_t, ldl_be_p, cpu_ldl_be_data_ra) +DO_LD(ld1s_le, uint32_t, ldl_le_p, cpu_ldl_le_data_ra) +DO_LD(ld1d_be, uint64_t, ldq_be_p, cpu_ldq_be_data_ra) +DO_LD(ld1d_le, uint64_t, ldq_le_p, cpu_ldq_le_data_ra) + +DO_LDQ(sve_ld1qq_be, sme_ld1q_be, 1, ldq_be_p, cpu_ldq_be_data_ra) +DO_LDQ(sve_ld1qq_le, sme_ld1q_le, 0, ldq_le_p, cpu_ldq_le_data_ra) + +DO_ST(st1b, uint8_t, stb_p, cpu_stb_data_ra) +DO_ST(st1h_be, uint16_t, stw_be_p, cpu_stw_be_data_ra) +DO_ST(st1h_le, uint16_t, stw_le_p, cpu_stw_le_data_ra) +DO_ST(st1s_be, uint32_t, stl_be_p, cpu_stl_be_data_ra) +DO_ST(st1s_le, uint32_t, stl_le_p, cpu_stl_le_data_ra) +DO_ST(st1d_be, uint64_t, stq_be_p, cpu_stq_be_data_ra) +DO_ST(st1d_le, uint64_t, stq_le_p, cpu_stq_le_data_ra) + +DO_STQ(sve_st1qq_be, sme_st1q_be, 1, stq_be_p, cpu_stq_be_data_ra) +DO_STQ(sve_st1qq_le, sme_st1q_le, 0, stq_le_p, cpu_stq_le_data_ra) + +#undef DO_LD +#undef DO_ST +#undef DO_LDQ +#undef DO_STQ + +/* + * Common helper for all contiguous predicated loads. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_ld1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + const intptr_t reg_max = simd_oprsz(desc); + const intptr_t esize = 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no load occurs. */ + clr_fn(za, 0, reg_max); + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_LOAD, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_READ, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc => !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags = info.page[0].flags | info.page[1].flags; + if (unlikely(flags != 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. Perform the load + * into scratch memory to preserve register state until the end. + */ + ARMVectorReg scratch = { }; + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[1]; + if (reg_last < 0) { + reg_last = info.reg_off_split; + if (reg_last < 0) { + reg_last = info.reg_off_last[0]; + } + } + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, &scratch, reg_off, addr + reg_off, ra); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + + cpy_fn(za, &scratch, reg_max); + return; +#endif + } + + /* The entire operation is in RAM, on valid pages. */ + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[0]; + host = info.page[0].host; + + if (!vertical) { + memset(za, 0, reg_max); + } else if (reg_off) { + clr_fn(za, 0, reg_off); + } + + while (reg_off <= reg_last) { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off += esize; + } while (reg_off <= reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off = info.reg_off_split; + if (unlikely(reg_off >= 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off = info.reg_off_first[1]; + if (unlikely(reg_off >= 0)) { + reg_last = info.reg_off_last[1]; + host = info.page[1].host; + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } else if (vertical) { + clr_fn(za, reg_off, esize); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, + target_ulong addr, uint32_t desc, uintptr_t ra, + const int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn, + ClearFn *clr_fn, + CopyFn *cpy_fn) +{ + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 = extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc = 0; + } + + sme_ld1(env, za, vg, addr, desc, ra, esz, mtedesc, vertical, + host_fn, tlb_fn, clr_fn, cpy_fn); +} + +#define DO_LD(L, END, ESZ) \ +void HELPER(sme_ld1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ + clear_horizontal, copy_horizontal); \ +} \ +void HELPER(sme_ld1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ + clear_vertical_##L, copy_vertical_##L); \ +} \ +void HELPER(sme_ld1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ + sve_ld1##L##L##END##_host, sve_ld1##L##L##END##_tlb, \ + clear_horizontal, copy_horizontal); \ +} \ +void HELPER(sme_ld1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_ld1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ + sme_ld1##L##END##_v_host, sme_ld1##L##END##_v_tlb, \ + clear_vertical_##L, copy_vertical_##L); \ +} + +DO_LD(b, , MO_8) +DO_LD(h, _be, MO_16) +DO_LD(h, _le, MO_16) +DO_LD(s, _be, MO_32) +DO_LD(s, _le, MO_32) +DO_LD(d, _be, MO_64) +DO_LD(d, _le, MO_64) +DO_LD(q, _be, MO_128) +DO_LD(q, _le, MO_128) + +#undef DO_LD + +/* + * Common helper for all contiguous predicated stores. + */ + +static inline QEMU_ALWAYS_INLINE +void sme_st1(CPUARMState *env, void *za, uint64_t *vg, + const target_ulong addr, uint32_t desc, const uintptr_t ra, + const int esz, uint32_t mtedesc, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + const intptr_t reg_max = simd_oprsz(desc); + const intptr_t esize = 1 << esz; + intptr_t reg_off, reg_last; + SVEContLdSt info; + void *host; + int flags; + + /* Find the active elements. */ + if (!sve_cont_ldst_elements(&info, addr, vg, reg_max, esz, esize)) { + /* The entire predicate was false; no store occurs. */ + return; + } + + /* Probe the page(s). Exit with exception for any invalid page. */ + sve_cont_ldst_pages(&info, FAULT_ALL, env, addr, MMU_DATA_STORE, ra); + + /* Handle watchpoints for all active elements. */ + sve_cont_ldst_watchpoints(&info, env, vg, addr, esize, esize, + BP_MEM_WRITE, ra); + + /* + * Handle mte checks for all active elements. + * Since TBI must be set for MTE, !mtedesc => !mte_active. + */ + if (mtedesc) { + sve_cont_ldst_mte_check(&info, env, vg, addr, esize, esize, + mtedesc, ra); + } + + flags = info.page[0].flags | info.page[1].flags; + if (unlikely(flags != 0)) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + /* + * At least one page includes MMIO. + * Any bus operation can fail with cpu_transaction_failed, + * which for ARM will raise SyncExternal. We cannot avoid + * this fault and will leave with the store incomplete. + */ + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[1]; + if (reg_last < 0) { + reg_last = info.reg_off_split; + if (reg_last < 0) { + reg_last = info.reg_off_last[0]; + } + } + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + reg_off += esize; + } while (reg_off & 63); + } while (reg_off <= reg_last); + return; +#endif + } + + reg_off = info.reg_off_first[0]; + reg_last = info.reg_off_last[0]; + host = info.page[0].host; + + while (reg_off <= reg_last) { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off += 1 << esz; + } while (reg_off <= reg_last && (reg_off & 63)); + } + + /* + * Use the slow path to manage the cross-page misalignment. + * But we know this is RAM and cannot trap. + */ + reg_off = info.reg_off_split; + if (unlikely(reg_off >= 0)) { + tlb_fn(env, za, reg_off, addr + reg_off, ra); + } + + reg_off = info.reg_off_first[1]; + if (unlikely(reg_off >= 0)) { + reg_last = info.reg_off_last[1]; + host = info.page[1].host; + + do { + uint64_t pg = vg[reg_off >> 6]; + do { + if ((pg >> (reg_off & 63)) & 1) { + host_fn(za, reg_off, host + reg_off); + } + reg_off += 1 << esz; + } while (reg_off & 63); + } while (reg_off <= reg_last); + } +} + +static inline QEMU_ALWAYS_INLINE +void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr, + uint32_t desc, uintptr_t ra, int esz, bool vertical, + sve_ldst1_host_fn *host_fn, + sve_ldst1_tlb_fn *tlb_fn) +{ + uint32_t mtedesc = desc >> (SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + int bit55 = extract64(addr, 55, 1); + + /* Remove mtedesc from the normal sve descriptor. */ + desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); + + /* Perform gross MTE suppression early. */ + if (!tbi_check(desc, bit55) || + tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { + mtedesc = 0; + } + + sme_st1(env, za, vg, addr, desc, ra, esz, mtedesc, + vertical, host_fn, tlb_fn); +} + +#define DO_ST(L, END, ESZ) \ +void HELPER(sme_st1##L##END##_h)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, false, \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ +} \ +void HELPER(sme_st1##L##END##_v)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1(env, za, vg, addr, desc, GETPC(), ESZ, 0, true, \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ +} \ +void HELPER(sme_st1##L##END##_h_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, false, \ + sve_st1##L##L##END##_host, sve_st1##L##L##END##_tlb); \ +} \ +void HELPER(sme_st1##L##END##_v_mte)(CPUARMState *env, void *za, void *vg, \ + target_ulong addr, uint32_t desc) \ +{ \ + sme_st1_mte(env, za, vg, addr, desc, GETPC(), ESZ, true, \ + sme_st1##L##END##_v_host, sme_st1##L##END##_v_tlb); \ +} + +DO_ST(b, , MO_8) +DO_ST(h, _be, MO_16) +DO_ST(h, _le, MO_16) +DO_ST(s, _be, MO_32) +DO_ST(s, _le, MO_32) +DO_ST(d, _be, MO_64) +DO_ST(d, _le, MO_64) +DO_ST(q, _be, MO_128) +DO_ST(q, _le, MO_128) + +#undef DO_ST diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index d2a7232491..978af74d1d 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -151,3 +151,72 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) return true; } + +static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) +{ + typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32); + + /* + * Indexed by [esz][be][v][mte][st], which is (except for load/store) + * also the order in which the elements appear in the function names, + * and so how we must concatenate the pieces. + */ + +#define FN_LS(F) { gen_helper_sme_ld1##F, gen_helper_sme_st1##F } +#define FN_MTE(F) { FN_LS(F), FN_LS(F##_mte) } +#define FN_HV(F) { FN_MTE(F##_h), FN_MTE(F##_v) } +#define FN_END(L, B) { FN_HV(L), FN_HV(B) } + + static GenLdSt1 * const fns[5][2][2][2][2] = { + FN_END(b, b), + FN_END(h_le, h_be), + FN_END(s_le, s_be), + FN_END(d_le, d_be), + FN_END(q_le, q_be), + }; + +#undef FN_LS +#undef FN_MTE +#undef FN_HV +#undef FN_END + + TCGv_ptr t_za, t_pg; + TCGv_i64 addr; + int desc = 0; + bool be = s->be_data == MO_BE; + bool mte = s->mte_active[0]; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sme_smza_enabled_check(s)) { + return true; + } + + t_za = get_tile_rowcol(s, a->esz, a->rs, a->za_imm, a->v); + t_pg = pred_full_reg_ptr(s, a->pg); + addr = tcg_temp_new_i64(); + + tcg_gen_shli_i64(addr, cpu_reg(s, a->rn), a->esz); + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rm)); + + if (mte) { + desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); + desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); + desc <<= SVE_MTEDESC_SHIFT; + } else { + addr = clean_data_tbi(s, addr); + } + desc = simd_desc(s->svl, s->svl, desc); + + fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + tcg_constant_i32(desc)); + + tcg_temp_free_ptr(t_za); + tcg_temp_free_ptr(t_pg); + tcg_temp_free_i64(addr); + return true; +} From patchwork Thu Jun 2 21:48:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=UNh13BfV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh2G57YDz9s0w for ; Fri, 3 Jun 2022 08:46:14 +1000 (AEST) Received: from localhost ([::1]:39810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwta0-0005Lo-0z for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:46:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001ic-1b for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:40567) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskL-0000xB-Dy for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:52 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id el14so4460405qvb.7 for ; Thu, 02 Jun 2022 14:52:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=UNh13BfV7arA5TxObmWyk4RxENWFy7Fxw2O8EH2PYF5eIgLYtQ6qv/c9wau5my+FZV 7OUy9EpTk5lCrrOgFUwSfnT36X8HVtcctH1NvymVOUW0Try7w++FwidfcuromWfjd9yT NBxFLnWRG4HeX6BBiRMEhEHI6zNfPC8Fjoc1HwjRAou6fgul2dtx4MxAWkj1Vm41ufdz qJ/SolNoycnVx1FVhCJUg3dEieCeXd4opCao1koeLYqySNLgT/pfE1FOwZltmPYF8vnT vqfDJU91bewoWOTAqkl+l0VYnRTY48s4lT40caFzyYOz8knJm4an771ca+N1W9w6tQMr SQQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=A2mCashB0+zOsF3/PjPFllI+ysVN/UR8lvPC6Q4jjYzQaCFhyLScOIou2rZws834kt k9xtNh380RoAb7sL8NcoqUfIjw2yQoesITa8wd3844eKE+DWqEBkvUpqxpFS3DuacUX6 8pqFpYxVuihmaaVMBQ2aVTXcGho1/yOvjaX5eo161RoIojrSZ6ykLL9fFMApNtOniX15 LnSY6j+LT+fUvb6aWwJCsjsffedYAP5waSrG0kNrduYKR0xGYX/oj64G5QSak8sG+ZfL PyhX/gHJRTpnAuHlEmo7SW3yVFXh6BtSygvDNNaEv0V/lUXoahTmnEXxPug2b+JDd0F+ 3w6g== X-Gm-Message-State: AOAM530W7SRdYTdALmMBXzqdO166M/wkNMBYF87zXLEMK3oemQKcrE8o ZEaumHWhcozKQMw+qBICDsg8pnZ/ucXYxQ== X-Google-Smtp-Source: ABdhPJzYHLcGwLKpBSX8GR7vEe55Pq9ndNY66z+qYRy6v22VAEz5HWoIbEy9DhaG2hCvOKoblgdC9g== X-Received: by 2002:a17:903:41c1:b0:163:771e:e61c with SMTP id u1-20020a17090341c100b00163771ee61cmr6945534ple.49.1654206756302; Thu, 02 Jun 2022 14:52:36 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 47/71] target/arm: Export unpredicated ld/st from translate-sve.c Date: Thu, 2 Jun 2022 14:48:29 -0700 Message-Id: <20220602214853.496211-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index c341c95582..54503745a9 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -165,4 +165,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 13bdd027a5..adf0cd3e68 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4294,7 +4294,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align = QEMU_ALIGN_DOWN(len, 8); int len_remain = len % 8; @@ -4320,7 +4321,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) t0 = tcg_temp_new_i64(); for (i = 0; i < len_align; i += 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4333,6 +4334,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); + if (base != cpu_env) { + TCGv_ptr b = tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base = b; + } + gen_set_label(loop); t0 = tcg_temp_new_i64(); @@ -4340,7 +4347,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); tp = tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4348,6 +4355,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base != cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain == 0); + } } /* @@ -4376,13 +4388,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align = QEMU_ALIGN_DOWN(len, 8); int len_remain = len % 8; @@ -4408,7 +4421,7 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) t0 = tcg_temp_new_i64(); for (i = 0; i < len_align; i += 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4422,11 +4435,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) clean_addr = new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); + if (base != cpu_env) { + TCGv_ptr b = tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base = b; + } + gen_set_label(loop); t0 = tcg_temp_new_i64(); tp = tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4437,12 +4456,17 @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base != cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain == 0); + } } /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 = tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); switch (len_remain) { case 2: @@ -4474,7 +4498,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = vec_full_reg_size(s); int off = vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4487,7 +4511,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = pred_full_reg_size(s); int off = pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4500,7 +4524,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = vec_full_reg_size(s); int off = vec_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4513,7 +4537,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size = pred_full_reg_size(s); int off = pred_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } From patchwork Thu Jun 2 21:48:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=JclfqLLm; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgc01tzdz9s0w for ; Fri, 3 Jun 2022 08:26:56 +1000 (AEST) Received: from localhost ([::1]:49104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtHK-00070v-AH for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:26:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38310) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskD-0001Wu-JE for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:41 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:37398) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskA-0000tS-Cp for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:41 -0400 Received: by mail-pf1-x434.google.com with SMTP id bo5so5804268pfb.4 for ; Thu, 02 Jun 2022 14:52:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DVA+HWK843xLMqB7esE5JHN46OyQAAXOs3TeUqe1TX8=; b=JclfqLLmSR/VNhjJ+CVbnZuBdx/S3gxVc4kdcRZwq4ynp4ilImO1eTjrF57lziVfV6 L6oT4kssaUMDdItnnpN2rxgU1CnN9zdCkYgzr+h2lprqcSnYMeEGJivxIGEdatMwHuy+ q+cRbhROHXjCwpz91xiYC3C1L78AnOlLD6fED8f/MgBMbvhdzYStJXUB63V+/NtPRV83 iNopNLzlfzQsi5fD0vCNlv/xABjKZnn0uUMHVHG87r3kRjo95Va4+SJr8CK28oMQIdn2 y7hJh/MuxCHTxWjjpV582yfh+2vTKYZT2p25ue8kdkiEovu7UOgrB3eGzcuyBgeCkZUd 41NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DVA+HWK843xLMqB7esE5JHN46OyQAAXOs3TeUqe1TX8=; b=NIL6O4QvTo0NvKYAAF2kK21xmKkbutbVH4+tBjnCOod+JVION+HTFMQwITzWYqnp4P Ygg+o/h4RxdhoZf96pch+9ucR9Rab3NIAas51BZxcK/P1x3fbTCBb+KUYRWpkowdOtNl 2REzeSSp39PDlKSMtKVXx7mY6nybEIVUlYa+nWoLs+wQGSYouhXin7bBOz+kyIti0jVj jbHwBZjUsuvGnyZRL/UYnLtCZdGHXwst5jppnYZ3mQiETkrvry3k/A29to+hyaPBNuCE sqR1ct0YXUL1AZFgTHQh+b7lUDu1kzjpWk0Y5ggrh9M+uFdRZtJYr7Qum7HIAKapaQgt tmow== X-Gm-Message-State: AOAM5319h20AqgVN99i7nexyPJbEsPlXgO/a0iF6EMuV2NnnO1vJbpuK 9RdKOKbOhyclcBrRbOsMV3m7mgxLeTIAVA== X-Google-Smtp-Source: ABdhPJybWFCis2NaUpft9Y4aXdFnlM5IH2jxGSuWVNvFlLINqoBDjRrVo28g7lsB6CGTXi/Rbg5IEQ== X-Received: by 2002:a63:d008:0:b0:3fc:f8bb:4ed9 with SMTP id z8-20020a63d008000000b003fcf8bb4ed9mr3091742pgf.215.1654206757067; Thu, 02 Jun 2022 14:52:37 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 48/71] target/arm: Implement SME LDR, STR Date: Thu, 2 Jun 2022 14:48:30 -0700 Message-Id: <20220602214853.496211-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We can reuse the SVE functions for LDR and STR, passing in the base of the ZA vector and a zero offset. Signed-off-by: Richard Henderson --- target/arm/sme.decode | 7 +++++++ target/arm/translate-sme.c | 23 +++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 900e3f2a07..f1ebd857a5 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst rs=%mova_rs LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ &ldst esz=4 rs=%mova_rs + +&ldstr rv rn imm +@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \ + &ldstr rv=%mova_rs + +LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr +STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 978af74d1d..c3e544d69c 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -220,3 +220,26 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) tcg_temp_free_i64(addr); return true; } + +typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int); + +static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) +{ + int imm = a->imm; + TCGv_ptr base; + + if (!sme_za_enabled_check(s)) { + return true; + } + + /* ZA[n] equates to ZA0H.B[n]. */ + base = get_tile_rowcol(s, MO_8, a->rv, imm, false); + + fn(s, base, 0, s->svl, a->rn, imm * s->svl); + + tcg_temp_free_ptr(base); + return true; +} + +TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) +TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) From patchwork Thu Jun 2 21:48:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LwgAeufX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDghC5V55z9s0w for ; Fri, 3 Jun 2022 08:30:35 +1000 (AEST) Received: from localhost ([::1]:59136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtKr-0005Lg-Nc for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:30:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskF-0001bp-8l for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:43 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:37484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskB-0000tk-Ba for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:42 -0400 Received: by mail-pg1-x52e.google.com with SMTP id i185so5809975pge.4 for ; Thu, 02 Jun 2022 14:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sgRdSe37RQpWV2b3fES1plqznaLnrgUpAgZ7R8ertBU=; b=LwgAeufXBNNtdQ6RiRkVhqEH5JpYxrCI9OpUrnwKAqGsdoAHVfjuGFD1Tz2g5v0Efq vhQtqQk6xDh/4R2LbYQh0oK7WDRVnM/PXzFH64LRujKHd684f7EY8PXj6L1MYU/knz89 rs00VL/M3cshj9TEPYpySm+2wu1YknyayDS4KT6yeR6Wzv35cNxYvb+lPz9iIOTZgzWn cINopf6FEk8hrqml0TKjAEMModc4xmkC5rOfAm2Mnxf6NQhZKkniDlQS0NmZwdSTGXe6 KxYxy9U9wJyexlfTMNIlWfl9CgQ9NVCw4M7XcSshf5JaSnTQlgagZrKOo8njwueEmEJu hRdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sgRdSe37RQpWV2b3fES1plqznaLnrgUpAgZ7R8ertBU=; b=KAPUA3bYyUlNEKeWhHKrztKtrBjRtNYbjndS+BRndige2IXehj9lNFByYwLYJduTk2 OvLU8oJYsroQtMZ4n1SpL/K89/z3EgfxOhDKTOi0Io6opzagFFCoZMgCrW0E5s/q59zR XPtlsqKjrnHKsA265T0Q00mSfTawsadP+x3RU6qTm54mQbmW4h24vKCjJJLOTlB9vaj2 ShwtL7aSMp+QW9YXxj0N5xhoiRWy54S08VKflSOVfuaqx1nFThAuP2gXyVxJTlLqjvx0 uGvF0+U24WxaZmlW3UP10KqbJ0g8kmasAkupGeoxYQ8bccPvBxqF7f9s6soh5r5ETTu/ TTZw== X-Gm-Message-State: AOAM533so3hhVtLQXtRNdxoRePgG2O3M9fnF1tWLAyCWhR6ay2/zYhAd /4/IW2mNR60Y6WdQxL+22zqmaTdGbvq92Q== X-Google-Smtp-Source: ABdhPJw0wYpg+s5zHZfPKpn7aSgUN0cQ0xNpO347lNwVnw1GyAwhWNZ1O7mp0O5zNe2JDh2cuKBvyQ== X-Received: by 2002:a63:2b02:0:b0:3fa:fdcf:9c5b with SMTP id r2-20020a632b02000000b003fafdcf9c5bmr5908198pgr.448.1654206757903; Thu, 02 Jun 2022 14:52:37 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 49/71] target/arm: Implement SME ADDHA, ADDVA Date: Thu, 2 Jun 2022 14:48:31 -0700 Message-Id: <20220602214853.496211-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 11 +++++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 +++++++++++++ 4 files changed, 136 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 5cca01f372..6f0fce7e2c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -114,3 +114,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \ LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b32c8435cb..b2b6380901 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -806,3 +806,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; + uint64_t *pn = vpn, *pm = vpm; + uint32_t * restrict zda = vzda, * restrict zn = vzn; + + for (row = 0; row < oprsz; ) { + uint64_t pa = pn[row >> 4]; + do { + if (pa & 1) { + for (col = 0; col < oprsz; ) { + uint64_t pb = pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] += zn[col]; + } + pb >>= 4; + } while (++col & 15); + } + } + pa >>= 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint8_t *pn = vpn, *pm = vpm; + uint64_t * restrict zda = vzda, * restrict zn = vzn; + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] += zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 4; + uint64_t *pn = vpn, *pm = vpm; + uint32_t * restrict zda = vzda, * restrict zn = vzn; + + for (row = 0; row < oprsz; ) { + uint64_t pa = pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row = zn[row]; + for (col = 0; col < oprsz; ) { + uint64_t pb = pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] += zn_row; + } + pb >>= 4; + } while (++col & 15); + } + } + pa >>= 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint8_t *pn = vpn, *pm = vpm; + uint64_t * restrict zda = vzda, * restrict zn = vzn; + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row = zn[row]; + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] += zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index c3e544d69c..e9676b2415 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -243,3 +243,33 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn) TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + uint32_t desc = simd_desc(s->svl, s->svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) From patchwork Thu Jun 2 21:48:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=uWdAnGyt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgtC4B9Gz9sFr for ; Fri, 3 Jun 2022 08:39:15 +1000 (AEST) Received: from localhost ([::1]:47896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtTF-0000Ht-K0 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:39:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskF-0001cZ-Pu for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:45 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:35429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskC-0000tw-4T for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:43 -0400 Received: by mail-pj1-x1030.google.com with SMTP id o6-20020a17090a0a0600b001e2c6566046so10655771pjo.0 for ; Thu, 02 Jun 2022 14:52:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mksmTgYxc+i1xeor+23w3y2aLNd6eFpnSEzpP11e0Kc=; b=uWdAnGytpL8zYWw2bLGkMHLBZhI+VgBdsap+Afoq2rVBY/YgfMIWgB8/Do6ZasMQsV YLYsPaXAgpvQcpR3J71KRPtYW6ur56XRY3v6xJG8tLzQ328RwX+YcFY0cUogcLmneNem 7QjEQDdid7B+1wUd+7Ec1yZrXUSGEcHNsCH0+5/v5bntZOSyPDhEbuxMvl/hAZ95GA5D aAiSAZb8BYIWajoTujht82xkx3aOC1Lu2qCccswQyl4ZenoYMjZkaJpzj2rJY9OZiGe+ J+eDPPzCns982bXwwv7YxGQ3jcOor1ziyC9mXt/ozyTnw46Ss2h+4qXB4O+XV9YiZMgT 6kcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mksmTgYxc+i1xeor+23w3y2aLNd6eFpnSEzpP11e0Kc=; b=M4rjI/TfI8Q0LB2eyqwVLkwg0eSgR8w+VtCGZAZRCsSIf1eJ/ygQi0vGbPHhNQv/Dw 1A1mc4AaDs6wxE3HvU2kglm6/f19LTNiCtgodlB/wCE7/NHdz0eO5SHJlK1rg9Uo8wzZ h9rOB+aiEYeuvjt9NeUsoXPbl8G2mKxTiNW9OYNXELtnkde8V7cWPZ2/Y1chfP4jey14 fZHeq9sk4IkAM4iBvWG2JxIW+wIex5XHZfrbXzhaobLhE6b0DjexQDKG5q3cpdJxwFwQ R9E6dVLws2c6xvrGH/hEXrDYd2DKzvFQQzH7BzpYeyz33kDpN2Snzotw60TYngcftcdw ijfA== X-Gm-Message-State: AOAM532juktFYg2MkGx/XkjrDd9Qr0Ftt3iilxv8Mgy3bmyKrEaFiZfG YDvQa5PvoglAZ20nYxSDirevEtzEP/kiHw== X-Google-Smtp-Source: ABdhPJyrgcpkimoiTcwfMhiRMQE9L9nWMgeABdFaTanwyesgvBgF9ySR4vVnEFeAK4Z48Hlpb27IrA== X-Received: by 2002:a17:902:d4d1:b0:163:82c7:24 with SMTP id o17-20020a170902d4d100b0016382c70024mr6881254plg.5.1654206758724; Thu, 02 Jun 2022 14:52:38 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 50/71] target/arm: Implement FMOPA, FMOPS (non-widening) Date: Thu, 2 Jun 2022 14:48:32 -0700 Message-Id: <20220602214853.496211-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 9 +++++ target/arm/sme_helper.c | 67 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 33 +++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 6f0fce7e2c..727095a3eb 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -119,3 +119,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b2b6380901..16655c86a2 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" @@ -896,3 +897,69 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) << 31; + uint16_t *pn = vpn, *pm = vpm; + + bool save_dn = get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row = 0; row < oprsz; ) { + uint16_t pa = pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row = vza + row * sizeof(ARMVectorReg); + uint32_t n = *(uint32_t *)(vzn + row) ^ neg; + + for (col = 0; col < oprsz; ) { + uint16_t pb = pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a = vza_row + col; + uint32_t *m = vzm + col; + *a = float32_muladd(n, *m, *a, 0, vst); + } + col += 4; + pb >>= 4; + } while (col & 15); + } + } + row += 4; + pa >>= 4; + } while (row & 15); + } + + set_default_nan_mode(save_dn, vst); +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + uint64_t neg = (uint64_t)simd_data(desc) << 63; + uint64_t *za = vza, *zn = vzn, *zm = vzm; + uint8_t *pn = vpn, *pm = vpm; + + bool save_dn = get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row = 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row = &za[row * sizeof(ARMVectorReg)]; + uint64_t n = zn[row] ^ neg; + + for (col = 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a = &za_row[col]; + *a = float64_muladd(n, zm[col], *a, 0, vst); + } + } + } + } + + set_default_nan_mode(save_dn, vst); +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e9676b2415..e6e4541e76 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -273,3 +273,36 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + uint32_t desc = simd_desc(s->svl, s->svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + zm = vec_full_reg_ptr(s, a->zm); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + fpst = fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, + a, MO_32, gen_helper_sme_fmopa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, + a, MO_64, gen_helper_sme_fmopa_d) From patchwork Thu Jun 2 21:48:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=EFMg04W1; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgpM3GjRz9s0w for ; Fri, 3 Jun 2022 08:35:55 +1000 (AEST) Received: from localhost ([::1]:39554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtQ0-0002vq-HN for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskG-0001cr-5f for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:33524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskC-0000uE-WD for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:43 -0400 Received: by mail-pf1-x431.google.com with SMTP id w21so5850085pfc.0 for ; Thu, 02 Jun 2022 14:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l9/P4k41tvaBx3FynADzNq0fNHgArONzp5FUlS6UNac=; b=EFMg04W1++2hdCw6/xl11577eFiJHLXPJMFV4slglvOPf2P5trJcAlDnWoTx0YRXwv 61b/xeV0h0Qt6bwKZXNu2rl4oK95L+fONcQZrvjZDfsWYaJpJd7soBYsBX4m1plVoFsk UUEBTzaxSSGyZY/CsTsxuG9hMLgCyO0l3Vzk/ypRkE3+HQKSG5nqMw2yBOih+mOCRlN4 Udyi9TJx6KG9OR6t7F1Mi4pYDlf//DT5zRQhUQW4XuGEurPNjt+pQos6LMxPSjU9xNE6 MfLKXoaAD57Zattfx60TjI4uwMM1WMkyI7gKytpUq7fMwXP8rDQr9UUsHZP5ohQ2+wbN o5wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l9/P4k41tvaBx3FynADzNq0fNHgArONzp5FUlS6UNac=; b=TXEmL1QRxGBj/NSpaHa4UMrxqZ5J7PO8SDhP3AaSjHzBoP4JTeUUCWP52Yj1dOoFyv p2pPZZA38/rFZajUAE8AvPh67Yo3YWK9ccPJtMVI9HE79PT7bnBNTF0/ps8jQgx0fj/0 mIvzE/HBO/pRRHIxolOMjogTk58zMSIK8DQ7vpWE8am53Iv5OJvLfwk0Xudtre4gv/20 IlZbTFZ25d7auqdiJ923X+1DNmmXzE6gt21GjceEwSWLs4gE8q8zoiENangJjv2QSDKv FQrRwvRjPNay8UTmobUx+7YOAQifZ/ZXOMeAeH4bZTYlQlfSLS7OTmKJt4/zBhSzsx1N tTVw== X-Gm-Message-State: AOAM5327g4PYURJMF9fKNQTduJHH1fdkpnCQI+fufjOV7Y0KJdtTNWEb l1LKc+st0XFv9Rz22TqOJUa3BW9lgzDKfA== X-Google-Smtp-Source: ABdhPJwFzH14KgPRMVsHwOu8SNwWr3I7BxOH6rFKTIknJMIDdPTR0tUgxNbrukTjBqFDpPpRyudC6w== X-Received: by 2002:a65:6b8a:0:b0:3db:7dc5:fec2 with SMTP id d10-20020a656b8a000000b003db7dc5fec2mr5765553pgw.223.1654206759577; Thu, 02 Jun 2022 14:52:39 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 51/71] target/arm: Implement BFMOPA, BFMOPS Date: Thu, 2 Jun 2022 14:48:33 -0700 Message-Id: <20220602214853.496211-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 2 ++ target/arm/sme_helper.c | 52 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 29 +++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 727095a3eb..6b36542133 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -124,3 +124,5 @@ DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index ba4774d174..afd9c0dffd 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -73,3 +73,5 @@ ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 + +BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 16655c86a2..69e4252abc 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -963,3 +963,55 @@ void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, set_default_nan_mode(save_dn, vst); } + +/* + * Alter PAIR as needed for controlling predicates being false, + * and for NEG on an enabled row element. + */ +static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) +{ + pair ^= neg; + if (!(pg & 1)) { + pair &= 0xffff0000u; + } + if (!(pg & 4)) { + pair &= 0x0000ffffu; + } + return pair; +} + +void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) << 15; + uint16_t *pn = vpn, *pm = vpm; + + for (row = 0; row < oprsz; ) { + uint16_t pa = pn[H2(row >> 4)]; + do { + void *vza_row = vza + row * sizeof(ARMVectorReg); + uint32_t n = *(uint32_t *)(vzn + row); + + n = f16mop_adj_pair(n, pa, neg); + + for (col = 0; col < oprsz; ) { + uint16_t pb = pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) == 0b0101 || (pb & 0b0101) == 0b0101) { + uint32_t *a = vza_row + col; + uint32_t m = *(uint32_t *)(vzm + col); + + m = f16mop_adj_pair(m, pb, neg); + *a = bfdotadd(*a, n, m); + + col += 4; + pb >>= 4; + } + } while (col & 15); + } + row += 4; + pa >>= 4; + } while (row & 15); + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e6e4541e76..581bf9174f 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -274,6 +274,32 @@ TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_addva_d) +static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5 *fn) +{ + uint32_t desc = simd_desc(s->svl, s->svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za = get_tile_rowcol(s, esz, 31, a->zad, false); + zn = vec_full_reg_ptr(s, a->zn); + zm = vec_full_reg_ptr(s, a->zm); + pn = pred_full_reg_ptr(s, a->pn); + pm = pred_full_reg_ptr(s, a->pm); + + fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, gen_helper_gvec_5_ptr *fn) { @@ -306,3 +332,6 @@ TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a, MO_64, gen_helper_sme_fmopa_d) + +/* TODO: FEAT_EBF16 */ +TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) From patchwork Thu Jun 2 21:48:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638507 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=KAyMkH19; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgtZ4Kqcz9s0w for ; Fri, 3 Jun 2022 08:39:34 +1000 (AEST) Received: from localhost ([::1]:49484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtTY-0001Lv-Kk for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:39:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskI-0001dA-4e for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:46948) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskD-0000uU-Mi for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:44 -0400 Received: by mail-pl1-x636.google.com with SMTP id w3so5508804plp.13 for ; Thu, 02 Jun 2022 14:52:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jaLSxCdfXBjAEEFrDF/LiYn6nOvGZYPG2MzO42FnVJ8=; b=KAyMkH19KY/Pm2RFkuqWb3Qye0mJCAMve9qqpl4bcuroGDuzPzj6Eenp1rxYW86c3A NhXi1VYeyEMHeovBhn7gMlO3FG/8OVnsjetOZ0hqpJquij9eaniT4suQ190ltnPSv1QE 1NJ3PT45n8cp7lEWWD/CqHo325jPrVJVZw2dP3q+zIMgh0G9+yl5LB+6M8eA80cNemCT PPBHNJfF+WIa4AtrKdSJhROfScsPqq3BV/eS0lzq5hp703cUL1T/A/mOGBHIldrUSNkP XmxkX0ig3b5/QDckmCrTTCL0M2OgCtjqufNhREtUzcqaUnQGd0HqqmlQxyJ2Cg1Zo69F bW8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jaLSxCdfXBjAEEFrDF/LiYn6nOvGZYPG2MzO42FnVJ8=; b=IzvDJlz7cblMjRHJtQ7hA5c1lal/Hc2IrtLylmpD9c5eBYCpQEHDgMUz/IFGxGZDW6 xKpSpWkFFxZK1k0MEw7RsDFQicqhH9Rez/9Vo7jtk/gplVL5CxuyxLcFnYNiC1LZLFEP ezYNTTkIMWeyidWDu0QSG7museiYCDZPzKuhYFG/Y8+MeW09vEwXVJYPi3ufM0Tdu4Zd Kn/9y0IkwFNqeUQIm4LVIdsJvjlOilKUONB3KcdKJCiA86AM9qa566fpUzRFnK2gIx0R 6ZVdKmZfNB/94gVM4aj+JrdZ0bBLfl6GK3Kf37SlgYSH1n2r6+JkCAcG9adxzs4uBKii uShw== X-Gm-Message-State: AOAM532raHEkW61mw9QifXl3lMUOxQ4/2PUM24fmeifO+cZsecjvlKxS TeUQVlmaPNpyLfXXiKVXKaq3C1FmXRdLBA== X-Google-Smtp-Source: ABdhPJwCjDpoXQma+9jWl85MASGwiY8VMcWwZJ0dmpJATC8Mv3/TbUUJyH343P8l0Ak9mnb4vc2ihQ== X-Received: by 2002:a17:902:d64e:b0:163:5074:c130 with SMTP id y14-20020a170902d64e00b001635074c130mr7126494plh.125.1654206760283; Thu, 02 Jun 2022 14:52:40 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 52/71] target/arm: Implement FMOPA, FMOPS (widening) Date: Thu, 2 Jun 2022 14:48:34 -0700 Message-Id: <20220602214853.496211-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 2 ++ target/arm/sme.decode | 1 + target/arm/sme_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 2 ++ 4 files changed, 79 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 6b36542133..ecc957be14 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -120,6 +120,8 @@ DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, diff --git a/target/arm/sme.decode b/target/arm/sme.decode index afd9c0dffd..e8d27fd8a0 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -75,3 +75,4 @@ FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 69e4252abc..0807fbc708 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -980,6 +980,80 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg) return pair; } +static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2, + float_status *s) +{ + float64 e1r = float16_to_float64(e1 & 0xffff, true, s); + float64 e1c = float16_to_float64(e1 >> 16, true, s); + float64 e2r = float16_to_float64(e2 & 0xffff, true, s); + float64 e2c = float16_to_float64(e2 >> 16, true, s); + float64 t64; + float32 t32; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + FloatRoundMode old_rm = get_float_rounding_mode(s); + set_float_rounding_mode(float_round_to_odd, s); + + t64 = float64_mul(e1r, e2r, s); + + set_float_rounding_mode(old_rm, s); + + t64 = float64r32_muladd(e1c, e2c, t64, 0, s); + + /* This conversion is exact, because we've already rounded. */ + t32 = float64_to_float32(t64, s); + + /* The final accumulation step is not fused. */ + return float32_add(sum, t32, s); +} + +void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz = simd_maxsz(desc); + uint32_t neg = simd_data(desc) << 15; + uint16_t *pn = vpn, *pm = vpm; + + bool save_dn = get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row = 0; row < oprsz; ) { + uint16_t pa = pn[H2(row >> 4)]; + do { + void *vza_row = vza + row * sizeof(ARMVectorReg); + uint32_t n = *(uint32_t *)(vzn + row); + + n = f16mop_adj_pair(n, pa, neg); + + for (col = 0; col < oprsz; ) { + uint16_t pb = pm[H2(col >> 4)]; + do { + if ((pa & 0b0101) == 0b0101 || (pb & 0b0101) == 0b0101) { + uint32_t *a = vza_row + col; + uint32_t m = *(uint32_t *)(vzm + col); + + m = f16mop_adj_pair(m, pb, neg); + *a = f16_dotadd(*a, n, m, vst); + + col += 4; + pb >>= 4; + } + } while (col & 15); + } + row += 4; + pa >>= 4; + } while (row & 15); + } + + set_default_nan_mode(save_dn, vst); +} + void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, void *vpm, uint32_t desc) { diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 581bf9174f..847f2274b1 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -328,6 +328,8 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } +TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, + a, MO_32, gen_helper_sme_fmopa_h) TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a, MO_32, gen_helper_sme_fmopa_s) TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, From patchwork Thu Jun 2 21:48:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638511 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=TDIHcX+Y; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgyN70Xnz9s0w for ; Fri, 3 Jun 2022 08:42:52 +1000 (AEST) Received: from localhost ([::1]:59244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtWk-0007wW-Vy for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:42:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38518) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskI-0001dD-6N for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:41757) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskE-0000uo-FK for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:45 -0400 Received: by mail-pj1-x1030.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso5911054pjg.0 for ; Thu, 02 Jun 2022 14:52:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v2OWlMDXUhVyLVgrCa1XT6Oie3T/J/YrHToI9tDWVqs=; b=TDIHcX+YhcJv9QGBgBPMNTQWKRY1540ITeZ9jpxfcda0QMr2f/ZGbu0nsMvIoDhavr H1PQKZrHIfFm5JSK+a+2w4g9a1DP5MVe4EbwwnDjpHUvbCwhDwZ9hvu32XyfYzMoi9Zg 9i0ryN9NUyBcXCNO6VP4jaUweEGWAKryC65Xs3YifRvRFk0R/vMYUtoVkF3WetQG8TGO BsEKfjx/Jk1WSclzoLLBBO8YeRJu8zppZKDQ37aA2Ayllq6cuz4KNZbtKmHli5U+hohD aSfccQneugCEULwBPXnf5PBzbx8awkoKIonc5Ltrigf51ExxNnGOnbSOh8l86IW9JekJ QDiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v2OWlMDXUhVyLVgrCa1XT6Oie3T/J/YrHToI9tDWVqs=; b=5pCzPflPt/Kr5rNd4ew0WB3X0Wqh42/ygEvIoHaD5KIdICaNdpUrB5q6oxlgy9qTn5 iW1hYUx8b6iJ88caI2HiuQ/qHP7xvv9uQU1Wib1pqKIAo9TzFmp1VcaIx39nGHDkTW/I 5PNufPuRHZVS03wXoewoeMtTKMXA+bp/40YEaX+GngrN5oevwUcgTOgZpmnHhk8u9LMa SM2YsDGrbNCf8WFVsFM5VURnc53FGPib3W62nsFITi8o7TsfHNoB7dp4xTU0D5UZrJLo fOUyVKUhquMWRcqx9IlfRZYCJZTQqLcPpiBbV2VPsc2bK6hi1bzBK28/Fdfy0cPnFrpZ HREw== X-Gm-Message-State: AOAM532uMSsAT7HRRgBSDmnvAug4GHldPJKSI0jVmLC28/99ciSWxGYX 2SE/Jlb86vuvTtcOwAI4i/MmRdv6cAqKrw== X-Google-Smtp-Source: ABdhPJzMpW7OyuGrJxmS8tHyF8SdRVtUXwCNsz5rg2d5DlreVXRSb4BxZT+NJA/N7xsaj8nu/iFZrw== X-Received: by 2002:a17:902:f64f:b0:156:f1cc:b284 with SMTP id m15-20020a170902f64f00b00156f1ccb284mr6694383plg.147.1654206761064; Thu, 02 Jun 2022 14:52:41 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 53/71] target/arm: Implement SME integer outer product Date: Thu, 2 Jun 2022 14:48:35 -0700 Message-Id: <20220602214853.496211-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16. Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 16 ++++++++ target/arm/sme.decode | 10 +++++ target/arm/sme_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 14 +++++++ 4 files changed, 122 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index ecc957be14..31562551ee 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -128,3 +128,19 @@ DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sme_bfmopa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_smopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_umopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_sumopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sme_usmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index e8d27fd8a0..628804e37a 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -76,3 +76,13 @@ FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 BFMOPA 10000001 100 ..... ... ... ..... . 00 .. @op_32 FMOPA_h 10000001 101 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_s 1010000 0 10 0 ..... ... ... ..... . 00 .. @op_32 +SUMOPA_s 1010000 0 10 1 ..... ... ... ..... . 00 .. @op_32 +USMOPA_s 1010000 1 10 0 ..... ... ... ..... . 00 .. @op_32 +UMOPA_s 1010000 1 10 1 ..... ... ... ..... . 00 .. @op_32 + +SMOPA_d 1010000 0 11 0 ..... ... ... ..... . 0 ... @op_64 +SUMOPA_d 1010000 0 11 1 ..... ... ... ..... . 0 ... @op_64 +USMOPA_d 1010000 1 11 0 ..... ... ... ..... . 0 ... @op_64 +UMOPA_d 1010000 1 11 1 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 0807fbc708..cebddabbc7 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -1089,3 +1089,85 @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn, } while (row & 15); } } + +typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool); + +static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm, + uint8_t *pn, uint8_t *pm, + uint32_t desc, IMOPFn *fn) +{ + intptr_t row, col, oprsz = simd_oprsz(desc) / 8; + bool neg = simd_data(desc); + + for (row = 0; row < oprsz; ++row) { + uint8_t pa = pn[H1(row)]; + uint64_t *za_row = &za[row * sizeof(ARMVectorReg)]; + uint64_t n = zn[row]; + + for (col = 0; col < oprsz; ++col) { + uint8_t pb = pm[H1(col)]; + uint64_t *a = &za_row[col]; + + *a = fn(n, zm[col], *a, pa & pb, neg); + } + } +} + +#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ +{ \ + uint32_t sum0 = 0, sum1 = 0; \ + /* Apply P to N as a mask, making the inactive elements 0. */ \ + n &= expand_pred_b(p); \ + sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ + sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \ + sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ + sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \ + sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ + sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \ + sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ + sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \ + if (neg) { \ + sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \ + } else { \ + sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \ + } \ + return ((uint64_t)sum1 << 32) | sum0; \ +} + +#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \ +static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \ +{ \ + uint64_t sum = 0; \ + /* Apply P to N as a mask, making the inactive elements 0. */ \ + n &= expand_pred_h(p); \ + sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \ + sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \ + sum += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \ + sum += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \ + return neg ? a - sum : a + sum; \ +} + +DEF_IMOP_32(smopa_s, int8_t, int8_t) +DEF_IMOP_32(umopa_s, uint8_t, uint8_t) +DEF_IMOP_32(sumopa_s, int8_t, uint8_t) +DEF_IMOP_32(usmopa_s, uint8_t, int8_t) + +DEF_IMOP_64(smopa_d, int16_t, int16_t) +DEF_IMOP_64(umopa_d, uint16_t, uint16_t) +DEF_IMOP_64(sumopa_d, int16_t, uint16_t) +DEF_IMOP_64(usmopa_d, uint16_t, int16_t) + +#define DEF_IMOPH(NAME) \ + void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \ + void *vpm, uint32_t desc) \ + { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); } + +DEF_IMOPH(smopa_s) +DEF_IMOPH(umopa_s) +DEF_IMOPH(sumopa_s) +DEF_IMOPH(usmopa_s) +DEF_IMOPH(smopa_d) +DEF_IMOPH(umopa_d) +DEF_IMOPH(sumopa_d) +DEF_IMOPH(usmopa_d) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 847f2274b1..4aa0aff25c 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -337,3 +337,17 @@ TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, /* TODO: FEAT_EBF16 */ TRANS_FEAT(BFMOPA, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_bfmopa) + +TRANS_FEAT(SMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_smopa_s) +TRANS_FEAT(UMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_umopa_s) +TRANS_FEAT(SUMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_sumopa_s) +TRANS_FEAT(USMOPA_s, aa64_sme, do_outprod, a, MO_32, gen_helper_sme_usmopa_s) + +TRANS_FEAT(SMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_smopa_d) +TRANS_FEAT(UMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_umopa_d) +TRANS_FEAT(SUMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_sumopa_d) +TRANS_FEAT(USMOPA_d, aa64_sme_i16i64, do_outprod, + a, MO_64, gen_helper_sme_usmopa_d) From patchwork Thu Jun 2 21:48:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=taIkIsel; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhFS0Gjwz9s0w for ; Fri, 3 Jun 2022 08:55:56 +1000 (AEST) Received: from localhost ([::1]:36478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtjN-0005gi-2K for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:55:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskI-0001d9-42 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:42908) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskF-0000v8-BW for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:45 -0400 Received: by mail-pf1-x431.google.com with SMTP id 187so5797180pfu.9 for ; Thu, 02 Jun 2022 14:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=asM1RIMMm/LbRASBkWsCTEFIsFdYgesXksTZnMcbxew=; b=taIkIselXkd8Iy3nT2sdEa+OJ32gxnfUF50Tqodz9ZG02pD3i2zc6KP4/hKnZNxRCO 9H3h97N0abl6CevaPuIHQWwZZYnqbEU6zWnfAgnZgbqwuH/HDCx/k8oBkU595nw25OIH dQLQWI37Qj7oZ6+qBUd0sv6V7eaxevonj2kr0WTp4WzBIVRSMjFsbfrtbz/QYJsFG1Qc sBEGZXyFGMGITw7kWkfVVOqDKLWx6sak/XTuuKjuVIj9PmuKYDFAJw/XTQT2ISctlEC0 3Gn/uPxoOdFSYv8NizsTcA+Sf0k1Wfz33r0YZzMOYkn6vvm7tdt1gdGV9kCp4juzBl3E E9QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=asM1RIMMm/LbRASBkWsCTEFIsFdYgesXksTZnMcbxew=; b=muqfwgGDShRL86o6bhqaueUpUgQX/hKYgaPALOrngaTK0TKHG8PbafrrTugKpo1Mqm sFnhYAdtbO72aKojsyfGQ9kBJr6fJPkceeJV5oLbKs7cMYeqXaNCLx+czLJ5kK0Y6+WL /5SaxwJhfc/5fmOPt3OS5g+NoB6rq3BWhood1d2EckCM0AKneVrjL9lJG3TMlYXzDMtj Wz5Ag0s7ICAP4IJ4fss8BW+W8bzwS5cRXumjok9K8OJuUngAiGLxDJ5CNyEieIWyINBN +lcNXdXqJt+yA1FVVxnP3bovtF1gSFsIu0B0p9TuVu35iiMLI8UOUcKfg8DD406NuRnH AK7g== X-Gm-Message-State: AOAM531H1tWfS5KR4Lu05EMXW8fz+IT/jr6U3HZ64aTToT03CqfYAHr8 UdEpeq5C4DE5VuuX9hg01NYSrgu5JD8OmA== X-Google-Smtp-Source: ABdhPJx0O/lqLQj4dmuyABfts+dCeqkHEC0MAiCmr34ZYK4VhY1/2Ah7QAm//afNRVl4Pa7Ec0Y+ow== X-Received: by 2002:a63:8ac3:0:b0:3fc:948b:a1d9 with SMTP id y186-20020a638ac3000000b003fc948ba1d9mr6020152pgd.50.1654206762005; Thu, 02 Jun 2022 14:52:42 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 54/71] target/arm: Implement PSEL Date: Thu, 2 Jun 2022 14:48:36 -0700 Message-Id: <20220602214853.496211-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/sve.decode | 20 +++++++++++++ target/arm/translate-sve.c | 57 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index bbdaac6ac7..bf561c270a 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1674,3 +1674,23 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 ### SVE2 floating-point bfloat16 dot-product (indexed) BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 + +### SVE broadcast predicate element + +&psel esz pd pn pm rv imm +%psel_rv 16:2 !function=plus_12 +%psel_imm_b 22:2 19:2 +%psel_imm_h 22:2 20:1 +%psel_imm_s 22:2 +%psel_imm_d 23:1 +@psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ + &psel rv=%psel_rv + +PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ + @psel esz=0 imm=%psel_imm_b +PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ + @psel esz=1 imm=%psel_imm_h +PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ + @psel esz=2 imm=%psel_imm_s +PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ + @psel esz=3 imm=%psel_imm_d diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index adf0cd3e68..58d0894e15 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7379,3 +7379,60 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) + +static bool trans_PSEL(DisasContext *s, arg_psel *a) +{ + int vl = vec_full_reg_size(s); + int pl = pred_gvec_reg_size(s); + int elements = vl >> a->esz; + TCGv_i64 tmp, didx, dbit; + TCGv_ptr ptr; + + if (!dc_isar_feature(aa64_sme, s)) { + return false; + } + if (!sve_access_check(s)) { + return true; + } + + tmp = tcg_temp_new_i64(); + dbit = tcg_temp_new_i64(); + didx = tcg_temp_new_i64(); + ptr = tcg_temp_new_ptr(); + + /* Compute the predicate element. */ + tcg_gen_addi_i64(tmp, cpu_reg(s, a->rv), a->imm); + if (is_power_of_2(elements)) { + tcg_gen_andi_i64(tmp, tmp, elements - 1); + } else { + tcg_gen_remu_i64(tmp, tmp, tcg_constant_i64(elements)); + } + + /* Extract the predicate byte and bit indices. */ + tcg_gen_shli_i64(tmp, tmp, a->esz); + tcg_gen_andi_i64(dbit, tmp, 7); + tcg_gen_shri_i64(didx, tmp, 3); + if (HOST_BIG_ENDIAN) { + tcg_gen_xori_i64(didx, didx, 7); + } + + /* Load the predicate word. */ + tcg_gen_trunc_i64_ptr(ptr, didx); + tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); + + /* Extract the predicate bit and replicate to MO_64. */ + tcg_gen_shr_i64(tmp, tmp, dbit); + tcg_gen_andi_i64(tmp, tmp, 1); + tcg_gen_neg_i64(tmp, tmp); + + /* Apply to either copy the source, or write zeros. */ + tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), + pred_full_reg_offset(s, a->pn), tmp, pl, pl); + + tcg_temp_free_i64(tmp); + tcg_temp_free_i64(dbit); + tcg_temp_free_i64(didx); + tcg_temp_free_ptr(ptr); + return true; +} From patchwork Thu Jun 2 21:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638510 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=RGtVoUAn; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgyN1JRcz9s0w for ; Fri, 3 Jun 2022 08:42:52 +1000 (AEST) Received: from localhost ([::1]:59200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtWj-0007ur-8V for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:42:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskI-0001dE-8x for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:46793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskF-0000vY-W6 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:45 -0400 Received: by mail-pj1-x102a.google.com with SMTP id v5-20020a17090a7c0500b001df84fa82f8so5860855pjf.5 for ; Thu, 02 Jun 2022 14:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cId+jl3LafbTbLYlOOg+jSuzH9qsoTjBGOokKriD7lU=; b=RGtVoUAnKrmiHcDWN7aPbAVtWMmBhVS5coJOccPDEAuospGyYwi2VCYSzMwM/L9GV9 Sa208Knn4EWbKmj1vf1yujxA4fRU1Ir7dJ8tHjHQaBmpSM+bhwTrgiz5kggi8Wa6sASN lL6dbIwoB6blkANJFFVxvvRmKCuuP3KZqpHJlgO4KD0Y4eRZbcPadMj1kJR+vfWpabxg pmvQmXnd5KcsxVFTxFhXUjPGp1F88FhZH6hXXDgppj3g7JIztU/UAfThFuoZPDFSLA6K 7n0XAvRjFCG6MRRfuaIy1kkPMxBWpIihD7rCxkoJmuhm5IL7Mpp7+BMU93xOUBvMGNHk Dvpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cId+jl3LafbTbLYlOOg+jSuzH9qsoTjBGOokKriD7lU=; b=VmuFj/GHhzdrq9wVdWvMfWYEzGH7Is+sF2ggE2I1jvs9XZO8YYdJRTn9dBptPE5o8s DL2DCxWsoL+Bn/qpMfkr6yCVClOe6207ARvUfF/0PRp4k5HNvkQ8UG7bljHSYUg7xBXF vl8ikMUrtzfCOAA51/zeX1qqR5uJd3KM9GYX7BDGyjRugWFxUVL0ftJl9MYbhIEJTX3Z XRWJDyzRNVHKFk1J5rUKv4L4JTlHcIskma1H/SuTL0mMAgd3nnS9BR5bftHZ1LavlV5w rHhnnjIi0IRjpiX54EKbFHnprhgIXdHIu1Rtd8FaKNi4xLWoi38tvbARUQ2ITqqIOMH2 LW2g== X-Gm-Message-State: AOAM5317uYBWPnHsDcUxj6hjWsDY2Znms/rRMJlx595O0BinRRIDNbeD qvnNMI+hSY//HBqGcutn85MbQoWVoOnOFA== X-Google-Smtp-Source: ABdhPJxyjwzEGirAjm0ZjD9Q6FP2eyznf8VNDAbwI8h6hGh22yol6vGj9/TUbI0Ko7Ala4UMzG6rlw== X-Received: by 2002:a17:902:c2d8:b0:15e:fa17:56cc with SMTP id c24-20020a170902c2d800b0015efa1756ccmr6997819pla.40.1654206762721; Thu, 02 Jun 2022 14:52:42 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 55/71] target/arm: Implement REVD Date: Thu, 2 Jun 2022 14:48:37 -0700 Message-Id: <20220602214853.496211-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c | 16 ++++++++++++++++ target/arm/translate-sve.c | 2 ++ 4 files changed, 21 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index ab0333400f..cc4e1d8948 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -719,6 +719,8 @@ DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sme_revd_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index bf561c270a..d1e229fd6e 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9a26f253e0..5de82696b5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + + for (i = 0; i < opr_sz; i += 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 = n[i + 0]; + uint64_t n1 = n[i + 1]; + d[i + 0] = n1; + d[i + 1] = n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 58d0894e15..1129f1fc56 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2896,6 +2896,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) From patchwork Thu Jun 2 21:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=mlNUVBJ1; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh5D6w7xz9s0w for ; Fri, 3 Jun 2022 08:48:48 +1000 (AEST) Received: from localhost ([::1]:47972 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtcV-0002VP-2F for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:48:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskL-0001dJ-Ef for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:34446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskH-0000vu-Nm for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:47 -0400 Received: by mail-pg1-x52a.google.com with SMTP id g184so5823150pgc.1 for ; Thu, 02 Jun 2022 14:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Y6c86S49EQ/11CGVeXxn3v5RBBipyfm3CtBQLEKQtA=; b=mlNUVBJ10G63GYtD4IxlLZ66HnnEGG5SFgKRx2AagAlDe87hZwjtvMn26iJX78skTh MylgRYQcSVqGUG04CIqoUJJCwpQ7IXbYa32c43vP6JNyta23a3kAISqAsT2SocFxov86 jiOm+3rJDsVjjBlSnVgEda3LpD10jgUcXQHgBrL5aJ/P6zGDs1qo74dLLEtq3Zj98nQo otRA7mj5a0Z/m53KCPz8h5P93D0hfrxtD6HdWhuEmd9crrBRfzdKmA0IoDWamuqEYjpv 3DexLj7eWLyBjhzbAJ4qu3KrjF0tzCh3/w9e4saGPXojnHb8MdL8JkfnTz3FwLpdKytC 9xkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Y6c86S49EQ/11CGVeXxn3v5RBBipyfm3CtBQLEKQtA=; b=DPAJ4s8GKkXVF7I61MggTggp+kD+NfaTEOsebC1ASAnxWAv85ZkbvaEd6hzLaiFYUZ 6JEMWKMUobpyMhYt5aMCto1P1+odStkwEfYhon4Z+bX7acATT1SKfq+9eObQWY08uupV Np0+jiPt82PKJqDskiVNR9IQqb03Rn4a3oVVCqGmdOxW9toa7BXUmXNqIlEN30gqoIcH np5Hif+X3Kz8ZD98mApQ6KK6TKrQH7asxLIa2GWUlQTKzpRL9SCunY1KtQaz4ttn834D veMKBTPmC0OH1sgFsQYnUwZPtWeNHnSJcfIPqDBcGLI7VcbmTKGhLh96iscpYnLwwVU4 svkA== X-Gm-Message-State: AOAM5324W8TTH/dDNgzQ/8jEhHMNX1KMDcSY5vWHvsz39qekBBav3v/0 bCk9ZCfnV+2OptrznAzwJxU0fwZFZl5TKg== X-Google-Smtp-Source: ABdhPJzaHczy0263lq6GycRpImwBf9QuYnTJm0Lv4FC5akaG2jJCjbnFzuBj08CNplKmAVjqvokHnw== X-Received: by 2002:a63:f455:0:b0:3fc:e1c1:bf10 with SMTP id p21-20020a63f455000000b003fce1c1bf10mr4387956pgk.467.1654206763515; Thu, 02 Jun 2022 14:52:43 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 56/71] target/arm: Implement SCLAMP, UCLAMP Date: Thu, 2 Jun 2022 14:48:38 -0700 Message-Id: <20220602214853.496211-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.h | 18 +++++++ target/arm/sve.decode | 5 ++ target/arm/translate-sve.c | 102 +++++++++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 24 +++++++++ 4 files changed, 149 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5bca7255f1..f9bc4b29b4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1017,6 +1017,24 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(gvec_uclamp_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/sve.decode b/target/arm/sve.decode index d1e229fd6e..ad411b5790 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1695,3 +1695,8 @@ PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ @psel esz=2 imm=%psel_imm_s PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ @psel esz=3 imm=%psel_imm_d + +### SVE clamp + +SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm +UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 1129f1fc56..40c5bf1a55 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7438,3 +7438,105 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_temp_free_ptr(ptr); return true; } + +static void gen_sclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_smax_i32(d, a, n); + tcg_gen_smin_i32(d, d, m); +} + +static void gen_sclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_smax_i64(d, a, n); + tcg_gen_smin_i64(d, d, m); +} + +static void gen_sclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_smax_vec(vece, d, a, n); + tcg_gen_smin_vec(vece, d, d, m); +} + +static void gen_sclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] = { + INDEX_op_smin_vec, INDEX_op_smax_vec, 0 + }; + static const GVecGen4 ops[4] = { + { .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_b, + .opt_opc = vecop, + .vece = MO_8 }, + { .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_h, + .opt_opc = vecop, + .vece = MO_16 }, + { .fni4 = gen_sclamp_i32, + .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_s, + .opt_opc = vecop, + .vece = MO_32 }, + { .fni8 = gen_sclamp_i64, + .fniv = gen_sclamp_vec, + .fno = gen_helper_gvec_sclamp_d, + .opt_opc = vecop, + .vece = MO_64, + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(SCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_sclamp, a) + +static void gen_uclamp_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, TCGv_i32 a) +{ + tcg_gen_umax_i32(d, a, n); + tcg_gen_umin_i32(d, d, m); +} + +static void gen_uclamp_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 a) +{ + tcg_gen_umax_i64(d, a, n); + tcg_gen_umin_i64(d, d, m); +} + +static void gen_uclamp_vec(unsigned vece, TCGv_vec d, TCGv_vec n, + TCGv_vec m, TCGv_vec a) +{ + tcg_gen_umax_vec(vece, d, a, n); + tcg_gen_umin_vec(vece, d, d, m); +} + +static void gen_uclamp(unsigned vece, uint32_t d, uint32_t n, uint32_t m, + uint32_t a, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop[] = { + INDEX_op_umin_vec, INDEX_op_umax_vec, 0 + }; + static const GVecGen4 ops[4] = { + { .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_b, + .opt_opc = vecop, + .vece = MO_8 }, + { .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_h, + .opt_opc = vecop, + .vece = MO_16 }, + { .fni4 = gen_uclamp_i32, + .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_s, + .opt_opc = vecop, + .vece = MO_32 }, + { .fni8 = gen_uclamp_i64, + .fniv = gen_uclamp_vec, + .fno = gen_helper_gvec_uclamp_d, + .opt_opc = vecop, + .vece = MO_64, + .prefer_i64 = TCG_TARGET_REG_BITS == 64 } + }; + tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &ops[vece]); +} + +TRANS_FEAT(UCLAMP, aa64_sme, gen_gvec_fn_arg_zzzz, gen_uclamp, a) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 9a9c034e36..f59d3b26ea 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -2690,3 +2690,27 @@ void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm, } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +#define DO_CLAMP(NAME, TYPE) \ +void HELPER(NAME)(void *d, void *n, void *m, void *a, uint32_t desc) \ +{ \ + intptr_t i, opr_sz = simd_oprsz(desc); \ + for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \ + TYPE aa = *(TYPE *)(a + i); \ + TYPE nn = *(TYPE *)(n + i); \ + TYPE mm = *(TYPE *)(m + i); \ + TYPE dd = MIN(MAX(aa, nn), mm); \ + *(TYPE *)(d + i) = dd; \ + } \ + clear_tail(d, opr_sz, simd_maxsz(desc)); \ +} + +DO_CLAMP(gvec_sclamp_b, int8_t) +DO_CLAMP(gvec_sclamp_h, int16_t) +DO_CLAMP(gvec_sclamp_s, int32_t) +DO_CLAMP(gvec_sclamp_d, int64_t) + +DO_CLAMP(gvec_uclamp_b, uint8_t) +DO_CLAMP(gvec_uclamp_h, uint16_t) +DO_CLAMP(gvec_uclamp_s, uint32_t) +DO_CLAMP(gvec_uclamp_d, uint64_t) From patchwork Thu Jun 2 21:48:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=vk9WESaJ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh9W1b09z9s0w for ; Fri, 3 Jun 2022 08:52:31 +1000 (AEST) Received: from localhost ([::1]:56414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtg5-00089z-1s for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:52:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskL-0001dM-H0 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:36380) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskH-0000w4-Ou for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:47 -0400 Received: by mail-pj1-x102a.google.com with SMTP id u12-20020a17090a1d4c00b001df78c7c209so10647853pju.1 for ; Thu, 02 Jun 2022 14:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GOZiM5VIUJ7hxXAisXLAxtYs3O/u/UcypIboV374q90=; b=vk9WESaJaWUwIqE6eCG5pL9COhfB/rOS2fgD8DMicZQQl6lxkGCRBmMhj7P0TxzWfV LgMYLQkKfhvtLAWnZm/CFA+DmqEuhzGr5emHr/mjG5j+mvN0FesxtTKQ5h2X7ZSEHjX7 TPHqUd6WpJPpb/sY+0fAXrp575oGU5/39+IJpoeZV99NwVKQkOWRwBYnwjyWv0XKOpU8 pyQ3iVlmVdUj1uCpnFeKC/YVML0YRor2ElgRj8hGr+DVZV7F9aJPA+AweUAun2skXVpU KIU1/SFJ0y6vhHXp7Q+SksROPNxYBiM6gIyWEcCRkhok6Wi41pq1n4tuSK59l63VKWyo UwGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GOZiM5VIUJ7hxXAisXLAxtYs3O/u/UcypIboV374q90=; b=K235BSfYpSrOYcZ5qnGYygbd93P+VsVkhyi/H0vhqx23V7CY3c1WJDUSsdvFoR4E56 2wTblCmBNNmKPyBGTESdbWVZFvLbVLuUnx3emG6H1gIqgplEXROoa8PjXjEXK+R5NkR6 F2dw/AWBE9s+pEFlVChjauoyzq4YhrnYs1ALYraIyC+FJYkt0W8VuLdkR7b5MFxmrKSS ObgyVsmK8lHF36gkvDBs553OI9KfGakPxdVWiDPj6+9/T0z2d73zbev2Ydgliw/MR8iD +JWfXFsqhSFfXX7BRXfaILW7vqGHZSwUAE1xHkqB8GJv8mcQuMQogrOqmqJN/jEju3zw 7VZQ== X-Gm-Message-State: AOAM530W5A8FQnswaSDgVzGrSKmyPHR4x6uUrAp5EiEIftkDUbxq0DEW UTO3cKC0U6ZAFPYw8hWFyc2quUSdRvKL6A== X-Google-Smtp-Source: ABdhPJxMZrWS7eZ4FXlpkNAPnt79duaXqJF40kB1iGGZd7VmYSH4F85Fd//jypVLYR8f1BWLBUsssw== X-Received: by 2002:a17:902:8487:b0:15f:b2c:435 with SMTP id c7-20020a170902848700b0015f0b2c0435mr6928647plo.33.1654206764263; Thu, 02 Jun 2022 14:52:44 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 57/71] target/arm: Reset streaming sve state on exception boundaries Date: Thu, 2 Jun 2022 14:48:39 -0700 Message-Id: <20220602214853.496211-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We can handle both exception entry and exception return by hooking into aarch64_sve_change_el. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7396be4352..af612b52b5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14276,6 +14276,19 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, return; } + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + + /* + * Both AArch64.TakeException and AArch64.ExceptionReturn + * invoke ResetSVEState when taking an exception from, or + * returning to, AArch32 state when PSTATE.SM is enabled. + */ + if (old_a64 != new_a64 && FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + return; + } + /* * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped * at ELx, or not available because the EL is in AArch32 state, then @@ -14288,10 +14301,8 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len = (old_a64 && !sve_exception_el(env, old_el) ? sve_vqm1_for_el(env, old_el) : 0); - new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len = (new_a64 && !sve_exception_el(env, new_el) ? sve_vqm1_for_el(env, new_el) : 0); From patchwork Thu Jun 2 21:48:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=WQa2vu1w; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDgxp2jX7z9s0w for ; Fri, 3 Jun 2022 08:42:22 +1000 (AEST) Received: from localhost ([::1]:58244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtWG-0007Ia-Ep for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:42:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38634) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskL-0001eP-NY for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:49 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:44680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskI-0000wF-KO for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:48 -0400 Received: by mail-pj1-x1030.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so5876427pjb.3 for ; Thu, 02 Jun 2022 14:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mFVh//BfUxyaXH4iD2Urka1nyqKt2dpPAkCKhfkhOyw=; b=WQa2vu1wcLEcs2BIUcuyvhiVHdgDF3ulolTu9+CzNxXIynp2w3lLsvgS1HOsGrwtEc L8c9L/6NCoQYQPKOiOOyKYbHi4/qRBON/ibGFFCjAHE5QJGcvDvayYjIWstqjlC99T5c SnNUHwbr1LQOHJH+TqBbqlm86/eZg2epavfWYIuj0KsRwXMy3qDPAx2bdihs9wJuoAiN klWyla4q6I2JSFjOGMua7aomJ5sWKg0V6kVDO+GUoroHe57m7PZSiBSHCUnQDdYrxIvg DCNd2umrbnFZeSIt8Q8/caG1FmiWn1uP+QYLRYe4ySWhFuTnipQfco41Qo5LMUN9hIv2 SC+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mFVh//BfUxyaXH4iD2Urka1nyqKt2dpPAkCKhfkhOyw=; b=I4W1lIC9mraeCsa3GrcRWs5j8VLUz79TuQpyLbUWN2aYt5TVSvgUQWjEYNBrV+HS7A BhO0jsktk4G3G4ee3CIVNqdwWeD3Tz3DBxsv5ImRFFgafebUEL7pAgKpiibjSPm/dpz+ CBTX4CABo4F/jxbIThuUmrzcNxqC9+ctUa7yzoaEPP0eTO5ffHJpTrK+TUD+jZTPGMaf LNmHpAn8iBj9kCGScLBr9iwM33wmLKM9E0JPo2wCbWnvhts+gyms4F/r/jUWgbUE9oet YwchrZhTL9GL1fwAERyogfWV7nvbhmwyT0Cd+RKE3Jd4KQDAwRADlHJiWTLoLwePhjOB VqOA== X-Gm-Message-State: AOAM532ELBCi+kPEQYjmY4vqJ/LDL0aORdo/bu2GGqi4u18WFehacmOM 0cmxEqUr6eFugm8KI02wgTwEt1cxE2CXdw== X-Google-Smtp-Source: ABdhPJxd/ucThABlh+YAaWP/5Csy+crNZzM742XzFefhGa+LFW/r26BExoGeKmtSHwrKqfdElOkPXQ== X-Received: by 2002:a17:903:25c1:b0:164:1517:e8c3 with SMTP id jc1-20020a17090325c100b001641517e8c3mr7143204plb.116.1654206765246; Thu, 02 Jun 2022 14:52:45 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 58/71] target/arm: Enable SME for -cpu max Date: Thu, 2 Jun 2022 14:48:40 -0700 Message-Id: <20220602214853.496211-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Note that SME remains effectively disabled for user-only, because we do not yet set CPACR_EL1.SMEN. This needs to wait until the kernel ABI is implemented. Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 4 ++++ target/arm/cpu64.c | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 49cc3e8340..834289cb8e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,10 @@ the following architecture extensions: - FEAT_SHA512 (Advanced SIMD SHA512 instructions) - FEAT_SM3 (Advanced SIMD SM3 instructions) - FEAT_SM4 (Advanced SIMD SM4 instructions) +- FEAT_SME (Scalable Matrix Extension) +- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) +- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) +- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index aaf2c243d6..d77522e278 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1017,6 +1017,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=on property. */ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 = t; @@ -1067,6 +1068,16 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 = t; + t = cpu->isar.id_aa64smfr0; + t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */ + t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ + t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ + t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ + cpu->isar.id_aa64smfr0 = t; + /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); From patchwork Thu Jun 2 21:48:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bg3Fli44; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh4h5rqZz9s0w for ; Fri, 3 Jun 2022 08:48:20 +1000 (AEST) Received: from localhost ([::1]:45888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtc2-00016T-E5 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:48:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskM-0001h6-SA for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:53 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:43746) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskJ-0000re-Hz for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:50 -0400 Received: by mail-pj1-x1029.google.com with SMTP id l7-20020a17090aaa8700b001dd1a5b9965so5882494pjq.2 for ; Thu, 02 Jun 2022 14:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h8NNZqBa/oaHcQdJifd9wVEds8arqW1sbQgko9Vs+gQ=; b=bg3Fli44Ic1XJqkc889xc/WCNbVx6q3cClYbT99/y1umLsyQXql+DpCCpHpPlhzSW+ mPSGgEAhDZr9iIRxvoMctOimn5t7XqDribZ9c1eDlDUsLZX7n9hObxcqI46o7lJZ+S4X wYKyezrm5dF1G/WJmSZMRP9xgDwa1EruQyOzZw3MjFKZbRTkByXK7eWIPuqehCEn9d4w AnOg+g8h/SY0A/pfBSZDAxbG7cm/rK5Wiuj3f/CiSpNaTeDD7wofv9yLS6DljbPiJrTJ nzaHETacJiE1q6MPzGC8b8IqoyAVxeLiIvwFKJDKG6p48ustslK8j52XTV+urESTL2vc 4QWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h8NNZqBa/oaHcQdJifd9wVEds8arqW1sbQgko9Vs+gQ=; b=csCxg6zZipOu127HEb6CT3HTHsPIWEYEO+Lwmem8lPTu9IYDIACig4A9vrTrOLFsJM D6FdRMtKz8vLQVQr1gg+AnezvrxENyTbrgs5OXgCotvzXk6NrcgdjQQYbTuKqv4ElLYp fAlPz3z6MvkcQJVBKm8Ag432NkdR2vvNYKFVxqVH4EF/bTo1XIdI/92jvLycTVT/IsPZ 6BPKZoIdgGb71yGj7zlwcV+30KX3HbTluOROcukk/0O7dM+QGf6b3mYox/gY7HmqoiZn RWq9taPEDu2EkV3/SAxvDN1i+YpnxK3Dv5xnsnQ+y/GZnbwj698jLNBvXeCK3cjG2Vtl G0vA== X-Gm-Message-State: AOAM531NT9Ju37dIUv4wdVFtoqQpt5JLAbLBKLTiz+eAo0FmFppn2ES0 1t3mgTRKnq81TW9E3JqiU7J0lVInWHCIuQ== X-Google-Smtp-Source: ABdhPJw8j9fDaO61rwVKjNwBa7b69M5yiPqQQTZ6/3ik1Jb8P9MWHoNUJnz9jImR3Kg9x9B0E3cxmQ== X-Received: by 2002:a17:90a:cb8c:b0:1e6:715f:ed28 with SMTP id a12-20020a17090acb8c00b001e6715fed28mr7447100pju.69.1654206765945; Thu, 02 Jun 2022 14:52:45 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 59/71] linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS Date: Thu, 2 Jun 2022 14:48:41 -0700 Message-Id: <20220602214853.496211-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/target_cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h index 97a477bd3e..f90359faf2 100644 --- a/linux-user/aarch64/target_cpu.h +++ b/linux-user/aarch64/target_cpu.h @@ -34,10 +34,13 @@ static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags) static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { - /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is + /* + * Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is * different from AArch32 Linux, which uses TPIDRRO. */ env->cp15.tpidr_el[0] = newtls; + /* TPIDR2_EL0 is cleared with CLONE_SETTLS. */ + env->cp15.tpidr2_el0 = 0; } static inline abi_ulong get_sp_from_cpustate(CPUARMState *state) From patchwork Thu Jun 2 21:48:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gsZz0Tyi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh2v3rkRz9s0w for ; Fri, 3 Jun 2022 08:46:47 +1000 (AEST) Received: from localhost ([::1]:42208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtaX-00071Q-Ji for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:46:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001if-2Z for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46946) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskL-0000tx-Dp for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:51 -0400 Received: by mail-pl1-x634.google.com with SMTP id w3so5508758plp.13 for ; Thu, 02 Jun 2022 14:52:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VJKQ6WoqB0EGYqa/ELNpHbDiJmRFJHnsDZvzPsZOiDk=; b=gsZz0TyimC007DcePY8I4GsBFmI0xvPR19BY6g6qfL4iDKpXqKeSnoz60taOm6W96y DLGXYn16Pmu4jO5i1j5DG6ptDnC75rVssLmu3xOJH3iE9rIKbaBcJpORN6U0n6cXOQM6 MlPArFcCsLiOdHLDaotSJgLO9WY6QwrZVqRJaPhYsw9ORC5PCGk+Wh8lo11C+SXIC+je KGe5XJuVnWF9fxux019CeFbK98oOvMGCD9ihw8rNg9/5OPLSxJYVdupzq9B1IeMII03X 0aDaHaa4i3+MO55Ud3EPCvoWV+Y2F1yY8z40rQWcVDRJBb/L+8p4yosNdrzbsuVqjriC n3SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VJKQ6WoqB0EGYqa/ELNpHbDiJmRFJHnsDZvzPsZOiDk=; b=h62XPSVqEBz/OPXMgwi3CzZpmjD8c0HrMz74Wwaad5oxapo10i4C/1makWwBv3KeDh dN5FwUlSw13ldZfi9fZSWv5ISzLZU1ZMWNTBtNEjYdT/eyZQUAskiGWAgXBiSNXA0rxP yqbAUrdAv8vxvAIhX6maQeXhkFc4g88bRW0KrwlekWS9wI33Yy5RSkGb+dXR+rhkys5U ewYR4eZU46XAvIHePyV0O3/jrGsBB3+I8hZ6zSGlLPklPknlQrShU2dw0gZAA9DNeP3L SXUFmdZAWhkPd1gpyj65o2l4g2rrFN2OPdsyX2Kvca7jMDDi971MJg5i/BYxEFPAlKk6 4wdw== X-Gm-Message-State: AOAM533Hn6Q6rcPYNOFAfmW00+wtdckvDEp7h2mbFQqs51HWnIodazLe JHssuTSaheTlSLzy2yywf3lwzopHdVIQ+A== X-Google-Smtp-Source: ABdhPJwdz7AgvrHWWyQcjaFEGJiQZKJPHfn7BzN+sQTgmBqUUNESFNxLfmfMrg+jPWWREPAAlDAW3Q== X-Received: by 2002:a17:902:ef43:b0:156:9c5d:b0fe with SMTP id e3-20020a170902ef4300b001569c5db0femr6923626plx.158.1654206766667; Thu, 02 Jun 2022 14:52:46 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 60/71] linux-user/aarch64: Reset PSTATE.SM on syscalls Date: Thu, 2 Jun 2022 14:48:42 -0700 Message-Id: <20220602214853.496211-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b273f6299..4af6996d57 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,15 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: + /* + * On syscall, PSTATE.ZA is preserved, along with the ZA matrix. + * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + env->svcr = FIELD_DP64(env->svcr, SVCR, SM, 0); + arm_rebuild_hflags(env); + arm_reset_sve_state(env); + } ret = do_syscall(env, env->xregs[8], env->xregs[0], From patchwork Thu Jun 2 21:48:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Rj3C6XmP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh5g3Vp4z9s0w for ; Fri, 3 Jun 2022 08:49:11 +1000 (AEST) Received: from localhost ([::1]:49626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtcr-0003do-9s for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001ie-25 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:35338) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskL-0000xH-EJ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:52 -0400 Received: by mail-pl1-x635.google.com with SMTP id o6so454906plg.2 for ; Thu, 02 Jun 2022 14:52:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fTTanV00VRUEDDRlC72SOtxqE7eMJfPYW/wq+3NK8Kc=; b=Rj3C6XmPE62VN/vOznNbclSEGFkL7frNTgm42UpAuyE2uOcpb3N9dRaqOkEinqVzGi bThh3XLxAapareQ83mUCt59uxKK7xYFpS+YErTymS+8+2zjE7OvDO4pL6wZvl1mDmv5E usqDjJKQ0uzaw53rqnRmMYN/4+oKCICooZhV9jb2JHuNmOOwYQFGi5iIi1VWM6d4c+gu 0cRSu46fRcNWpl+AMW6tnnTHmeX3J46TPLMu30O62EEtIubUXDJjtIkcxmAzn2wYh0Pc PF/OvjmAUwVlINedJE5FqS6q0sgoqhWp1k/+Zwb9mHPm29OqqZXTRXURZkEgJwNiFXUp q1RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fTTanV00VRUEDDRlC72SOtxqE7eMJfPYW/wq+3NK8Kc=; b=vLpKmj/9vgbu2AjiRO/e1NKTmaQbIPtmn9kTs0OzJMwkXGLmhSD6wUhpD1TZ8kSBLH NRZx5WJP2FWSHFtPDbvecypkplyoRr91A9b9a2e55Y+t3klcn9368RHe7nlCo4JXhYHF oOBGlpOC71KJGe7UmEQujMn47cOcMQ9f8SYORjp7dco2Woh2tGCUYd3PeaW3QugfLB3C +YBQs03XhXidZm183ZNfIEXdLPrWiL3dUOHhLEgiNkEqnDiRkZIAFAlC7MoahD3n1G0X d5q2tZXYXEoH4ebZjomxWV7XpLCtB/Yx3Yh7b/IdsAMN8+bZxExpUyx78DBTf9pvbjKv TMew== X-Gm-Message-State: AOAM531z4QBH9qCVgW2OeqJ1bmw4tZMs8KpBwCsHVdczuXyD+E07e1DK Wu0lt2210LOzGJdCcRFRPbtSctDKex57gg== X-Google-Smtp-Source: ABdhPJzBDoYaVXQbnKEz+ypkWBh/E+iyG4Z/IvDUgIUPovGsgtSTgIghlU4pYaavWHbqk/5hBencHQ== X-Received: by 2002:a17:902:9a42:b0:158:bf91:ecec with SMTP id x2-20020a1709029a4200b00158bf91ececmr7023731plv.115.1654206767820; Thu, 02 Jun 2022 14:52:47 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 61/71] linux-user/aarch64: Add SM bit to SVE signal context Date: Thu, 2 Jun 2022 14:48:43 -0700 Message-Id: <20220602214853.496211-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make sure to zero the currently reserved fields. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 30e89f67c8..08a9746ace 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -78,7 +78,8 @@ struct target_extra_context { struct target_sve_context { struct target_aarch64_ctx head; uint16_t vl; - uint16_t reserved[3]; + uint16_t flags; + uint16_t reserved[2]; /* The actual SVE data immediately follows. It is laid out * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of * the original struct pointer. @@ -101,6 +102,8 @@ struct target_sve_context { #define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) +#define TARGET_SVE_SIG_FLAG_SM 1 + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -177,9 +180,13 @@ static void target_setup_sve_record(struct target_sve_context *sve, { int i, j; + memset(sve, 0, sizeof(*sve)); __put_user(TARGET_SVE_MAGIC, &sve->head.magic); __put_user(size, &sve->head.size); __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + if (FIELD_EX64(env->svcr, SVCR, SM)) { + __put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags); + } /* Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian store From patchwork Thu Jun 2 21:48:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=v8k2SBmg; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhY61DKyz9sFr for ; Fri, 3 Jun 2022 09:09:30 +1000 (AEST) Received: from localhost ([::1]:34226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtwW-0006qM-9X for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 19:09:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001ih-4Y for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:44686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskM-0000xT-1a for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:53 -0400 Received: by mail-pj1-x1036.google.com with SMTP id gc3-20020a17090b310300b001e33092c737so5876504pjb.3 for ; Thu, 02 Jun 2022 14:52:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xfbnb7TdCVSBLKBo6fQd3FAajC5xAFCP1x/5wXNW3q0=; b=v8k2SBmgfeWDCm5dCMsYKFNEoxiA8XNxvV+gwWW325JQljR9R6pjS6PsSQnD1KKJLa 9p0oGJ1/8mSLt51aeL52tzYhqO85WNSV/9hMgXmx0BevqYd8jsB7spjV55ohf9XSp4vH /doTqwaGp2OssIaF4Xd6CG4TAjCNSftLmcAOZO/iK/mCh3yuafKt+CFZNH9Tx+zxY5t5 driUzbqVaP+cyP0PU9L2sWNYcS/Ii6ErKa7Rf1uCB0Tj5qjaJy45FTU3GCvaJzmAoaqC RzomYQ4lc+BzPqXM9ClWnB1apbhcpJqpwTTqH8dLusQ09x5ZFDmdfn1VYUMUf0WmzvzC vX3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xfbnb7TdCVSBLKBo6fQd3FAajC5xAFCP1x/5wXNW3q0=; b=3WQ57WUkN65BUC20sUas2ENJdhHSm9mw7GV7vs1iNOdYhs2CP6P+sTjbHINOcweYnb PzO2LRX0/k4fc4bDiJZfCqtvDs7TJh2Dp3E/EfwTed3vn/rlcMrXghZPUrEkD7KsTrph fChMsPRM7nGINUS0fzGhTCvxYwv+pt1bC0QYIlD3fYB3ZlGShUAirfr72cPwWsSK+lHT 31X02SzuHKMZc9YeeeUKBmKbUayysvta92MUVROcoZ+ycAefF9RkX5LfmIp4VFUb5ezG dmh9xc0472N80xHIbQx6UKs8ZH/Id4YfKNn3/kYYCCTZa/WJGO0JuF3GmeDO50W1VJJs /dew== X-Gm-Message-State: AOAM530crg4rA//FzGkc1UUmOxiV76C6qYiMcneG4dgiUdCY30m4fLmo +CqAC2CRJgDeR6TDCYIzr5K5oVoeFLaUcA== X-Google-Smtp-Source: ABdhPJw0dz5EE+B7ApLala/BssvTllvxPMHo5lXYJNA4mWYH2JhAvL9dsdkZyU8+45PEyv9eHrhI4w== X-Received: by 2002:a17:903:11d0:b0:155:c240:a2c0 with SMTP id q16-20020a17090311d000b00155c240a2c0mr6866622plh.143.1654206768753; Thu, 02 Jun 2022 14:52:48 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 62/71] linux-user/aarch64: Tidy target_restore_sigframe error return Date: Thu, 2 Jun 2022 14:48:44 -0700 Message-Id: <20220602214853.496211-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Fold the return value setting into the goto, so each point of failure need not do both. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 08a9746ace..e9ff280d2a 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -287,7 +287,6 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve = NULL; uint64_t extra_datap = 0; bool used_extra = false; - bool err = false; int vq = 0, sve_size = 0; target_restore_general_frame(env, sf); @@ -301,8 +300,7 @@ static int target_restore_sigframe(CPUARMState *env, switch (magic) { case 0: if (size != 0) { - err = true; - goto exit; + goto err; } if (used_extra) { ctx = NULL; @@ -314,8 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, case TARGET_FPSIMD_MAGIC: if (fpsimd || size != sizeof(struct target_fpsimd_context)) { - err = true; - goto exit; + goto err; } fpsimd = (struct target_fpsimd_context *)ctx; break; @@ -329,13 +326,11 @@ static int target_restore_sigframe(CPUARMState *env, break; } } - err = true; - goto exit; + goto err; case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { - err = true; - goto exit; + goto err; } __get_user(extra_datap, &((struct target_extra_context *)ctx)->datap); @@ -348,8 +343,7 @@ static int target_restore_sigframe(CPUARMState *env, /* Unknown record -- we certainly didn't generate it. * Did we in fact get out of sync? */ - err = true; - goto exit; + goto err; } ctx = (void *)ctx + size; } @@ -358,17 +352,19 @@ static int target_restore_sigframe(CPUARMState *env, if (fpsimd) { target_restore_fpsimd_record(env, fpsimd); } else { - err = true; + goto err; } /* SVE data, if present, overwrites FPSIMD data. */ if (sve) { target_restore_sve_record(env, sve, vq); } - - exit: unlock_user(extra, extra_datap, 0); - return err; + return 0; + + err: + unlock_user(extra, extra_datap, 0); + return 1; } static abi_ulong get_sigframe(struct target_sigaction *ka, From patchwork Thu Jun 2 21:48:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jFrq7X3n; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh683tkMz9s0w for ; Fri, 3 Jun 2022 08:49:36 +1000 (AEST) Received: from localhost ([::1]:51854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtdG-00057T-IM for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:49:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001ii-49 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:46793) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskM-0000vY-EN for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:53 -0400 Received: by mail-pj1-x102a.google.com with SMTP id v5-20020a17090a7c0500b001df84fa82f8so5860855pjf.5 for ; Thu, 02 Jun 2022 14:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aHd4rex5KLokg6+1+Y3fFNXszj9You6Kl613kNttCcU=; b=jFrq7X3n2vOjm1EoiPKRlOOc5WkVJw6gGEw0kWR/bZ5oYbkfVb2Fhr26iBhmYMG7rw FbLbzu+lw4gXzax1v740DlIF4uhnBMyCb5qdKQAsW6OyViogpkwI5oIdDytGAxjEiQlF wPBxVBHOyqNsLAdxYE9H5R0qiBvqreCRL6SsGexL7pJp+pGKMb1f3PbPqZjSYL2lHjqP E9VB4J0qtGOxNFPVOOKd47CajEPQDuMmXef8rpu563KRJck+Fyw3JhQu9263eOCf32Bp 9T3ppDmwjyndHiRY1XxfGz4SUfeeZ8XwuhkEf8rAuN/XEGBZFFODYbvTtnoLwryqVPQF 675g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aHd4rex5KLokg6+1+Y3fFNXszj9You6Kl613kNttCcU=; b=4FcnO0VZgkLP6a4oBG/4Ydf3OfHMJLl1HQ9IOU3mu9NMsqVvEf85v5Wthtd4cpBaTe gezTdby4XpD/ucKN0OrSMt26257AOX5TAzdm0vS1SG6VxP7cITTUEiK6+G1V1Aj5qEJR YajANcB4SEbf9pBh8tu69kEsRc/vMMGfp/liLnDzxhD239q27VhgBELzNOScecD6f1xE Hlg+HkenpNuHrXNdypQ/UteyrJewe4jRU3FnMrnB5kZhdAyI9OX+Wtc0Bv+pZPGfNgPO UEUHB3/EjAGMnNAW7Chs2X1NNA7DpVa/qH2xBNwfbOnl2Mn7zfLW96yB0+5cQ0FLhYwT 31GQ== X-Gm-Message-State: AOAM533QOFrPSg4iyQK0rP6ESIMn0GiQcY5v8xBvtOdw2ZzCzvNXXCtT MQgf8wNT25IVBrV4I78foIqJrNI1CI+osw== X-Google-Smtp-Source: ABdhPJzi492VvwtTo4Lxrm+ONs+Sg8sDfeiad1LA6iotPWIu6P72tGD6p2uZk7HMkFufz6x7/YtvWw== X-Received: by 2002:a17:90a:a384:b0:1dc:a407:b5ac with SMTP id x4-20020a17090aa38400b001dca407b5acmr7499555pjp.11.1654206769627; Thu, 02 Jun 2022 14:52:49 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 63/71] linux-user/aarch64: Do not allow duplicate or short sve records Date: Thu, 2 Jun 2022 14:48:45 -0700 Message-Id: <20220602214853.496211-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In parse_user_sigframe, the kernel rejects duplicate sve records, or records that are smaller than the header. We were silently allowing these cases to pass, dropping the record. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index e9ff280d2a..590f2258b2 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -318,10 +318,13 @@ static int target_restore_sigframe(CPUARMState *env, break; case TARGET_SVE_MAGIC: + if (sve || size < sizeof(struct target_sve_context)) { + goto err; + } if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq = sve_vq_cached(env); sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); - if (!sve && size == sve_size) { + if (size == sve_size) { sve = (struct target_sve_context *)ctx; break; } From patchwork Thu Jun 2 21:48:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638531 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LZVb9I1g; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhT16ljwz9sFk for ; Fri, 3 Jun 2022 09:05:56 +1000 (AEST) Received: from localhost ([::1]:54752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtt1-0001Yp-Hf for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 19:05:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001il-Ex for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:33787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskN-0000vZ-EB for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:54 -0400 Received: by mail-pl1-x62b.google.com with SMTP id s12so5586268plp.0 for ; Thu, 02 Jun 2022 14:52:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SAiy4u2+hcjlkm4K4/FWEX6wsTP/y8YNbat6sNJslGQ=; b=LZVb9I1gjy3lEmOuvnrHzTPD7EeKZn7wicuW1n8fOgUHmjSpU1grEBNZyO63gg2mrZ WZHmeKlrfKOK4D1d47Zfizvroehz1IZRLT/CjqPGyj0sJDuW8yzGfG2kYj7Llz17jLF0 YIe8pgLJgqXQ1wlI33LlPkIY+ARw5x2MEforEkIwMLIL6/qdp9eA2M79DEhG1LLeToSj 4KgDKjMX/uE4hNsk4H6hLzlep/EoVUgbeCf/KqHABZVQDfr2XoQSXYIZMgTvqMe/logg 3FgiVTwOlqwHLawAlIe3prLge6UX5I3jP6jtCqZYuCPSGw3Xp6VPfvv1CfoqG/tqvTJM N3KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SAiy4u2+hcjlkm4K4/FWEX6wsTP/y8YNbat6sNJslGQ=; b=6hpOUyGYj1rAC6FZBNX/qkvee8n4Y0r8KfSvmBpGtf6d9g7Z9lk6RG3cHVQCT/YBry Aqi/e+gxdTDTSL9EPsMhzgZPVlyhGcKA50I2yVHFWKtizYn/p8uLkzoFHpXCDsgA4738 PViWakLBMxsSl67Itmb7jy6mAHT9w6NbFg0RJpg+PVr+qK0EUN0ENiM7HD9f20HY7xuW fR+Go2N5qPfWFcoEARRvR+vd+pmw/49iue9ySuULH4CMetW/iMWcZrSZq3Dsu7E3f2D7 Px7bG3AMT0Fru4L9K48cybuUI1+0wd4XfXyqOmRaZ/m3d7OUEPbbbKC47pWqC6+YYEU6 NXGw== X-Gm-Message-State: AOAM531xLEZuKtnNvwI1QcnjkiHgLZzRbo6/PDXX0SvABVrztdzSPoUL D6LjZHCnePGGgJI7fH+f4QpbLxaaIVmUJg== X-Google-Smtp-Source: ABdhPJwx/oTbDCDeSxamegsIUOiBhWM2AvzlLAivo8tcfp0T9XMwxtgTAOPCnY3dOL839wgstXfjhA== X-Received: by 2002:a17:902:bf06:b0:14d:8c72:96c6 with SMTP id bi6-20020a170902bf0600b0014d8c7296c6mr7019950plb.156.1654206770666; Thu, 02 Jun 2022 14:52:50 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 64/71] linux-user/aarch64: Verify extra record lock succeeded Date: Thu, 2 Jun 2022 14:48:46 -0700 Message-Id: <20220602214853.496211-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 590f2258b2..711fd19701 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -340,6 +340,9 @@ static int target_restore_sigframe(CPUARMState *env, __get_user(extra_size, &((struct target_extra_context *)ctx)->size); extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0); + if (!extra) { + return 1; + } break; default: From patchwork Thu Jun 2 21:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=N3/1BKJ1; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhC345pTz9s0w for ; Fri, 3 Jun 2022 08:53:51 +1000 (AEST) Received: from localhost ([::1]:60058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwthN-0002Sy-D4 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:53:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskR-0001ip-Af for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:34786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskP-0000yw-JN for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:55 -0400 Received: by mail-pf1-x42c.google.com with SMTP id c196so5821566pfb.1 for ; Thu, 02 Jun 2022 14:52:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G9tBDIOox4Y0NhHvT3VV3KFHeeNFnyNER4ZnNO5qAIM=; b=N3/1BKJ1Ko8TBV5VQwomspi2MMYZSTWZqHyMBd8DEEgcJHJ1Ir5g3Z7D4pf3VqMD4a K9Ijgdq30ZarfSdZyT/d52nxkThBfOaFCGhLcxV6KJsEuVeKiYlT/Dm8m5kOVjJ93+W9 +TVYltkMfUc7/6uW7TxbrrqQCrbZi893QAynu/fKqpqCJA9R351Wt7uMoL5+IENzkWha VVzWqVNJFu6cnnUwq6BLAMvRcjl8sTLe7uFisSwMNtQAyQ+bfw13iATF2RD8f2Rj3pT3 sARvnKsKcdehbvbrEbTcuzf7JZlOJfXKuR1nYf5AyLQH3qzkscK2eytaBbXsaNfE4bia R76w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G9tBDIOox4Y0NhHvT3VV3KFHeeNFnyNER4ZnNO5qAIM=; b=lxZxDiayOrIzCjz085nbi7Ifpa/r4Z+hrr+bPGxkv50Ilh/o/Ni2ngl9a0IBGR5bh0 qtWjamGo1l3AWDW7X9Z17IE49m3griYqzBeFrJkUq7KiXcWX8KzWGzXwmtDTGNVGKzLg MAwF5b+r1ZpGFuYLo/gdlH66bQtIxNgk9Wgnwrx9HZNXcVrQt1h0MtmL08RilAUWlp5D ajQjVBl9Qo8+mC4dEWa8V6Be5u6X1KVxMfcY/f4RmJ9FCTzv1d+ACP8hpcJb8NQNBkOH ClxRKCmzJb1II+5uosqMTJs277rc2ICsjVw1sNrqz/h5M8KJkvsiuU70AhaLE/MReS6s 7TKA== X-Gm-Message-State: AOAM530cw8dn8MCVzwEDdnA1QEkpnAHzLcz7nsq32ue1gov4Xjv8n42e dQoLV+BTZZ0FwbFmmCyKq0bfxEbQvMabpw== X-Google-Smtp-Source: ABdhPJzmclNm9RKHUPGCaBEnavFNqPvgM4+b34jzmvoDoXorx2zfx96xfeiTs/cER8G2s+bdjZcPUg== X-Received: by 2002:a05:6a00:882:b0:510:a043:d4bc with SMTP id q2-20020a056a00088200b00510a043d4bcmr7156291pfj.64.1654206771596; Thu, 02 Jun 2022 14:52:51 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 65/71] linux-user/aarch64: Move sve record checks into restore Date: Thu, 2 Jun 2022 14:48:47 -0700 Message-Id: <20220602214853.496211-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the checks out of the parsing loop and into the restore function. This more closely mirrors the code structure in the kernel, and is slightly clearer. Reject rather than silently skip incorrect VL and SVE record sizes. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 51 +++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 711fd19701..73b15038ad 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -250,12 +250,36 @@ static void target_restore_fpsimd_record(CPUARMState *env, } } -static void target_restore_sve_record(CPUARMState *env, - struct target_sve_context *sve, int vq) +static bool target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, + int size) { - int i, j; + int i, j, vl, vq; - /* Note that SVE regs are stored as a byte stream, with each byte element + if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { + return false; + } + + __get_user(vl, &sve->vl); + vq = sve_vq_cached(env); + + /* Reject mismatched VL. */ + if (vl != vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.SM. */ + if (size <= sizeof(*sve)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + /* + * Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian load * of our 64-bit hunks. */ @@ -277,6 +301,7 @@ static void target_restore_sve_record(CPUARMState *env, } } } + return true; } static int target_restore_sigframe(CPUARMState *env, @@ -287,7 +312,7 @@ static int target_restore_sigframe(CPUARMState *env, struct target_sve_context *sve = NULL; uint64_t extra_datap = 0; bool used_extra = false; - int vq = 0, sve_size = 0; + int sve_size = 0; target_restore_general_frame(env, sf); @@ -321,15 +346,9 @@ static int target_restore_sigframe(CPUARMState *env, if (sve || size < sizeof(struct target_sve_context)) { goto err; } - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = sve_vq_cached(env); - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); - if (size == sve_size) { - sve = (struct target_sve_context *)ctx; - break; - } - } - goto err; + sve = (struct target_sve_context *)ctx; + sve_size = size; + break; case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { @@ -362,8 +381,8 @@ static int target_restore_sigframe(CPUARMState *env, } /* SVE data, if present, overwrites FPSIMD data. */ - if (sve) { - target_restore_sve_record(env, sve, vq); + if (sve && !target_restore_sve_record(env, sve, sve_size)) { + goto err; } unlock_user(extra, extra_datap, 0); return 0; From patchwork Thu Jun 2 21:48:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638523 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ad85cxzt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDh8l5YZdz9s0w for ; Fri, 3 Jun 2022 08:51:50 +1000 (AEST) Received: from localhost ([::1]:55650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtfP-0007ea-8w for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskT-0001it-7r for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:42527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0000zB-1z for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:55 -0400 Received: by mail-pg1-x535.google.com with SMTP id d129so5792672pgc.9 for ; Thu, 02 Jun 2022 14:52:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Il2EY1tYeQoGkETVU6ZiO8+VIpoFNiLUWrHdhwd5vU=; b=ad85cxztuPpNDJ4V2wwFUeNeV89mWgxashtc1pQiWYa/p9FCi8IIe/ppo07Lwm6NiJ MU/0JC5p7ucYCe+js76rlX3VTCv3O3d8pVpEt9s5ymrD4IHlz2fWNXgAvnx63ho/Ur8Y k4dcb9s2vtQiPiIq8dXEjnhtwj01PDZtr/uwm+F70BDqPnFIumpgF5Zq6UISAlxwNDTw tzGZ38BroU0pAb/WSPFm1DXinGA683bD/1mFeWMtZUTpMZ+GbILaqtdW3oXKo+exzrg2 Zs6jU67tmCBrfBDTXiq0t3k5dshCSDymY0PgqZLZ70f+sLerLPjmsClBCZZK7pOsUSzQ MQmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Il2EY1tYeQoGkETVU6ZiO8+VIpoFNiLUWrHdhwd5vU=; b=u51gwr7pU7xOtCLH33qXVJECd/OOu50MVwKTyZuYuN7hi98UzL2VKKqigD/bgYD6lq YmwddrFhWKfrvvaGHsV1LXbDsJPP1KENI2IujzGyfWMov5L1rjawgOjPkNNroDVDMxAM z6VpQcYpJujhlLYKpEYnJ/D0AERGfoxJuqq8lOge/JuRK6NVHmInbvbnb4h/Vk0LigPd IIB9C/0Swr3XssJb+LQHRSsxD3TB0uM4kHZSsdPp5QdPsRy+sK2v8AqpDLTdVfUGjVIA pvYVUgPSfe0f7HwQPZRf/oHZcs4/iVOFQFFO0PN2mSENESpR0n228hIdF+X57NTbysoi Q/sw== X-Gm-Message-State: AOAM532ia+P0ZuGfPCVuK3d2l1kKncXlSjcArZK5WXEzLyAm1tbmz5Hh sI5zCqQq5YcC4JVDlbnFOy0nmt1oiUdSHA== X-Google-Smtp-Source: ABdhPJz/LNQE6KRHEipCCWgc6Fspxi7W1/RQeHRYfMcMxLkIWUGiyShzUWpFvVRyK3HDUKZ9JRgchA== X-Received: by 2002:a05:6a00:140a:b0:4e0:54d5:d01 with SMTP id l10-20020a056a00140a00b004e054d50d01mr7171764pfu.20.1654206772537; Thu, 02 Jun 2022 14:52:52 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 66/71] linux-user/aarch64: Implement SME signal handling Date: Thu, 2 Jun 2022 14:48:48 -0700 Message-Id: <20220602214853.496211-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Set the SM bit in the SVE record on signal delivery, create the ZA record. Restore SM and ZA state according to the records present on return. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 158 ++++++++++++++++++++++++++++++++++-- 1 file changed, 149 insertions(+), 9 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 73b15038ad..79b2fc1cfe 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -104,6 +104,22 @@ struct target_sve_context { #define TARGET_SVE_SIG_FLAG_SM 1 +#define TARGET_ZA_MAGIC 0x54366345 + +struct target_za_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual ZA data immediately follows. */ +}; + +#define TARGET_ZA_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES) +#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \ + (TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N)) +#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \ + TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -207,6 +223,32 @@ static void target_setup_sve_record(struct target_sve_context *sve, } } +static void target_setup_za_record(struct target_za_context *za, + CPUARMState *env, int vq, int size) +{ + int i, j, vl = vq * TARGET_SVE_VQ_BYTES; + + memset(za, 0, sizeof(*za)); + __put_user(TARGET_ZA_MAGIC, &za->head.magic); + __put_user(size, &za->head.size); + __put_user(vl, &za->vl); + + if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return; + } + + /* + * Note that ZA vectors are stored as a byte stream, + * with each byte element at a subsequent address. + */ + for (i = 0; i < vl; ++i) { + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __put_user_e(env->zarray[i].d[j], z + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -252,16 +294,28 @@ static void target_restore_fpsimd_record(CPUARMState *env, static bool target_restore_sve_record(CPUARMState *env, struct target_sve_context *sve, - int size) + int size, int *svcr) { - int i, j, vl, vq; + int i, j, vl, vq, flags; + bool sm; + /* ??? Kernel tests SVE && (!sm || SME); suggest (sm ? SME : SVE). */ if (!cpu_isar_feature(aa64_sve, env_archcpu(env))) { return false; } __get_user(vl, &sve->vl); - vq = sve_vq_cached(env); + __get_user(flags, &sve->flags); + + sm = flags & TARGET_SVE_SIG_FLAG_SM; + if (sm) { + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + vq = sme_vq_cached(env); + } else { + vq = sve_vq_cached(env); + } /* Reject mismatched VL. */ if (vl != vq * TARGET_SVE_VQ_BYTES) { @@ -278,6 +332,8 @@ static bool target_restore_sve_record(CPUARMState *env, return false; } + *svcr = FIELD_DP64(*svcr, SVCR, SM, sm); + /* * Note that SVE regs are stored as a byte stream, with each byte element * at a subsequent address. This corresponds to a little-endian load @@ -304,15 +360,57 @@ static bool target_restore_sve_record(CPUARMState *env, return true; } +static bool target_restore_za_record(CPUARMState *env, + struct target_za_context *za, + int size, int *svcr) +{ + int i, j, vl, vq; + + if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) { + return false; + } + + __get_user(vl, &za->vl); + vq = sme_vq_cached(env); + + /* Reject mismatched VL. */ + if (vl != vq * TARGET_SVE_VQ_BYTES) { + return false; + } + + /* Accept empty record -- used to clear PSTATE.ZA. */ + if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) { + return true; + } + + /* Reject non-empty but incomplete record. */ + if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) { + return false; + } + + *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1); + + for (i = 0; i < vl; ++i) { + uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i); + for (j = 0; j < vq * 2; ++j) { + __get_user_e(env->zarray[i].d[j], z + j, le); + } + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra = NULL; struct target_fpsimd_context *fpsimd = NULL; struct target_sve_context *sve = NULL; + struct target_za_context *za = NULL; uint64_t extra_datap = 0; bool used_extra = false; int sve_size = 0; + int za_size = 0; + int svcr = 0; target_restore_general_frame(env, sf); @@ -350,6 +448,14 @@ static int target_restore_sigframe(CPUARMState *env, sve_size = size; break; + case TARGET_ZA_MAGIC: + if (za || size < sizeof(struct target_za_context)) { + goto err; + } + za = (struct target_za_context *)ctx; + za_size = size; + break; + case TARGET_EXTRA_MAGIC: if (extra || size != sizeof(struct target_extra_context)) { goto err; @@ -381,9 +487,16 @@ static int target_restore_sigframe(CPUARMState *env, } /* SVE data, if present, overwrites FPSIMD data. */ - if (sve && !target_restore_sve_record(env, sve, sve_size)) { + if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; } + if (za && !target_restore_za_record(env, za, za_size, &svcr)) { + goto err; + } + if (env->svcr != svcr) { + env->svcr = svcr; + arm_rebuild_hflags(env); + } unlock_user(extra, extra_datap, 0); return 0; @@ -451,7 +564,8 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, .total_size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs = 0, vq = 0, sve_size = 0; + int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0; + int sve_vq = 0, sve_size = 0, za_vq = 0, za_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; @@ -461,11 +575,22 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, &layout); /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { - vq = sve_vq_cached(env); - sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || + cpu_isar_feature(aa64_sme, env_archcpu(env))) { + sve_vq = sve_vq_cached(env); + sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq), 16); sve_ofs = alloc_sigframe_space(sve_size, &layout); } + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { + /* ZA state needs saving only if it is enabled. */ + za_vq = sme_vq_cached(env); + if (FIELD_EX64(env->svcr, SVCR, ZA)) { + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(za_vq); + } else { + za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0); + } + za_ofs = alloc_sigframe_space(za_size, &layout); + } if (layout.extra_ofs) { /* Reserve space for the extra end marker. The standard end marker @@ -512,7 +637,10 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, target_setup_end_record((void *)frame + layout.extra_end_ofs); } if (sve_ofs) { - target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size); + target_setup_sve_record((void *)frame + sve_ofs, env, sve_vq, sve_size); + } + if (za_ofs) { + target_setup_za_record((void *)frame + za_ofs, env, za_vq, za_size); } /* Set up the stack frame for unwinding. */ @@ -536,6 +664,18 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, env->btype = 2; } + /* + * Invoke the signal handler with both SM and ZA disabled. + * When clearing SM, ResetSVEState, per SMSTOP. + */ + if (FIELD_EX64(env->svcr, SVCR, SM)) { + arm_reset_sve_state(env); + } + if (env->svcr) { + env->svcr = 0; + arm_rebuild_hflags(env); + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); From patchwork Thu Jun 2 21:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638533 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=gjFtRYE1; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhWr0TjJz9sFk for ; Fri, 3 Jun 2022 09:08:24 +1000 (AEST) Received: from localhost ([::1]:60310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtvS-0005P0-25 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 19:08:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskR-0001ir-PZ for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:35725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0000v7-5y for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:55 -0400 Received: by mail-pg1-x532.google.com with SMTP id 129so5817177pgc.2 for ; Thu, 02 Jun 2022 14:52:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HgDKwyzczRHeCVUcDPOzrXt54ML/m2izvxlxKvoxXd8=; b=gjFtRYE1m15O1niQwGJn/daT9cU04KxZLDP03iGS6Xxrtu7RXCl1NDNHVe+btGwc3X ljLXZR/nMraSCnTswRwYCwH9hKlHZfCVcLV2MxRd4a+1ybZVI8zyzvUauB7kMl5N4BZJ OXUY/cw/LLnZQ1Bn0gzIkwcQ46Bm4xWMp4X6WpKErSaWfT6oCQVZrz5QHkZW4zjOXhbG OmPGB47x5uvVjChJz5+jg4prNVljhWyzEXvGuxEX2COD8QQe6na1iS0+JYs4aUrA4mD5 Ea0JxaIOyudykE3mAZYKDegp54dXYz0sVK8dCAOjn62UjufeTkJ+SQgMzfOIj0LCB3uU f+9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HgDKwyzczRHeCVUcDPOzrXt54ML/m2izvxlxKvoxXd8=; b=iR75zNZ+hOz4prlGfinf76tBgjOdQPpGWozmbxBV7No0DkJhMvppo15urqKIo3jV38 lZoV+8M2LMNPrtMZTEvJ04fW/yuwFEr6/R1c78FrJijbF82gqJr0dinpsacxzBW9MU26 64pjYf3Ad0XpI8Isv5sHdmKut2M2rUEIqpyYFRG6aX2BEEK8uK10rca3UiBmDBdkWtLb DwoDKPGTt9SL7GErDzzMe901+95vT5d2OHpzMrKgAfwYSK4x7jvt9EOkkWnB+Ho+64Im MN57yt9NWlNaMElPXLx6/K7AVljYLnAjk0akVRnWCE4Op2bhfLR/hE5BUZBazAuiRSzE pEQQ== X-Gm-Message-State: AOAM533NZej7UkpF0J8RsJVDa8iAfPdjqPSZHqDLeb/FdjLXrkGREY7w Jtj88I+dy0U3OI0WpKdqc1EIbl9Y8K+ewA== X-Google-Smtp-Source: ABdhPJywTG85rB6+y10175Il5a8+2W8bmN2mXMqznvk+9DtYybnLHbfvbZHJSEvVmHQbWy6O5YEIbg== X-Received: by 2002:a62:3646:0:b0:51b:91c7:fd4a with SMTP id d67-20020a623646000000b0051b91c7fd4amr15589319pfa.78.1654206773232; Thu, 02 Jun 2022 14:52:53 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 67/71] linux-user: Rename sve prctls Date: Thu, 2 Jun 2022 14:48:49 -0700 Message-Id: <20220602214853.496211-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add "sve" to the sve prctl functions, to distinguish them from the coming "sme" prctls with similar names. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 8 ++++---- linux-user/syscall.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index fdd973e07d..3c2ef734fe 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,7 +6,7 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H -static abi_long do_prctl_get_vl(CPUArchState *env) +static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { @@ -14,9 +14,9 @@ static abi_long do_prctl_get_vl(CPUArchState *env) } return -TARGET_EINVAL; } -#define do_prctl_get_vl do_prctl_get_vl +#define do_prctl_sve_get_vl do_prctl_sve_get_vl -static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) +static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) { /* * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT. @@ -47,7 +47,7 @@ static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2) } return -TARGET_EINVAL; } -#define do_prctl_set_vl do_prctl_set_vl +#define do_prctl_sve_set_vl do_prctl_sve_set_vl static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f55cdebee5..a7f41ef0ac 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6365,11 +6365,11 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_set_fp_mode #define do_prctl_set_fp_mode do_prctl_inval1 #endif -#ifndef do_prctl_get_vl -#define do_prctl_get_vl do_prctl_inval0 +#ifndef do_prctl_sve_get_vl +#define do_prctl_sve_get_vl do_prctl_inval0 #endif -#ifndef do_prctl_set_vl -#define do_prctl_set_vl do_prctl_inval1 +#ifndef do_prctl_sve_set_vl +#define do_prctl_sve_set_vl do_prctl_inval1 #endif #ifndef do_prctl_reset_keys #define do_prctl_reset_keys do_prctl_inval1 @@ -6434,9 +6434,9 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, case PR_SET_FP_MODE: return do_prctl_set_fp_mode(env, arg2); case PR_SVE_GET_VL: - return do_prctl_get_vl(env); + return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: - return do_prctl_set_vl(env, arg2); + return do_prctl_sve_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; From patchwork Thu Jun 2 21:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=battyZXz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhMl2YMDz9sFk for ; Fri, 3 Jun 2022 09:01:23 +1000 (AEST) Received: from localhost ([::1]:47496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtof-0004wO-Cs for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 19:01:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskT-0001iv-0M for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:33280) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0000wE-U8 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:56 -0400 Received: by mail-pl1-x630.google.com with SMTP id s12so5586340plp.0 for ; Thu, 02 Jun 2022 14:52:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LhGeTTc5zjX7U0kCCpIqQRg/F4IwvyDy51EbtKdkfIA=; b=battyZXzGMcXgwqTIxlqa+WlrhE0J0uLCTA1YJTvqZrdmFkCXwqDUnHCv9iVFquWOF 3juQYSw9sSHjuCyj2OvaiOVNp8gh9fVGiiQNxVi5A5lzer54jF1EKrOacJERNvLOaVhG sRpm53ADVTZlvZFHRrx8zA8mF77tadfwfftyQuuC4AFPZrUpfOwPNSPld0khb2FT3SxZ +JfaRlouYCOXZ+64T4tyFS2eSQOEezaHSYBr97ji9BeWvm9gd5Cyf9ThY0QqDERsV/ne sfMb/nhqn/pEPlbxkj+pKliGqfCu30TzXBDAH/geXSumDabjyMX0ttVF8+2FdNc12B+R xAnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LhGeTTc5zjX7U0kCCpIqQRg/F4IwvyDy51EbtKdkfIA=; b=PANLFupl5DXx4HpnNzbjXq83s9F29RjS/MjXQ03ddE3HP62AU1pKOF1shjN0gFp//L 5ajwyyEbFM+tzGOmxunG7FECzUJWfIEdN2rhBYOPaJfyR9BnOXxcSgF1R3leemGXBkko oGA6TFSKvy7wbRQELPT0zrglLV3v4PDDaDSboeXoXFbtNYe7wv1emPJliqVvvAIwSt5Q tGuRY2av6Yl7CdAK9m8Gqax0ANsE/vf70r1YnRtwZyECMM+rGiWqqLqD7BvvwxywRht4 cxuYoxgut9MJZhrYZMD2b5e8I4uIwLT2LjNK6G74OmmmflBk3D85STqkj2bhkQp4YZuY 9CZQ== X-Gm-Message-State: AOAM531l5qqlaFbcD91L5ci27sYBFvov6GJ3PkFRXtt9MHsTIC4rqsiG UO9G8Zmu+OiBMybqgJuRAn6nxrvqh3sunA== X-Google-Smtp-Source: ABdhPJw/y0lDCDTBMOXvtI25QzbV9ycZFD0sshQpJzmFTDyA72qxsDslKB6PAPnbOp5AibNgLrgVQA== X-Received: by 2002:a17:902:b588:b0:161:64fe:af8c with SMTP id a8-20020a170902b58800b0016164feaf8cmr6973422pls.26.1654206774062; Thu, 02 Jun 2022 14:52:54 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 68/71] linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL Date: Thu, 2 Jun 2022 14:48:50 -0700 Message-Id: <20220602214853.496211-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These prctl set the Streaming SVE vector length, which may be completely different from the Normal SVE vector length. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_prctl.h | 48 +++++++++++++++++++++++++++++++ linux-user/syscall.c | 16 +++++++++++ 2 files changed, 64 insertions(+) diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 3c2ef734fe..01282bd78c 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -10,6 +10,7 @@ static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); if (cpu_isar_feature(aa64_sve, cpu)) { + /* PSTATE.SM is always unset on syscall entry. */ return sve_vq_cached(env) * 16; } return -TARGET_EINVAL; @@ -27,6 +28,7 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { uint32_t vq, old_vq; + /* PSTATE.SM is always unset on syscall entry. */ old_vq = sve_vq_cached(env); /* @@ -49,6 +51,52 @@ static abi_long do_prctl_sve_set_vl(CPUArchState *env, abi_long arg2) } #define do_prctl_sve_set_vl do_prctl_sve_set_vl +static abi_long do_prctl_sme_get_vl(CPUArchState *env) +{ + ARMCPU *cpu = env_archcpu(env); + if (cpu_isar_feature(aa64_sme, cpu)) { + return sme_vq_cached(env) * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_get_vl do_prctl_sme_get_vl + +static abi_long do_prctl_sme_set_vl(CPUArchState *env, abi_long arg2) +{ + /* + * We cannot support either PR_SME_SET_VL_ONEXEC or PR_SME_VL_INHERIT. + * Note the kernel definition of sve_vl_valid allows for VQ=512, + * i.e. VL=8192, even though the architectural maximum is VQ=16. + */ + if (cpu_isar_feature(aa64_sme, env_archcpu(env)) + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { + int vq, old_vq; + + old_vq = sme_vq_cached(env); + + /* + * Bound the value of vq, so that we know that it fits into + * the 4-bit field in SMCR_EL1. Because PSTATE.SM is cleared + * on syscall entry, we are not modifying the current SVE + * vector length. + */ + vq = MAX(arg2 / 16, 1); + vq = MIN(vq, 16); + env->vfp.smcr_el[1] = + FIELD_DP64(env->vfp.smcr_el[1], SMCR, LEN, vq - 1); + vq = sme_vq_cached(env); + + if (old_vq != vq) { + /* PSTATE.ZA state is cleared on any change to VQ. */ + env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); + arm_rebuild_hflags(env); + } + return vq * 16; + } + return -TARGET_EINVAL; +} +#define do_prctl_sme_set_vl do_prctl_sme_set_vl + static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2) { ARMCPU *cpu = env_archcpu(env); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a7f41ef0ac..e8d6e20b85 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6346,6 +6346,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr) #ifndef PR_SET_SYSCALL_USER_DISPATCH # define PR_SET_SYSCALL_USER_DISPATCH 59 #endif +#ifndef PR_SME_SET_VL +# define PR_SME_SET_VL 63 +# define PR_SME_GET_VL 64 +# define PR_SME_VL_LEN_MASK 0xffff +# define PR_SME_VL_INHERIT (1 << 17) +#endif #include "target_prctl.h" @@ -6386,6 +6392,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2) #ifndef do_prctl_set_unalign #define do_prctl_set_unalign do_prctl_inval1 #endif +#ifndef do_prctl_sme_get_vl +#define do_prctl_sme_get_vl do_prctl_inval0 +#endif +#ifndef do_prctl_sme_set_vl +#define do_prctl_sme_set_vl do_prctl_inval1 +#endif static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6437,6 +6449,10 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, return do_prctl_sve_get_vl(env); case PR_SVE_SET_VL: return do_prctl_sve_set_vl(env, arg2); + case PR_SME_GET_VL: + return do_prctl_sme_get_vl(env); + case PR_SME_SET_VL: + return do_prctl_sme_set_vl(env, arg2); case PR_PAC_RESET_KEYS: if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; From patchwork Thu Jun 2 21:48:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=e0Dzgjp6; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhFG6MXjz9s0w for ; Fri, 3 Jun 2022 08:55:46 +1000 (AEST) Received: from localhost ([::1]:35792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtjE-0005Dj-UG for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:55:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskW-0001jF-Cy for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:53:03 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:41937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskS-00010X-1w for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:53:00 -0400 Received: by mail-pf1-x42c.google.com with SMTP id p8so5801462pfh.8 for ; Thu, 02 Jun 2022 14:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8ss3EaTY1TKvXRQ5t3puVtJ4SylwysppKIF75i7g6zo=; b=e0Dzgjp6I8jGOEppACdfsKJaSp7FXZyc8E20KQp3Cuhp7s8vPjzW0NSt3pLhGncxFX tyImvZGGwCsfTg76sDRvWAX/fbxkgIxjLRZ7usEyBJu7kUuxLF4It65jm5QZFEDMltvE YUtx8l010oEn9Uon4FXWl/QK442US0lIavmq92Ulrsllh5id14U3VpgdL7UOVoSDP7bo 8jZjCR8uuqrZCED9bc4X+Qy9xu5mT1/BYpAmdGTJgUfUpiC0LKFMIryOGuQie1TI/i3F BvKUk8dZVfb6Iby+kEO259A1Atr0odW86Q3PV8abusC0D8COa7aRwbVXlFMcZUeKPf43 v25g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8ss3EaTY1TKvXRQ5t3puVtJ4SylwysppKIF75i7g6zo=; b=y3yYmSGVkgQkTCFzCSrT2LYqi2iA988LQkxQknuGAqCW4tk5yt17wkIXvo7idMM221 CSmcp19LvK7zAvi84g6LTTa/4FCC5q5ALToOGmANckLCUAR9c2Ltrd+N59fS5l4AWRyy NaL2E+6xu2a/ELTf/+gX4qiJoRYId24kBzuarsLb+oV7FWjebTMGNHiuJPAiWmXJFQdQ Zj92yjnbfk4V8EHbhyuhRIvuHK6JMV89qp9OErEp9pOfV+n6v76qz1XcxN5SsBtMfN4l BpnFXgkadgjTjwYDIobMjdGz9D4RQH5631FIftrCjIYjxAPg+fgmaMCaWY+R7j5akgpC wEbg== X-Gm-Message-State: AOAM532FMBGQ75a+vdZ4JufaxtzAB/hEZcwjvOkKYZXzepIc7LR6ge68 1GLS7+LNZUeoP5hP4uN+URWr0xbROSR6WA== X-Google-Smtp-Source: ABdhPJzcTCLQv16bP3zb47Y/k2mpc3/POxhn5q9iSx21uiCXXGFi3nHX8kVGxj7HP+yOemrA58OJzw== X-Received: by 2002:a62:1784:0:b0:51b:bc40:28a7 with SMTP id 126-20020a621784000000b0051bbc4028a7mr7121646pfx.55.1654206774809; Thu, 02 Jun 2022 14:52:54 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 69/71] target/arm: Only set ZEN in reset if SVE present Date: Thu, 2 Jun 2022 14:48:51 -0700 Message-Id: <20220602214853.496211-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" There's no reason to set CPACR_EL1.ZEN if SVE disabled. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 75295a14a3..5cb9f9f02c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -203,11 +203,10 @@ static void arm_cpu_reset(DeviceState *dev) /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, CPACR_EL1, FPEN, 3); - /* and to the SVE instructions */ - env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, - CPACR_EL1, ZEN, 3); - /* with reasonable vector length */ + /* and to the SVE instructions, with default vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } /* From patchwork Thu Jun 2 21:48:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=v6AINVzx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhVT5N48z9sFk for ; Fri, 3 Jun 2022 09:07:13 +1000 (AEST) Received: from localhost ([::1]:58138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtuJ-0003xO-Q3 for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 19:07:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskU-0001ix-DE for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:52111) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskS-00010v-UP for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:58 -0400 Received: by mail-pj1-x102d.google.com with SMTP id cx11so6034632pjb.1 for ; Thu, 02 Jun 2022 14:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gRUKfNIQaiiNP0vvAyDKnRSVA5VX9NVJiBVrOsiCdko=; b=v6AINVzxBuJPljN/SysCtACzcHObWIaQO/X+pGee1QnopmaCe3p5t9C7TyYxo/430a B22A9xXPylrX881YI2Lg8+5/maCylodRbB7gvIHVtQcR1d/MhbROzR3OQz0vjNSwk1DM ppVMhErMuvxMLZVXcyQjv5TM0GmGwU7DxieiiPnArQfl3OFjEf2gmygiUjeap7NcskJI mCBkVkoZqz3dNftQ/euOXYy8cgKm7IIP5hFR/raHzv7wSQMZlaYmgjuATqvsEqZSk1lt Bhl6dC1CBaGHPMExbvNiS/F0re/x66E9y6iM2g2SvhyuRHyWVMIVYBhpW0AQ2l74wYGY xR8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gRUKfNIQaiiNP0vvAyDKnRSVA5VX9NVJiBVrOsiCdko=; b=MdIMFdoso2pFWsRRYHs74KdoAKV+yg2H3nRhVT7EyBbHB7LKSi7wA+cPHBLYJFBIK+ R9ioHgzBqILyBbfS3W0J2fC5UQdmdkTOXOv9ilQGqGrcklfk/4tNibqaoqioU/3gQrUs XdOI3W1cgAGJ9q8r/tq36mD9lKpYoXLvstFztJqmmwADPSfMZEGlXonIvsPWBQco4b+n 9u0B2V7YYJfbFayPgUdzMLdYM60Wj2D7pzoXMV/ZISjmqc35oSx63vF/DS3Kx4vkWQIc 4jTLcYq/PZgd2h8jEmN4HydD01P6nggBo6d12c/L8ufac8Ks7oGaQcWTNx2uEGmVs7nw rOgA== X-Gm-Message-State: AOAM531uhOHpv/LyVFM8IiCp4hxcBtjb+IrHjqDWg6aXOHMSUCxsO46E uPR5SQqlXHY3+NVjhbzBRmD6Zf5HF9dwwg== X-Google-Smtp-Source: ABdhPJzU2Ll9rbIaiw4WwBsjEES5FtobEromxBhcVeHgpJFcRtg7ebHFXsW6ygMEUtUJ+dyeZP5EMA== X-Received: by 2002:a17:902:7004:b0:161:f216:4f3f with SMTP id y4-20020a170902700400b00161f2164f3fmr6965131plk.98.1654206775691; Thu, 02 Jun 2022 14:52:55 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 70/71] target/arm: Enable SME for user-only Date: Thu, 2 Jun 2022 14:48:52 -0700 Message-Id: <20220602214853.496211-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5cb9f9f02c..13b008547e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -209,6 +209,17 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; } + /* and for SME instructions, with default vector length, and TPIDR2 */ + if (cpu_isar_feature(aa64_sme, cpu)) { + env->cp15.sctlr_el[1] |= SCTLR_EnTP2; + env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, SMEN, 3); + env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; + if (cpu_isar_feature(aa64_sme_fa64, cpu)) { + env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], + SMCR, FA64, 1); + } + } /* * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. From patchwork Thu Jun 2 21:48:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1638525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=mRnDmgP+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LDhBJ3Grbz9sFr for ; Fri, 3 Jun 2022 08:53:12 +1000 (AEST) Received: from localhost ([::1]:58336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtgk-0001Ik-Ej for incoming@patchwork.ozlabs.org; Thu, 02 Jun 2022 18:53:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskV-0001jB-MH for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:53:03 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:41757) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskT-0000uo-A7 for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: by mail-pj1-x1030.google.com with SMTP id l20-20020a17090a409400b001dd2a9d555bso5911054pjg.0 for ; Thu, 02 Jun 2022 14:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DykCJozY64Fe8oG2Osy4GtewqpVyxda/M4nkZEjhEDk=; b=mRnDmgP++ifXN/MW014dfaGCMya65kA+ZThMcQz/YjIaDsE7mfwI2Hi/EsIUSUgs0u AoiMdY+mig/N3OlaPZXd7RAUwbuqH+eDyNa7bfBgZmCoqLZ2aNZWHZqY90ciAi/QXDjy xpj5245XQjrN72rj/F4K5QagSQGcf34bFB8cS71TaS7FljRs7Ji/8w2bhiOSlDHj+tY6 kgBPuTbr9KDSLUy27ygDC3XhAJcwGvsWaRA7vSKlvIq6ns4WsPIWUCHcPyUB1pUsyuva HVDi99XbaBv4LW6iFv5RLjwj6GZzZIzb7OfGVXBg9c0Grq33Cx56Cvac7/8QRIKMWcoR L91Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DykCJozY64Fe8oG2Osy4GtewqpVyxda/M4nkZEjhEDk=; b=HPC0H8A1W976pmlCgKGoSQXS+BLqLTVIKKlp+Ovb33KXrPsGpvm5CQFoNdMKf1l+XX ag91n3sleE3SYIYoYYGV4aIYbv4vWdyCVglXzXO5nwbN2ga+MkD/iphuh3QkXFJIYVCZ oo3YfSCt/6yUUANh4PRwFhTf1omUYvKpX2l5K8UtlGWtB84xvWE8RXwCiT5hsvbI/BFT ELm2gL3sPA/X1gXjQscnv7E9dDPW5j5sFSXkES3PNaDLfawjywR3S+DrHmMIu9WeRZrs FoknXdJ5TCnvQj6pDmEwM8HASa5AzCZvhYgN0wQS1Pw3KFrDkKupldGVwJj2hkvm32eU TGrg== X-Gm-Message-State: AOAM533PgNpUyn0IO8Z7ishJ5lAaBwHh+ML6W+55bthbZ7SBgK13x/oE QOcjVEE8sPZo73aJDaCBGA3qkufG6Fif9Q== X-Google-Smtp-Source: ABdhPJzu6VmXiz7XI9OoyX5NvZtg/8lbLVUYga3DgMHxrbFWet1JfnWDRGKG0owwa9X7bWeyHMU79Q== X-Received: by 2002:a17:902:7d8e:b0:162:22ff:495b with SMTP id a14-20020a1709027d8e00b0016222ff495bmr6997877plm.1.1654206776513; Thu, 02 Jun 2022 14:52:56 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 71/71] linux-user/aarch64: Add SME related hwcap entries Date: Thu, 2 Jun 2022 14:48:53 -0700 Message-Id: <20220602214853.496211-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- linux-user/elfload.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f7eae357f4..8135960305 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -601,6 +601,18 @@ enum { ARM_HWCAP2_A64_RNG = 1 << 16, ARM_HWCAP2_A64_BTI = 1 << 17, ARM_HWCAP2_A64_MTE = 1 << 18, + ARM_HWCAP2_A64_ECV = 1 << 19, + ARM_HWCAP2_A64_AFP = 1 << 20, + ARM_HWCAP2_A64_RPRES = 1 << 21, + ARM_HWCAP2_A64_MTE3 = 1 << 22, + ARM_HWCAP2_A64_SME = 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 = 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 = 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 = 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 = 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 = 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 = 1 << 29, + ARM_HWCAP2_A64_SME_FA64 = 1 << 30, }; #define ELF_HWCAP get_elf_hwcap() @@ -670,6 +682,14 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); return hwcaps; }