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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:27 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 1/9] RISC-V: Simplify memory model code [PR 100265] Date: Fri, 27 May 2022 08:07:15 +0200 Message-Id: <20220527060723.235095-2-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" We don't have any special treatment of MEMMODEL_SYNC_* values, so let's hide them behind the memmodel_base() function. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_amo_acquire): Ignore MEMMODEL_SYNC_* values. * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Likewise. * config/riscv/riscv.c (riscv_print_operand): Eliminate MEMMODEL_SYNC_* values by calling memmodel_base(). --- gcc/config/riscv/riscv.cc | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f83dc796d88..1a130f1fe3b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3578,20 +3578,17 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) acquire portion of memory model MODEL. */ static bool -riscv_memmodel_needs_amo_acquire (enum memmodel model) +riscv_memmodel_needs_amo_acquire (const enum memmodel model) { switch (model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: return true; case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: case MEMMODEL_RELAXED: return false; @@ -3604,20 +3601,17 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) implement the release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_release_fence (const enum memmodel model) { switch (model) { case MEMMODEL_ACQ_REL: case MEMMODEL_SEQ_CST: - case MEMMODEL_SYNC_SEQ_CST: case MEMMODEL_RELEASE: - case MEMMODEL_SYNC_RELEASE: return true; case MEMMODEL_ACQUIRE: case MEMMODEL_CONSUME: - case MEMMODEL_SYNC_ACQUIRE: case MEMMODEL_RELAXED: return false; @@ -3644,6 +3638,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) { machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); + const enum memmodel model = memmodel_base (INTVAL (op)); switch (letter) { @@ -3663,12 +3658,12 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); break; case 'F': - if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) + if (riscv_memmodel_needs_release_fence (model)) fputs ("fence iorw,ow; ", file); break; From patchwork Fri May 27 06:07:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636137 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=sXpPvkqX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L8ZCC6ssVz9sBB for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:28 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 2/9] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] Date: Fri, 27 May 2022 08:07:16 +0200 Message-Id: <20220527060723.235095-3-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The ratified A extension supports '.aq', '.rl' and '.aqrl' as memory ordering suffixes. Let's emit them in case we get a '%A' conversion specifier for riscv_print_operand(). As '%A' was already used for a similar, but restricted, purpose (only '.aq' was emitted so far), this does not require any other changes. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_amo_acquire): Remove function. * config/riscv/riscv.c (riscv_print_amo_memory_ordering_suffix): Add function to emit AMO memory ordering suffixes. * config/riscv/riscv.c (riscv_print_operand): Call riscv_print_amo_memory_ordering_suffix() instead of riscv_memmodel_needs_amo_acquire(). --- gcc/config/riscv/riscv.cc | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1a130f1fe3b..983a567c69c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3574,24 +3574,26 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } -/* Return true if the .AQ suffix should be added to an AMO to implement the - acquire portion of memory model MODEL. */ +/* Print the memory ordering suffix for AMOs. */ -static bool -riscv_memmodel_needs_amo_acquire (const enum memmodel model) +static void +riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) { switch (model) { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_ACQUIRE: + case MEMMODEL_RELAXED: + break; case MEMMODEL_CONSUME: - return true; - + case MEMMODEL_ACQUIRE: + fputs (".aq", file); + break; case MEMMODEL_RELEASE: - case MEMMODEL_RELAXED: - return false; - + fputs (".rl", file); + break; + case MEMMODEL_ACQ_REL: + case MEMMODEL_SEQ_CST: + fputs (".aqrl", file); + break; default: gcc_unreachable (); } @@ -3658,8 +3660,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) - fputs (".aq", file); + riscv_print_amo_memory_ordering_suffix (file, model); break; case 'F': From patchwork Fri May 27 06:07:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636138 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=ns1rCM49; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:29 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 3/9] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] Date: Fri, 27 May 2022 08:07:17 +0200 Message-Id: <20220527060723.235095-4-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" A previous patch took care, that the proper memory ordering suffixes for AMOs are emitted. Therefore there is no reason to keep the fence generation mechanism for release operations. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Remove function. * config/riscv/riscv.c (riscv_print_operand): Remove %F format specifier. * config/riscv/sync.md: Remove %F format specifier uses. --- gcc/config/riscv/riscv.cc | 29 ----------------------------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 8 insertions(+), 37 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 983a567c69c..5bb22044ce9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3599,29 +3599,6 @@ riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ - -static bool -riscv_memmodel_needs_release_fence (const enum memmodel model) -{ - switch (model) - { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_RELEASE: - return true; - - case MEMMODEL_ACQUIRE: - case MEMMODEL_CONSUME: - case MEMMODEL_RELAXED: - return false; - - default: - gcc_unreachable (); - } -} - /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping @@ -3629,7 +3606,6 @@ riscv_memmodel_needs_release_fence (const enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -3663,11 +3639,6 @@ riscv_print_operand (FILE *file, rtx op, int letter) riscv_print_amo_memory_ordering_suffix (file, model); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 86b41e6b00a..ddaeda0116d 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -65,7 +65,7 @@ (define_insn "atomic_store" (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set (attr "length") (const_int 8))]) (define_insn "atomic_" @@ -76,8 +76,8 @@ (define_insn "atomic_" (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + "amo.%A2 zero,%z1,%0" +) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -89,8 +89,8 @@ (define_insn "atomic_fetch_" (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amo.%A3 %0,%z2,%1" +) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,8 +101,8 @@ (define_insn "atomic_exchange" (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amoswap.%A3 %0,%z2,%1" +) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -115,7 +115,7 @@ (define_insn "atomic_cas_value_strong" UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + "1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" [(set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" From patchwork Fri May 27 06:07:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636139 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:30 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 4/9] RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] Date: Fri, 27 May 2022 08:07:18 +0200 Message-Id: <20220527060723.235095-5-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Using AMOSWAP as atomic store does not allow us to do sub-word accesses. Further, it is not consistent with our atomic_load () implementation. The benefit of AMOSWAP is that the resulting code sequence will be smaller (comapred to FENCE+STORE), however, this does not weight out for the lack of sub-word accesses. Additionally, HW implementors have claimed that an optimal implementation AMOSWAP is slightly more expensive than FENCE+STORE. So let's use STORE instead of AMOSWAP. gcc/ PR 100265 * config/riscv/sync.md (atomic_store): Remove. --- gcc/config/riscv/sync.md | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ddaeda0116d..86f4cef6af9 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -57,17 +57,6 @@ (define_insn "mem_thread_fence_1" ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. -(define_insn "atomic_store" - [(set (match_operand:GPR 0 "memory_operand" "=A") - (unspec_volatile:GPR - [(match_operand:GPR 1 "reg_or_0_operand" "rJ") - (match_operand:SI 2 "const_int_operand")] ;; model - UNSPEC_ATOMIC_STORE))] - "TARGET_ATOMIC" - "amoswap.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) - (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Fri May 27 06:07:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636143 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=rlRAKJmg; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L8ZGb2tn2z9sBB for ; Fri, 27 May 2022 16:12:39 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 39D7A382D478 for ; Fri, 27 May 2022 06:12:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39D7A382D478 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653631957; bh=ihAGyMR15/z7NYIasGROg0xxxIUpVp6Atp4Ka3jCFPk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=rlRAKJmg/abfOGYvhSTOEkBAB+PwREyvBkBdX1f0fVNytLiUGNul6hq7FhTQlXitw 4M+/elMP7wWD+pNh42Zc75FR/kH4+uqzPiUurr+H3pA6smJ0xSBbAq8nm+Cq5MrMuH l1WYC6b/a4KNbDLACOrrIpyNd3vAF5oZ6TcAcZiM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by sourceware.org (Postfix) with ESMTPS id B3A03382D475; Fri, 27 May 2022 06:07:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B3A03382D475 Received: by mail-wr1-f41.google.com with SMTP id i9so4512409wrc.13; Thu, 26 May 2022 23:07:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ihAGyMR15/z7NYIasGROg0xxxIUpVp6Atp4Ka3jCFPk=; b=KgqdUFYPU+pusn+RDc+QcxBrSJ3FCCLWgXi2kuKOWV+3PGyIyo8hHszAvpgUpOGNh7 cwIBr/YMycowSBzGh3JijrmRkN9O1f3umnN2kSUtMpUpTlg3bzkYO7068qP/8vSfaCTf ePOziebIl3ae3zm7Kxlo3hkY+3yQFZeGcWRBA8rpqVxQNrJw1GtfTWh/8isJrYZvtJJ2 lMCUewsbnuviS2pjx/PB7zfevnJxsBY7CVl5xuwzbLx4zPtG/IodoTEqZfej+HRvFSYY RfhkUuKguwipGtp7Q4N0JkTZ9T/ZIOt8lWsxwNKQ+5Xg5JE6fQLLTyT6Mj4daa99Op5Q UPCg== X-Gm-Message-State: AOAM532yAlVChK36qcpXzI9va2Q5WyJgomMErhE+QOOAhFv0hkMqk4JN q2a48B2ajzyEOOhvxO8VzU4NM102JV3XfaYG X-Google-Smtp-Source: ABdhPJw1/jPAbTE0EG/tc9NjfvH/GfZ8Bsbfxgefon7JjLPx7PO9+xa0xy3/gMWx+GsUIZtVknZJnA== X-Received: by 2002:a05:6000:1685:b0:20f:e86d:2c96 with SMTP id y5-20020a056000168500b0020fe86d2c96mr16557813wrd.587.1653631652470; Thu, 26 May 2022 23:07:32 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:32 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 5/9] RISC-V: Emit fences according to chosen memory model [PR 100265] Date: Fri, 27 May 2022 08:07:19 +0200 Message-Id: <20220527060723.235095-6-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" mem_thread_fence gets the desired memory model as operand. Let's emit fences according to this value (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). gcc/ PR 100265 * config/riscv/sync.md (mem_thread_fence): Emit fences according to given operand. * config/riscv/sync.md (mem_fence): Add INSNs for different fence flavours. * config/riscv/sync.md (mem_thread_fence_1): Remove. --- gcc/config/riscv/sync.md | 41 +++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 86f4cef6af9..ae80f94f2e0 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -34,26 +34,41 @@ (define_code_attr atomic_optab ;; Memory barriers. (define_expand "mem_thread_fence" - [(match_operand:SI 0 "const_int_operand" "")] ;; model + [(match_operand:SI 0 "const_int_operand")] ;; model "" { - if (INTVAL (operands[0]) != MEMMODEL_RELAXED) - { - rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); - MEM_VOLATILE_P (mem) = 1; - emit_insn (gen_mem_thread_fence_1 (mem, operands[0])); - } + enum memmodel model = memmodel_from_int (INTVAL (operands[0])); + if (!(is_mm_relaxed (model))) + emit_insn (gen_mem_fence (operands[0])); DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. -(define_insn "mem_thread_fence_1" +(define_expand "mem_fence" + [(set (match_dup 1) + (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")] + UNSPEC_MEMORY_BARRIER))] + "" +{ + operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (operands[1]) = 1; +}) + +(define_insn "*mem_fence" [(set (match_operand:BLK 0 "" "") - (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) - (match_operand:SI 1 "const_int_operand" "")] ;; model + (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] + UNSPEC_MEMORY_BARRIER))] "" - "fence\tiorw,iorw") +{ + enum memmodel model = memmodel_from_int (INTVAL (operands[1])); + if (is_mm_consume (model) || is_mm_acquire (model)) + return "fence\tr, rw"; + else if (is_mm_release (model)) + return "fence\trw, w"; + else if (is_mm_acq_rel (model)) + return "fence.tso"; + else + return "fence\trw, rw"; +}) ;; Atomic memory operations. From patchwork Fri May 27 06:07:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636146 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=dcfuV+HS; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L8ZHj1spLz9sBB for ; Fri, 27 May 2022 16:13:35 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9F6A8382D463 for ; Fri, 27 May 2022 06:13:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9F6A8382D463 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653632013; bh=96Sg1HDD6p5RVeu02AVdYDD0i8wF6J6/eh6yGN+ZNy8=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=dcfuV+HSFz4fajbfau58Sk2ZGEJF8pkBj7CRsey2L+CTbCMOAo1v9g6C/IrGqea4H 8SxCPs2vGbZd+iK3hoB3vZIZa3n9WYx9cvlDAMpw5jqv8a86D/E+DbLRn0MMBoxeBr hNpD6toefr2Ow6o98QVnvgv7Saxj6CtHOrjjUQkE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by sourceware.org (Postfix) with ESMTPS id E6F9C382D47B; Fri, 27 May 2022 06:07:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E6F9C382D47B Received: by mail-wm1-f45.google.com with SMTP id d5-20020a05600c34c500b0039776acee62so1709994wmq.1; Thu, 26 May 2022 23:07:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=96Sg1HDD6p5RVeu02AVdYDD0i8wF6J6/eh6yGN+ZNy8=; b=V30fwYa/w5j/AOY9L9dW4jYEPIMdbL/WSzT8sayIxCldckXyp9fO2bn3E3UnG9YQyi BJ3qp0M+BrMl2EVm/CH4vwLHz5VkBvFggBee5M9g+qH7I/uvFBBKQb+r8q2aUZO/Fu4l yv+ngaUwAo4ZIewMKFdWt6eh7qpP6XqfsztZscjqE/6KUGOpc+q9eHoxAlhe1TXmckxk y/f4HIyQ4W+0aWW/ti+6zBkxiT2SEMiyiUfnRRtehVIdnKvQ5BJOAsO4XFmhcRjUcow6 fBc9/+LShWcd4vD24GG8M+QECNFPuXA+tsDJVVpfJIF7D/SXsEAdWPW7d36m/m3YLz7b +LPw== X-Gm-Message-State: AOAM531X4v4mxKgHsqQEMh3esgu9xCZ/idwAF8tJvtQ9rJLsmco5ECen kjByEbRmCoxeI0RQQvYtyF4ImWUFeOqQbsRp X-Google-Smtp-Source: ABdhPJxTWCKQpa9KLzEipNSY/+fqnT627e2+Tu5WloH8x9F5uttUkxFzpm1xeVCNHPla3XYr3x0SDg== X-Received: by 2002:a05:600c:3c8b:b0:397:2db3:97a8 with SMTP id bg11-20020a05600c3c8b00b003972db397a8mr5284798wmb.132.1653631653697; Thu, 26 May 2022 23:07:33 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:33 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 6/9] RISC-V: Implement atomic_{load,store} [PR 100265] Date: Fri, 27 May 2022 08:07:20 +0200 Message-Id: <20220527060723.235095-7-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" A recent commit introduced a mechanism to emit proper fences for RISC-V. Additionally, we already have emit_move_insn (). Let's reuse this code and provide atomic_load and atomic_store for RISC-V (as defined in section "Code Porting and Mapping Guidelines" of the unpriv spec). Note, that this works also for sub-word atomics. gcc/ PR 100265 * config/riscv/sync.md (atomic_load): New. * config/riscv/sync.md (atomic_store): New. --- gcc/config/riscv/sync.md | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ae80f94f2e0..9eb0dde9086 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ (define_c_enum "unspec" [ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -72,6 +73,46 @@ (define_insn "*mem_fence" ;; Atomic memory operations. +(define_expand "atomic_load" + [(set (match_operand:ANYI 0 "register_operand" "=r") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "" + { + rtx target = operands[0]; + rtx mem = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_SEQ_CST))); + emit_move_insn (target, mem); + if (is_mm_acquire (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_ACQUIRE))); + + DONE; +}) + +(define_expand "atomic_store" + [(set (match_operand:ANYI 0 "memory_operand" "=A") + (unspec_volatile:ANYI + [(match_operand:ANYI 1 "reg_or_0_operand" "rJ") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_STORE))] + "" + { + rtx mem = operands[0]; + rtx val = operands[1]; + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + if (is_mm_release (model) || is_mm_seq_cst (model)) + emit_insn (gen_mem_fence (GEN_INT (MEMMODEL_RELEASE))); + emit_move_insn (mem, val); + + DONE; +}) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Fri May 27 06:07:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:34 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 7/9] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Fri, 27 May 2022 08:07:21 +0200 Message-Id: <20220527060723.235095-8-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" In order to emit LR/SC sequences, let's provide INSNs, which take care of memory ordering constraints. gcc/ PR 100266 * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New. * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New. * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 9eb0dde9086..3494683947e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,8 @@ (define_c_enum "unspec" [ UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER + UNSPEC_LOAD_RESERVED + UNSPEC_STORE_CONDITIONAL ]) (define_code_iterator any_atomic [plus ior xor and]) @@ -113,6 +115,28 @@ (define_expand "atomic_store" DONE; }) +(define_insn "@riscv_load_reserved" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED))] + "TARGET_ATOMIC" + "lr.%A2 %0, %1" +) + +(define_insn "@riscv_store_conditional" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) + (set (match_operand:GPR 1 "memory_operand" "=A") + (unspec_volatile:GPR + [(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC" + "sc.%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Fri May 27 06:07:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636149 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:35 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 8/9] RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] Date: Fri, 27 May 2022 08:07:22 +0200 Message-Id: <20220527060723.235095-9-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The current model of the LR and SC INSNs requires a sign-extension to use the generated SImode value for conditional branches, which only operate on XLEN registers. However, the sign-extension is actually not required in both cases, therefore this patch introduces additional INSNs that consume the sign-extension. Rationale: The sign-extension of the loaded value of a LR.W is specified as sign-extended. Therefore, a sign-extension is not required. The sign-extension of the success value a SC.W is specified as non-zero. As sign-extended non-zero value remains non-zero, therefore the sign-extension is not required. gcc/ PR 100266 * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3494683947e..66548bf891b 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -125,6 +125,21 @@ (define_insn "@riscv_load_reserved" "lr.%A2 %0, %1" ) +;; This pattern allows to consume a sign-extension of the loaded value. +;; This is legal, because the specification of LR.W defines the loaded +;; value to be sign-extended. + +(define_insn "riscv_load_reserved" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (unspec_volatile:SI + [(match_operand:SI 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED)))] + "TARGET_ATOMIC && TARGET_64BIT" + "lr.w%A2 %0, %1" +) + (define_insn "@riscv_store_conditional" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) @@ -137,6 +152,25 @@ (define_insn "@riscv_store_conditional" "sc.%A3 %0, %z2, %1" ) +;; This pattern allows to consume a sign-extension of the success +;; value of SC.W, which can then be used for instructions which +;; require values of XLEN-size (e.g. conditional branches). +;; This is legal, because any non-zero value remains non-zero +;; after sign-extension. + +(define_insn "riscv_store_conditional" + [(set (match_operand:DI 0 "register_operand" "=&r") + (sign_extend:DI + (unspec_volatile:SI [(const_int 0)] UNSPEC_STORE_CONDITIONAL))) + (set (match_operand:SI 1 "memory_operand" "=A") + (unspec_volatile:SI + [(match_operand:SI 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC && TARGET_64BIT" + "sc.w%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR From patchwork Fri May 27 06:07:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 1636150 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:36 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 9/9] RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266] Date: Fri, 27 May 2022 08:07:23 +0200 Message-Id: <20220527060723.235095-10-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christoph Muellner via Gcc-patches From: =?utf-8?q?Christoph_M=C3=BCllner?= Reply-To: Christoph Muellner Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Atomic instructions require zero-offset memory addresses. If we allow all addresses, the nonzero-offset addresses will be prepared in an extra register in an extra instruction before the actual atomic instruction. This patch introduces the predicate "riscv_sync_memory_operand", which restricts the memory operand to be suitable for atomic instructions. gcc/ PR 100266 * config/riscv/sync.md (riscv_sync_memory_operand): New. * config/riscv/sync.md (riscv_load_reserved): Use new predicate. * config/riscv/sync.md (riscv_store_conditional): Likewise. * config/riscv/sync.md (atomic_): Likewise. * config/riscv/sync.md (atomic_fetch_): Likewise. * config/riscv/sync.md (atomic_exchange): Likewise. * config/riscv/sync.md (atomic_compare_and_swap): Likewise. --- gcc/config/riscv/sync.md | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 66548bf891b..8f184d8bbb4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -30,6 +30,10 @@ (define_c_enum "unspec" [ UNSPEC_STORE_CONDITIONAL ]) +(define_predicate "riscv_sync_memory_operand" + (and (match_operand 0 "memory_operand") + (match_code "reg" "0"))) + (define_code_iterator any_atomic [plus ior xor and]) (define_code_attr atomic_optab [(plus "add") (ior "or") (xor "xor") (and "and")]) @@ -118,7 +122,7 @@ (define_expand "atomic_store" (define_insn "@riscv_load_reserved" [(set (match_operand:GPR 0 "register_operand" "=r") (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "A") + [(match_operand:GPR 1 "riscv_sync_memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_LOAD_RESERVED))] "TARGET_ATOMIC" @@ -133,7 +137,7 @@ (define_insn "riscv_load_reserved" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (unspec_volatile:SI - [(match_operand:SI 1 "memory_operand" "A") + [(match_operand:SI 1 "riscv_sync_memory_operand" "A") (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_LOAD_RESERVED)))] "TARGET_ATOMIC && TARGET_64BIT" @@ -143,7 +147,7 @@ (define_insn "riscv_load_reserved" (define_insn "@riscv_store_conditional" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) - (set (match_operand:GPR 1 "memory_operand" "=A") + (set (match_operand:GPR 1 "riscv_sync_memory_operand" "=A") (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") (match_operand:SI 3 "const_int_operand")] ;; model @@ -162,7 +166,7 @@ (define_insn "riscv_store_conditional" [(set (match_operand:DI 0 "register_operand" "=&r") (sign_extend:DI (unspec_volatile:SI [(const_int 0)] UNSPEC_STORE_CONDITIONAL))) - (set (match_operand:SI 1 "memory_operand" "=A") + (set (match_operand:SI 1 "riscv_sync_memory_operand" "=A") (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") (match_operand:SI 3 "const_int_operand")] ;; model @@ -172,7 +176,7 @@ (define_insn "riscv_store_conditional" ) (define_insn "atomic_" - [(set (match_operand:GPR 0 "memory_operand" "+A") + [(set (match_operand:GPR 0 "riscv_sync_memory_operand" "+A") (unspec_volatile:GPR [(any_atomic:GPR (match_dup 0) (match_operand:GPR 1 "reg_or_0_operand" "rJ")) @@ -184,7 +188,7 @@ (define_insn "atomic_" (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") - (match_operand:GPR 1 "memory_operand" "+A")) + (match_operand:GPR 1 "riscv_sync_memory_operand" "+A")) (set (match_dup 1) (unspec_volatile:GPR [(any_atomic:GPR (match_dup 1) @@ -198,7 +202,7 @@ (define_insn "atomic_fetch_" (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") (unspec_volatile:GPR - [(match_operand:GPR 1 "memory_operand" "+A") + [(match_operand:GPR 1 "riscv_sync_memory_operand" "+A") (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_EXCHANGE)) (set (match_dup 1) @@ -222,14 +226,14 @@ (define_insn "atomic_cas_value_strong" [(set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" - [(match_operand:SI 0 "register_operand" "") ;; bool output - (match_operand:GPR 1 "register_operand" "") ;; val output - (match_operand:GPR 2 "memory_operand" "") ;; memory - (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value - (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value - (match_operand:SI 5 "const_int_operand" "") ;; is_weak - (match_operand:SI 6 "const_int_operand" "") ;; mod_s - (match_operand:SI 7 "const_int_operand" "")] ;; mod_f + [(match_operand:SI 0 "register_operand" "") ;; bool output + (match_operand:GPR 1 "register_operand" "") ;; val output + (match_operand:GPR 2 "riscv_sync_memory_operand" "") ;; memory + (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value + (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value + (match_operand:SI 5 "const_int_operand" "") ;; is_weak + (match_operand:SI 6 "const_int_operand" "") ;; mod_s + (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "TARGET_ATOMIC" { emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2],