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Wed, 25 May 2022 15:04:22 -0700 From: David Thompson To: Subject: [SRU][F:linux-bluefield][PATCH v1 1/1] mlxbf_gige: remove driver-managed interrupt counts Date: Wed, 25 May 2022 18:04:22 -0400 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 186de5a7-bd78-489b-f3b0-08da3e9a888e X-MS-TrafficTypeDiagnostic: DM6PR12MB4699:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HDiDEQNnt1Ta0mvUSKB6lKnBFkxpWIOJ2BFKHDbGngunVnDA/uEoe0i++mlEs2t8kbJ0ej4qInHirI2VuEp1KgTsHF5shTvhI3pb/pMjdTEtFYoVY29j6n4EaHlf0FijMbETPyxw3e2erOG+t4o2L9PnKrRWXGCfK6PMifZnun+mlYYMIUySa+wxMhT1oB1CnVDs+/9UOTA9P4g+JCHMjd/L827YsMsU9ThAV0zyZi2nml3u0mqjBOVWThuO3Rj0IRJHHuvQgzXVulI8xk0nXz+8zKSe1OnMdCVPlEAl3ri53/IAyRjvdUJW2ORqalHY5aF4XFq0TqgTZntG1h7dmDfiC8Cy0Wr8VZmJ+3TFxMrBzEkQMmkNgnVI7J/4BzuFBnbzx3XIDh0hDCPKdtgz/OxYwW5Y/4yNh0KBnKOCLrR/LmTlf4F+2fFxsMDHQZ+5bhfpKrsR3kOtW+L4AHUM2hkWRzHZpCMMuKCeCMaS+iv9JxURuCbAar3fl6+/twEKZ45NqqDSzdSsvOVpAUi6RCtyWSu82V7KqWicVOBZbvGffsDlY4TuDI34AArwxQa+3M+/RV002Wbw4pdiTjykNRhspklwfz4u3iYcG4LclUFn5+QdYuScj1rZOFPf3m+3hErJttSoT01xXZk/GdQhB2rBOea0Glo0sdLtmhwcmVmsCPT8W/sVGPT2BjNjwel5p1F5GHKeHQU2lsy9w89StoC22UmQuVJqivgBJTg8sGVPILObmVEbP8uakQu3OmXQd5spw1v9s8MICuijnqCNXvby+qPCwaAciwrgjq2cDVcmfPp/+wnSGBgZowkguGYG X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(36860700001)(2616005)(5660300002)(7696005)(966005)(186003)(336012)(26005)(426003)(40460700003)(47076005)(508600001)(2906002)(8936002)(107886003)(70586007)(81166007)(83380400001)(316002)(6916009)(54906003)(356005)(4326008)(86362001)(8676002)(70206006)(82310400005)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 22:04:26.1583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 186de5a7-bd78-489b-f3b0-08da3e9a888e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4699 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: meriton@nvidia.com, khoav@nvidia.com Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1975749 The driver currently has three interrupt counters, which are incremented every time each interrupt handler executes. These driver-managed counters are not necessary as the kernel already has logic that manages interrupt counts and exposes them via /proc/interrupts. This patch removes the driver-managed counters. Signed-off-by: David Thompson Signed-off-by: Asmaa Mnebhi Link: https://lore.kernel.org/r/20220511135251.2989-1-davthompson@nvidia.com Signed-off-by: Jakub Kicinski (cherry picked from commit f4826443f4d69d2c97c184952c085caf0936a7b8) --- drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 3 --- .../ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 8 +++----- .../net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c | 9 --------- 3 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h index 86826a70f9dd..5fdf9b7179f5 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h @@ -90,9 +90,6 @@ struct mlxbf_gige { dma_addr_t rx_cqe_base_dma; u16 tx_pi; u16 prev_tx_ci; - u64 error_intr_count; - u64 rx_intr_count; - u64 llu_plu_intr_count; struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ]; struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ]; int error_irq; diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c index 24a32ffee4e4..257724323bfe 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c @@ -24,11 +24,9 @@ static void mlxbf_gige_get_regs(struct net_device *netdev, regs->version = MLXBF_GIGE_REGS_VERSION; /* Read entire MMIO register space and store results - * into the provided buffer. Each 64-bit word is converted - * to big-endian to make the output more readable. - * - * NOTE: by design, a read to an offset without an existing - * register will be acknowledged and return zero. + * into the provided buffer. By design, a read to an + * offset without an existing register will be + * acknowledged and return zero. */ memcpy_fromio(p, priv->base, MLXBF_GIGE_MMIO_REG_SZ); } diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c index c38795be04a2..5b3519f0cc46 100644 --- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c +++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c @@ -17,8 +17,6 @@ static irqreturn_t mlxbf_gige_error_intr(int irq, void *dev_id) priv = dev_id; - priv->error_intr_count++; - int_status = readq(priv->base + MLXBF_GIGE_INT_STATUS); if (int_status & MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR) @@ -75,8 +73,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id) priv = dev_id; - priv->rx_intr_count++; - /* NOTE: GigE silicon automatically disables "packet rx" interrupt by * setting MLXBF_GIGE_INT_MASK bit0 upon triggering the interrupt * to the ARM cores. Software needs to re-enable "packet rx" @@ -90,11 +86,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id) static irqreturn_t mlxbf_gige_llu_plu_intr(int irq, void *dev_id) { - struct mlxbf_gige *priv; - - priv = dev_id; - priv->llu_plu_intr_count++; - return IRQ_HANDLED; }