From patchwork Thu Sep 14 01:16:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 813674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xt0wq5cZYz9ryv for ; Thu, 14 Sep 2017 11:16:27 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xt0wq4hGGzDr8P for ; Thu, 14 Sep 2017 11:16:27 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xt0wV5KFYzDqkv for ; Thu, 14 Sep 2017 11:16:10 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8E1E1do085799 for ; Wed, 13 Sep 2017 21:16:07 -0400 Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) by mx0b-001b2d01.pphosted.com with ESMTP id 2cyf5ushkj-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 13 Sep 2017 21:16:07 -0400 Received: from localhost by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 13 Sep 2017 19:16:05 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8E1G5K43670476; Wed, 13 Sep 2017 18:16:05 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2656978056; Wed, 13 Sep 2017 19:16:05 -0600 (MDT) Received: from arbab-laptop.localdomain (unknown [9.53.92.213]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 10CDD78038; Wed, 13 Sep 2017 19:16:05 -0600 (MDT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 9016546059D; Wed, 13 Sep 2017 20:16:03 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 13 Sep 2017 20:16:03 -0500 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 17091401-0008-0000-0000-000008915CD0 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007725; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000227; SDB=6.00916669; UDB=6.00460339; IPR=6.00696899; BA=6.00005588; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017143; XFM=3.00000015; UTC=2017-09-14 01:16:06 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17091401-0009-0000-0000-000043F6A84E Message-Id: <1505351763-12233-1-git-send-email-arbab@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-13_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709140015 Subject: [Skiboot] [PATCH v2] npu2: hw-procedures: Enable low power mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple , Andrew Donnellan MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a procedure which sets the NTL low power config register. Signed-off-by: Reza Arbab Reviewed-by: Andrew Donnellan --- v2: * New documentation has updated the value we should set. v1: * http://patchwork.ozlabs.org/patch/810822/ --- hw/npu2-hw-procedures.c | 18 +++++++++++++++++- include/npu2-regs.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 7617962..bb0769b 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -310,9 +310,25 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0); } + return PROCEDURE_NEXT; +} + +/* Procedure 1.2.11 - Enable Low Power Mode */ +static uint32_t enable_low_power(struct npu2_dev *ndev) +{ + uint64_t val; + + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 5); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 68); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 68); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 1280); + npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val); + return PROCEDURE_COMPLETE; } -DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete); +DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete, + enable_low_power); /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */ static uint32_t phy_tx_zcal(struct npu2_dev *ndev) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 759404c..307e93b 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_MISC_CFG1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0C0) #define NPU2_NTL_SCRATCH1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0D0) #define NPU2_NTL_LOW_POWER_CFG(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0E0) +#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE PPC_BIT(0) +#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE PPC_BIT(1) +#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG PPC_BITMASK(2,7) +#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH PPC_BITMASK(8,19) +#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH PPC_BITMASK(20,31) +#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH PPC_BITMASK(32,43) #define NPU2_NTL_DBG_INHIBIT_CFG(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x220) #define NPU2_NTL_DISPLAY_CTL(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x280) #define NPU2_NTL_DISPLAY_DATA0(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x288)