From patchwork Fri May 13 10:28:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1630619 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=CVY8UpC9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L04cV4b5Nz9sFx for ; Fri, 13 May 2022 20:28:41 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B092A3876079 for ; Fri, 13 May 2022 10:28:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B092A3876079 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1652437718; bh=yUlf8yvRrSNNNcyTtnGnbxx2OxX1+Ph0ksDL+J57AZU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=CVY8UpC9P9p8MTQwGXA9Cc+JQIsUDsiOVpST8/57Cy636iKyT5UiGtAj/e2SrAkho 8xmcZ9ZC/m92J2o2UnqBgfApdjxIedEPpcOd/pEkKOXwHuYweiltqkNnJGaxA85ULK R0S69HoJxy+D57XSCRyNfEmFv6Iw7pXok6Ajbs90= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 5461738485AF for ; Fri, 13 May 2022 10:28:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5461738485AF Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D69F143D; Fri, 13 May 2022 03:28:19 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.2.52]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CCCD3F5A1; Fri, 13 May 2022 03:28:18 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [committed 1/2] arm: fix some issues in mve_vector_mem_operand Date: Fri, 13 May 2022 11:28:07 +0100 Message-Id: <20220513102808.3092726-1-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" There are a couple of issues with the mve_vector_mem_operand function. Firstly, SP is permitted as a register provided there is no write-back operation. Secondly, there were some cases where 'strict' was not being applied when checking which registers had been used. gcc/ChangeLog: * config/arm/arm.cc (mve_vector_mem_operand): Allow SP_REGNUM when there is no write-back. Fix use when strict is true. --- gcc/config/arm/arm.cc | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 69a18c2f157..2afe0445ed5 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -13527,7 +13527,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) int reg_no = REGNO (op); return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) ? reg_no <= LAST_LO_REGNUM - :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)) + : reg_no < LAST_ARM_REGNUM) || (!strict && reg_no >= FIRST_PSEUDO_REGISTER)); } code = GET_CODE (op); @@ -13536,10 +13536,10 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) || code == PRE_INC || code == POST_DEC) { reg_no = REGNO (XEXP (op, 0)); - return ((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) - ? reg_no <= LAST_LO_REGNUM - :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)) - || reg_no >= FIRST_PSEUDO_REGISTER; + return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode) + ? reg_no <= LAST_LO_REGNUM + :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)) + || (!strict && reg_no >= FIRST_PSEUDO_REGISTER)); } else if (((code == POST_MODIFY || code == PRE_MODIFY) && GET_CODE (XEXP (op, 1)) == PLUS @@ -13580,10 +13580,11 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) default: return FALSE; } - return reg_no >= FIRST_PSEUDO_REGISTER - || (MVE_STN_LDW_MODE (mode) - ? reg_no <= LAST_LO_REGNUM - : (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)); + return ((!strict && reg_no >= FIRST_PSEUDO_REGISTER) + || (MVE_STN_LDW_MODE (mode) + ? reg_no <= LAST_LO_REGNUM + : (reg_no < LAST_ARM_REGNUM + && (code == PLUS || reg_no != SP_REGNUM)))); } return FALSE; } From patchwork Fri May 13 10:28:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1630620 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=t2IewL6c; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L04dY4pS4z9sFx for ; Fri, 13 May 2022 20:29:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8251D383800D for ; Fri, 13 May 2022 10:29:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8251D383800D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1652437775; bh=/bMz+8UEvFtxzTc2Mcu1sOOOMITT/Iqo9GfsjVIJ5gA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=t2IewL6cJFD1geVNuYo/QNnjMtg4IwmIljwwQaj5eVzZGikKSLe64T9wn+qYv5KFz GFT9xvaSfA20iurWieeWN8/fNOBRC1bwxImlj4hv8LT38kuleGAOuWtGul8dh7eLJd SuDP4h/y3n9JATMH7+sh3p5IfR74zIAU7E6N/fMM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 0B661383D82A for ; Fri, 13 May 2022 10:28:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0B661383D82A Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF49F1477; Fri, 13 May 2022 03:28:19 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.2.52]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39D7C3F5A1; Fri, 13 May 2022 03:28:19 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [committed 2/2] arm: correctly handle misaligned MEMs on MVE [PR105463] Date: Fri, 13 May 2022 11:28:08 +0100 Message-Id: <20220513102808.3092726-2-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513102808.3092726-1-rearnsha@arm.com> References: <20220513102808.3092726-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Vector operations in MVE must be aligned to the element size, so if we are asked for a misaligned move in a wider mode we must recast it to a form suitable for the known alignment (larger elements have better address offset ranges, so there is some advantage to using wider element sizes if possible). Whilst fixing this, also rework the predicates used for validating operands - the Neon predicates are not right for MVE. gcc/ChangeLog: PR target/105463 * config/arm/mve.md (*movmisalign_mve_store): Use mve_memory_operand. (*movmisalign_mve_load): Likewise. * config/arm/vec-common.md (movmisalign): Convert to generator form... (@movmisalign): ... thus. Use generic predicates and then rework operands if they are not valid. For MVE rework to a narrower element size if the alignment is not high enough. --- gcc/config/arm/mve.md | 4 +- gcc/config/arm/vec-common.md | 90 ++++++++++++++++++++++++++++-------- 2 files changed, 73 insertions(+), 21 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 369d7a79f6c..f16991c0a34 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -10462,7 +10462,7 @@ (define_insn "arm_vcx3q_p_v16qi" ) (define_insn "*movmisalign_mve_store" - [(set (match_operand:MVE_VLD_ST 0 "neon_permissive_struct_operand" "=Ux") + [(set (match_operand:MVE_VLD_ST 0 "mve_memory_operand" "=Ux") (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")] UNSPEC_MISALIGNED_ACCESS))] "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) @@ -10475,7 +10475,7 @@ (define_insn "*movmisalign_mve_store" (define_insn "*movmisalign_mve_load" [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") - (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "neon_permissive_struct_operand" " Ux")] + (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "mve_memory_operand" " Ux")] UNSPEC_MISALIGNED_ACCESS))] "((TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))) diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index fd878cba22d..1fd68f3ac43 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -280,29 +280,81 @@ (define_expand "cml4" DONE; }) -(define_expand "movmisalign" - [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand") - (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")] +(define_expand "@movmisalign" + [(set (match_operand:VDQ 0 "nonimmediate_operand") + (unspec:VDQ [(match_operand:VDQ 1 "general_operand")] UNSPEC_MISALIGNED_ACCESS))] "ARM_HAVE__LDST && !BYTES_BIG_ENDIAN && unaligned_access && !TARGET_REALLY_IWMMXT" { - rtx adjust_mem; - /* This pattern is not permitted to fail during expansion: if both arguments - are non-registers (e.g. memory := constant, which can be created by the - auto-vectorizer), force operand 1 into a register. */ - if (!s_register_operand (operands[0], mode) - && !s_register_operand (operands[1], mode)) - operands[1] = force_reg (mode, operands[1]); - - if (s_register_operand (operands[0], mode)) - adjust_mem = operands[1]; - else - adjust_mem = operands[0]; - - /* Legitimize address. */ - if (!neon_vector_mem_operand (adjust_mem, 2, true)) - XEXP (adjust_mem, 0) = force_reg (Pmode, XEXP (adjust_mem, 0)); + rtx *memloc; + bool for_store = false; + /* This pattern is not permitted to fail during expansion: if both arguments + are non-registers (e.g. memory := constant, which can be created by the + auto-vectorizer), force operand 1 into a register. */ + if (!s_register_operand (operands[0], mode) + && !s_register_operand (operands[1], mode)) + operands[1] = force_reg (mode, operands[1]); + + if (s_register_operand (operands[0], mode)) + memloc = &operands[1]; + else + { + memloc = &operands[0]; + for_store = true; + } + + /* For MVE, vector loads/stores must be aligned to the element size. If the + alignment is less than that convert the load/store to a suitable mode. */ + if (TARGET_HAVE_MVE + && (MEM_ALIGN (*memloc) + < GET_MODE_ALIGNMENT (GET_MODE_INNER (mode)))) + { + scalar_mode new_smode; + switch (MEM_ALIGN (*memloc)) + { + case 64: + case 32: + new_smode = SImode; + break; + case 16: + new_smode = HImode; + break; + default: + new_smode = QImode; + break; + } + machine_mode new_mode + = mode_for_vector (new_smode, + GET_MODE_SIZE (mode) + / GET_MODE_SIZE (new_smode)).require (); + rtx new_mem = adjust_address (*memloc, new_mode, 0); + + if (!for_store) + { + rtx reg = gen_reg_rtx (new_mode); + emit_insn (gen_movmisalign (new_mode, reg, new_mem)); + emit_move_insn (operands[0], gen_lowpart (mode, reg)); + DONE; + } + emit_insn (gen_movmisalign (new_mode, new_mem, + gen_lowpart (new_mode, operands[1]))); + DONE; + } + + /* Legitimize address. */ + if ((TARGET_HAVE_MVE + && !mve_vector_mem_operand (mode, XEXP (*memloc, 0), false)) + || (!TARGET_HAVE_MVE + && !neon_vector_mem_operand (*memloc, 2, false))) + { + rtx new_mem + = replace_equiv_address (*memloc, + force_reg (Pmode, XEXP (*memloc, 0)), + false); + gcc_assert (MEM_ALIGN (new_mem) == MEM_ALIGN (*memloc)); + *memloc = new_mem; + } }) (define_insn "mve_vshlq_"