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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2022 20:17:31.6961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 535350f6-8e06-4ecc-3206-08da338b4775 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6418 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device-tree binding documentation to represent the Control Backbone (CBB) version 1.0 used in Tegra194 SOC. Signed-off-by: Sumit Gupta Reviewed-by: Rob Herring --- .../arm/tegra/nvidia,tegra194-cbb.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml new file mode 100644 index 000000000000..f967b45e83d5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 CBB 1.0 bindings + +maintainers: + - Sumit Gupta + +description: |+ + The Control Backbone (CBB) is comprised of the physical path from an + initiator to a target's register configuration space. CBB 1.0 has + multiple hierarchical sub-NOCs (Network-on-Chip) and connects various + initiators and targets using different bridges like AXIP2P, AXI2APB. + + This driver handles errors due to illegal register accesses reported + by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs + "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" + which is the main NOC. + + By default, the access issuing initiator is informed about the error + using SError or Data Abort exception unless the ERD (Error Response + Disable) is enabled/set for that initiator. If the ERD is enabled, then + SError or Data Abort is masked and the error is reported with interrupt. + + - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the + errors due to illegal accesses from CCPLEX are reported by interrupts. + If ERD is not set, then error is reported by SError. + - For other initiators, the ERD is disabled. So, the access issuing + initiator is informed about the illegal access by Data Abort exception. + In addition, an interrupt is also generated to CCPLEX. These initiators + include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and + engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder + engine) etc which can initiate transactions. + + The driver prints relevant debug information like Error Code, Error + Description, Master, Address, AXI ID, Cache, Protection, Security Group + etc on receiving error notification. + +properties: + $nodename: + pattern: "^[a-z]+-noc@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra194-cbb-noc + - nvidia,tegra194-aon-noc + - nvidia,tegra194-bpmp-noc + - nvidia,tegra194-rce-noc + - nvidia,tegra194-sce-noc + + reg: + maxItems: 1 + + interrupts: + description: + CCPLEX receives secure or nonsecure interrupt depending on error type. + A secure interrupt is received for SEC(firewall) & SLV errors and a + non-secure interrupt is received for TMO & DEC errors. + items: + - description: non-secure interrupt + - description: secure interrupt + + nvidia,axi2apb: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the node having all axi2apb bridges which need to be checked + for any error logged in their status register. + + nvidia,apbmisc: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + Specifies the apbmisc node which need to be used for reading the ERD + register. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - nvidia,axi2apb + - nvidia,apbmisc + +examples: + - | + #include + + cbb-noc@2300000 { + compatible = "nvidia,tegra194-cbb-noc"; + reg = <0x02300000 0x1000>; + interrupts = , + ; + nvidia,axi2apb = <&axi2apb>; + nvidia,apbmisc = <&apbmisc>; + }; From patchwork Wed May 11 20:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 1629737 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=L+2J1tMi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Kz5nC52mDz9sGY for ; Thu, 12 May 2022 06:17:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347675AbiEKURt (ORCPT ); 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Wed, 11 May 2022 20:17:40 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 11 May 2022 13:17:39 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Wed, 11 May 2022 13:17:36 -0700 From: Sumit Gupta To: , , , , , , CC: , , , , Thierry Reding Subject: [Patch v6 3/9] dt-bindings: arm: tegra: Add NVIDIA Tegra194 axi2apb binding Date: Thu, 12 May 2022 01:46:45 +0530 Message-ID: <20220511201651.30695-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220511201651.30695-1-sumitg@nvidia.com> References: <20220511201651.30695-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d195d46a-ed08-4b7b-e020-08da338b4cd8 X-MS-TrafficTypeDiagnostic: MN2PR12MB4566:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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All errors for APB slaves are reported as slave error because APB bas single bit to report error. So, CBB driver needs to further check error status registers of all the axi2apb bridges to find error type. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../arm/tegra/nvidia,tegra194-axi2apb.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml new file mode 100644 index 000000000000..788a13f8aa93 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra194 AXI2APB bridge + +maintainers: + - Sumit Gupta + +properties: + $nodename: + pattern: "^axi2apb@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra194-axi2apb + + reg: + maxItems: 6 + description: Physical base address and length of registers for all bridges + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + axi2apb: axi2apb@2390000 { + compatible = "nvidia,tegra194-axi2apb"; + reg = <0x02390000 0x1000>, + <0x023a0000 0x1000>, + <0x023b0000 0x1000>, + <0x023c0000 0x1000>, + <0x023d0000 0x1000>, + <0x023e0000 0x1000>; + }; From patchwork Wed May 11 20:16:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 1629742 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=MVkVcs+C; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Kz5pM6Dm6z9sG2 for ; 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Wed, 11 May 2022 13:18:26 -0700 From: Sumit Gupta To: , , , , , , CC: , , , Subject: [Patch v6 6/9] dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB2.0 binding Date: Thu, 12 May 2022 01:46:48 +0530 Message-ID: <20220511201651.30695-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220511201651.30695-1-sumitg@nvidia.com> References: <20220511201651.30695-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a95bbbd4-bb6e-43eb-c162-08da338b6a73 X-MS-TrafficTypeDiagnostic: BYAPR12MB5703:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OYUJNHayVcBFTfhdHbzTpMfnIoAuMKAcKcCvDvi07HUJMuvAy8vVsaogXMGKA/OVOYRQuRDr6kyq6Mj8VzPiJ6IrtpMd47e5uIC3CzwLds0G5QDIQ0YFJ+Y2w7A3/FVxdFLLFVyzns63FzbDf2aId73Ls7NhYXu9t3PEhKCF27b4sRbuiyHFELyDOF3AjfL0j0Zanv/rAUa8QFShROJJOBYSnXNLpaaQ/9ocvO3oOp7zSKsnKojHmF9PLnCdGUTQWXT96m1qQ79xhqQ47OI+r6omvjsQBBTVW4QPFiq6Fl1ccDLmGuCfSM9ddWEv1YtAOXCXrhpmcHS7kMoa0WzJcm+wQNNBdGRz3OfDCVNyUvjM9TSuPLij+YEyl1iPNp7pJBkz/z9w85J+yJmP1BleZwtPYKFesr/SA4Di1kY/2LrSa5P3rrUGRJv6MOxoxE8jnu0pAseqIhWePPSucrjiHNqiee9RLFEWpZedjajnn7MNPSSpU0PYR3qaLsytsByfsunDROnX7pOkB+mlgWyfdTkoA4ipUs9xJ3839+fsPbybc2F1+jdmd7mjZ9SEpe91Op1NC5tHl56kpnWQ8pF2nI7rMFEJCTm0OfAse1ufJD6x117zyELn8c33Ekf3+2MDIiHOU8VktvUe27+fa1G/x/1gkFpgOimtVov7tbh4ZmxUxlksWYgpwn/rMtPmqGg8xORaYWgns43153weG4rH/xtcA8HdYLnIlwksFXitXNg4DYhz9dr/L65hKIPfn9ZWx/t5M5PWfABtWS8uqJBDNpwuUIi0QGcTtTjrvIjomtX67hYODelZB3vBE0dP+l6K64sTwMpWKkMLK882rk/nMg== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(36860700001)(82310400005)(26005)(36756003)(2906002)(6666004)(8676002)(47076005)(8936002)(508600001)(70206006)(356005)(81166007)(426003)(86362001)(186003)(40460700003)(1076003)(4326008)(336012)(110136005)(54906003)(7696005)(83380400001)(107886003)(5660300002)(2616005)(316002)(70586007)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Sumit Gupta Reviewed-by: Rob Herring --- .../arm/tegra/nvidia,tegra234-cbb.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml new file mode 100644 index 000000000000..7b1fe50ffbe0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CBB 2.0 bindings + +maintainers: + - Sumit Gupta + +description: |+ + The Control Backbone (CBB) is comprised of the physical path from an + initiator to a target's register configuration space. CBB 2.0 consists + of multiple sub-blocks connected to each other to create a topology. + The Tegra234 SoC has different fabrics based on CBB 2.0 architecture + which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and + "CBB central fabric". + + In CBB 2.0, each initiator which can issue transactions connects to a + Root Master Node (MN) before it connects to any other element of the + fabric. Each Root MN contains a Error Monitor (EM) which detects and + logs error. Interrupts from various EM blocks are collated by Error + Notifier (EN) which is per fabric and presents a single interrupt from + fabric to the SoC interrupt controller. + + The driver handles errors from CBB due to illegal register accesses + and prints debug information about failed transaction on receiving + the interrupt from EN. Debug information includes Error Code, Error + Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, + Security Group etc on receiving error notification. + + If the Error Response Disable (ERD) is set/enabled for an initiator, + then SError or Data abort exception error response is masked and an + interrupt is used for reporting errors due to illegal accesses from + that initiator. The value returned on read failures is '0xFFFFFFFF' + for compatibility with PCIE. + +properties: + $nodename: + pattern: "^[a-z]+-fabric@[0-9a-f]+$" + + compatible: + enum: + - nvidia,tegra234-aon-fabric + - nvidia,tegra234-bpmp-fabric + - nvidia,tegra234-cbb-fabric + - nvidia,tegra234-dce-fabric + - nvidia,tegra234-rce-fabric + - nvidia,tegra234-sce-fabric + + reg: + maxItems: 1 + + interrupts: + items: + - description: secure interrupt from error notifier + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + + cbb-fabric@1300000 { + compatible = "nvidia,tegra234-cbb-fabric"; + reg = <0x13a00000 0x400000>; + interrupts = ; + };