From patchwork Mon May 9 21:14:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 1628816 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcdkim header.b=vBlbbVUV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kxv7m100lz9sCq for ; Tue, 10 May 2022 07:14:44 +1000 (AEST) Received: from localhost ([::1]:57428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noAiH-0005qd-VV for incoming@patchwork.ozlabs.org; Mon, 09 May 2022 17:14:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noAhq-0005pv-Pc for qemu-devel@nongnu.org; Mon, 09 May 2022 17:14:14 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:41704) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1noAho-0007Qi-8k for qemu-devel@nongnu.org; Mon, 09 May 2022 17:14:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652130852; x=1683666852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wnJyMXznj/NY6S7udslUPpj6o4RnH2MZKcgpGtQSUlg=; b=vBlbbVUV3PtQm3dLl4xe85Z4o42BhTKWNoSyaJahucFPFayNM67jHkS4 FaCXxFNP3sg/YFI4dhixFnFUFw0May/wvKWhtpgGaggf+e8AuW4mtBjDT av3N7bPGMRyg7hW2JgYXYlMbuNgeWBPVG9XMd5P83KPZmbTIDsBH9mNAG o=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 09 May 2022 14:14:09 -0700 X-QCInternal: smtphost Received: from hu-tsimpson-lv.qualcomm.com (HELO hu-devc-lv-u18-c.qualcomm.com) ([10.47.235.220]) by ironmsg09-lv.qualcomm.com with ESMTP; 09 May 2022 14:14:09 -0700 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 0A6DF5005B7; Mon, 9 May 2022 14:14:09 -0700 (PDT) From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, ale@rev.ng, bcain@quicinc.com, mlambert@quicinc.com Subject: [PATCH] Hexagon (target/hexagon) make VyV operands use a unique temp Date: Mon, 9 May 2022 14:14:01 -0700 Message-Id: <20220509211405.18581-2-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509211405.18581-1-tsimpson@quicinc.com> References: <20220509211405.18581-1-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=129.46.98.28; envelope-from=tsimpson@qualcomm.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/hvx_misc.c | 45 +++++++++++++++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 9 +++---- 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index b896f5897e..6e2c9ab3cd 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -498,6 +498,49 @@ static void test_vsubuwsat_dv(void) check_output_w(__LINE__, 2); } +static void test_vshuff(void) +{ + /* Test that vshuff works when the two operands are the same register */ + const uint32_t splat = 0x089be55c; + const uint32_t shuff = 0x454fa926; + MMVector v0, v1; + + memset(expect, 0x12, sizeof(MMVector)); + memset(output, 0x34, sizeof(MMVector)); + + asm volatile("v25 = vsplat(%0)\n\t" + "vshuff(v25, v25, %1)\n\t" + "vmem(%2 + #0) = v25\n\t" + : /* no outputs */ + : "r"(splat), "r"(shuff), "r"(output) + : "v25", "memory"); + + /* + * The semantics of Hexagon are the operands are pass-by-value, so create + * two copies of the vsplat result. + */ + for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + v0.uw[i] = splat; + v1.uw[i] = splat; + } + /* Do the vshuff operation */ + for (int offset = 1; offset < MAX_VEC_SIZE_BYTES; offset <<= 1) { + if (shuff & offset) { + for (int k = 0; k < MAX_VEC_SIZE_BYTES; k++) { + if (!(k & offset)) { + uint8_t tmp = v0.ub[k]; + v0.ub[k] = v1.ub[k + offset]; + v1.ub[k + offset] = tmp; + } + } + } + } + /* Put the result in the expect buffer for verification */ + expect[0] = v1; + + check_output_b(__LINE__, 1); +} + int main() { init_buffers(); @@ -533,6 +576,8 @@ int main() test_vadduwsat(); test_vsubuwsat_dv(); + test_vshuff(); + puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; } diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index 1fd9de95d5..d72c689ad7 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ## -## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. +## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -164,7 +164,9 @@ def genptr_decl(f, tag, regtype, regid, regno): (regtype, regid, regno)) f.write(" const intptr_t %s%sV_off =\n" % \ (regtype, regid)) - if (hex_common.is_tmp_result(tag)): + if (regid == "y"): + f.write(" offsetof(CPUHexagonState, vtmp);\n") + elif (hex_common.is_tmp_result(tag)): f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n" % \ (regtype, regid)) else: @@ -379,9 +381,6 @@ def genptr_src_read(f, tag, regtype, regid): f.write(" vreg_src_off(ctx, %s%sN),\n" % \ (regtype, regid)) f.write(" sizeof(MMVector), sizeof(MMVector));\n") - if (not hex_common.skip_qemu_helper(tag)): - f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\n" % \ - (regtype, regid, regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype == "Q"):