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Sat, 30 Apr 2022 09:14:38 -0700 (PDT) From: Adam Ford To: u-boot@lists.denx.de Cc: Adam Ford , "Ying-Chun Liu (PaulLiu)" , Jagan Teki , Matteo Lisi , Marek Vasut , Olaf Mandel , Peng Fan , Tim Harvey , "Ariel D'Alessandro" , Michael Trimarchi , Ilko Iliev , Fabio Estevam , Marco Franchi , Alifer Moraes , Lukasz Majewski , Sean Anderson Subject: [RFC 1/3] clk: imx8mm: Add UART clocks Date: Sat, 30 Apr 2022 11:14:20 -0500 Message-Id: <20220430161422.558361-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430161422.558361-1-aford173@gmail.com> References: <20220430161422.558361-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean There are four UART's with various clocks assoicated with each. Add them to the clock driver so they can be enabled and queried by the serial driver as needed. Signed-off-by: Adam Ford diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 542aa31f7a..8566c3e4a0 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -78,6 +78,18 @@ static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_ static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; +static const char *imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", + "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", + "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", + "sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m", + "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; + static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -267,6 +279,14 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00)); clk_dm(IMX8MM_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80)); + clk_dm(IMX8MM_CLK_UART1, + imx8m_clk_composite("uart1", imx8mm_uart1_sels, base + 0xaf00)); + clk_dm(IMX8MM_CLK_UART2, + imx8m_clk_composite("uart2", imx8mm_uart2_sels, base + 0xaf80)); + clk_dm(IMX8MM_CLK_UART3, + imx8m_clk_composite("uart3", imx8mm_uart3_sels, base + 0xb000)); + clk_dm(IMX8MM_CLK_UART4, + imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080)); clk_dm(IMX8MM_CLK_PWM1, imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380)); clk_dm(IMX8MM_CLK_PWM2, @@ -307,6 +327,16 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MM_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); + + clk_dm(IMX8MM_CLK_UART1_ROOT, + imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0)); + clk_dm(IMX8MM_CLK_UART2_ROOT, + imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); + clk_dm(IMX8MM_CLK_UART3_ROOT, + imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); + clk_dm(IMX8MM_CLK_UART4_ROOT, + imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MM_CLK_OCOTP_ROOT, imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MM_CLK_PWM1_ROOT, From patchwork Sat Apr 30 16:14:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 1624744 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Sat, 30 Apr 2022 09:14:41 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:3a27:d646:29a7:7498]) by smtp.gmail.com with ESMTPSA id u2-20020a02b1c2000000b0032b3a781771sm1532860jah.53.2022.04.30.09.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 09:14:40 -0700 (PDT) From: Adam Ford To: u-boot@lists.denx.de Cc: Adam Ford , "Ying-Chun Liu (PaulLiu)" , Jagan Teki , Matteo Lisi , Marek Vasut , Olaf Mandel , Peng Fan , Tim Harvey , "Ariel D'Alessandro" , Michael Trimarchi , Ilko Iliev , Fabio Estevam , Marco Franchi , Alifer Moraes , Simon Glass Subject: [RFC 2/3] serial: mxc: Enable getting and enabling clocks with CCF Composite Date: Sat, 30 Apr 2022 11:14:21 -0500 Message-Id: <20220430161422.558361-3-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430161422.558361-1-aford173@gmail.com> References: <20220430161422.558361-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Certain platforms have the UART clocks exposed through the CCF. When they are, it's possible to enable and query the clock(s) for a given UART. Add support getting, enabling, and querying the clocks. Signed-off-by: Adam Ford diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e4970a169b..c68040ba74 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -266,8 +267,13 @@ __weak struct serial_device *default_serial_console(void) int mxc_serial_setbrg(struct udevice *dev, int baudrate) { struct mxc_serial_plat *plat = dev_get_plat(dev); - u32 clk = imx_get_uartclk(); + u32 clk; +#if CONFIG_IS_ENABLED(CLK_COMPOSITE_CCF) + clk = clk_get_rate(&plat->ipg_clk); +#else + clk = imx_get_uartclk; +#endif _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte); return 0; @@ -277,6 +283,22 @@ static int mxc_serial_probe(struct udevice *dev) { struct mxc_serial_plat *plat = dev_get_plat(dev); +#if CONFIG_IS_ENABLED(CLK_COMPOSITE_CCF) + int ret = 0; + + ret = clk_enable(&plat->per_clk); + if (ret) { + printf("Failed to enable per_clk\n"); + return ret; + } + + ret = clk_enable(&plat->per_clk); + if (ret) { + printf("Failed to enable ipg_clk\n"); + return ret; + } + +#endif _mxc_serial_init(plat->reg, plat->use_dte); return 0; @@ -339,6 +361,21 @@ static int mxc_serial_of_to_plat(struct udevice *dev) plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "fsl,dte-mode"); +#if CONFIG_IS_ENABLED(CLK_COMPOSITE_CCF) + int ret = 0; + + ret = clk_get_by_name(dev, "per", &plat->per_clk); + if (ret) { + printf("Failed to get per_clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "ipg", &plat->ipg_clk); + if (ret) { + printf("Failed to get per_clk\n"); + return ret; + } +#endif return 0; } diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h index cc59eeb1dd..9a8c8498bf 100644 --- a/include/dm/platform_data/serial_mxc.h +++ b/include/dm/platform_data/serial_mxc.h @@ -10,6 +10,8 @@ struct mxc_serial_plat { struct mxc_uart *reg; /* address of registers in physical memory */ bool use_dte; + struct clk per_clk; + struct clk ipg_clk; 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Sat, 30 Apr 2022 09:14:42 -0700 (PDT) From: Adam Ford To: u-boot@lists.denx.de Cc: Adam Ford , "Ying-Chun Liu (PaulLiu)" , Jagan Teki , Matteo Lisi , Marek Vasut , Olaf Mandel , Peng Fan , Tim Harvey , "Ariel D'Alessandro" , Michael Trimarchi , Ilko Iliev , Fabio Estevam , Marco Franchi , Alifer Moraes Subject: [RFC 3/3] imx8: imx8mm_beacon: Remove manual UART clock initialization Date: Sat, 30 Apr 2022 11:14:22 -0500 Message-Id: <20220430161422.558361-4-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430161422.558361-1-aford173@gmail.com> References: <20220430161422.558361-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean SPL has a manual call to init_uart_clk in order to start the clocks. If the CCF has the UART clocks available, the serial driver can enable and query the clock when needed, so the manual call to init_uart_clk can be dropped. Signed-off-by: Adam Ford diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index f92b4c3ed0..fc0935bc97 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -114,8 +114,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - init_uart_clk(1); - board_early_init_f(); timer_init();