From patchwork Wed Apr 20 08:23:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Biener X-Patchwork-Id: 1619400 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=P4X8cS3p; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kjtxp4XFJz9sFx for ; Wed, 20 Apr 2022 18:24:29 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 371073857355 for ; Wed, 20 Apr 2022 08:24:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 371073857355 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1650443065; bh=bMmzTVMvCPBvhZ2g6tI+S5Hw+Z32tvx42/8yigUB0pM=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=P4X8cS3p8DiQaLS3g+iw8pUr9K+5VGg0eVgX8xVpBjEokRsPQL5iQzsG5hocQNgRx XLx6ITxQUWsUi36Dt8hhKVLIsCL8XnxhpSVsIoFrHxtsfZSzV1F9t7qZSE16UPbacm +6j9fKEoIWyFR51DZFhK5NghU49iVJ7RvRBapeS0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by sourceware.org (Postfix) with ESMTPS id 99D6E3858D3C for ; Wed, 20 Apr 2022 08:23:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 99D6E3858D3C Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 8B2D521115; Wed, 20 Apr 2022 08:23:41 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 71F4F13AD5; Wed, 20 Apr 2022 08:23:41 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id caGhGg3DX2IvcwAAMHmgww (envelope-from ); Wed, 20 Apr 2022 08:23:41 +0000 Date: Wed, 20 Apr 2022 10:23:41 +0200 (CEST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] tree-optimization/105312 - fix ISEL VCOND expansion MIME-Version: 1.0 Message-Id: <20220420082341.71F4F13AD5@imap2.suse-dmz.suse.de> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Biener via Gcc-patches From: Richard Biener Reply-To: Richard Biener Cc: richard.earnshaw@arm.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The following aligns ISEL VEC_COND_EXPR expansion using VCOND with the optab query done by vector lowering. Instead of only allowing the signed optab to provide EQ/NE compares we allow both here though since there seems to be no documented canonicalization. Bootstrap and regtest running on x86_64-unknown-linux-gnu, I've cut&pasted neon boilerplate for the testcase but cannot test it (a cc1 cross makes it UNSUPPORTED), if I don't hear otherwise I'm going to push as-is after testing completed. Thanks, Richard. 2022-04-20 Richard Biener PR tree-optimization/105312 * gimple-isel.cc (gimple_expand_vec_cond_expr): Query both VCOND and VCONDU for EQ and NE. * gcc.target/arm/pr105312.c: New testcase. --- gcc/gimple-isel.cc | 8 ++++++++ gcc/testsuite/gcc.target/arm/pr105312.c | 23 +++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/pr105312.c diff --git a/gcc/gimple-isel.cc b/gcc/gimple-isel.cc index 3635585bf45..a8f7a0d25d0 100644 --- a/gcc/gimple-isel.cc +++ b/gcc/gimple-isel.cc @@ -245,6 +245,14 @@ gimple_expand_vec_cond_expr (struct function *fun, gimple_stmt_iterator *gsi, GET_MODE_NUNITS (cmp_op_mode))); icode = get_vcond_icode (mode, cmp_op_mode, unsignedp); + /* Some targets do not have vcondeq and only vcond with NE/EQ + but not vcondu, so make sure to also try vcond here as + vcond_icode_p would canonicalize the optab query to. */ + if (icode == CODE_FOR_nothing + && (tcode == NE_EXPR || tcode == EQ_EXPR) + && ((icode = get_vcond_icode (mode, cmp_op_mode, !unsignedp)) + != CODE_FOR_nothing)) + unsignedp = !unsignedp; if (icode == CODE_FOR_nothing) { if (tcode == LT_EXPR diff --git a/gcc/testsuite/gcc.target/arm/pr105312.c b/gcc/testsuite/gcc.target/arm/pr105312.c new file mode 100644 index 00000000000..a02831bcbcf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr105312.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-mcpu=cortex-a15" } */ +/* { dg-add-options arm_neon } */ + +typedef float stress_matrix_type_t; +typedef unsigned int size_t; +static void __attribute__((optimize("-O3"))) stress_matrix_xy_identity( + const size_t n, + stress_matrix_type_t a[restrict n][n], + stress_matrix_type_t b[restrict n][n], + stress_matrix_type_t r[restrict n][n]) +{ + register size_t i; + (void)a; + (void)b; + for (i = 0; i < n; i++) { + register size_t j; + for (j = 0; j < n; j++) + r[i][j] = (i == j) ? 1.0 : 0.0; + return; + } +}