From patchwork Tue Feb 20 01:43:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 875364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zlk170hyXz9s08 for ; Tue, 20 Feb 2018 12:43:55 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NIZ/FT96"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3zlk166g5YzDrp2 for ; Tue, 20 Feb 2018 12:43:54 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NIZ/FT96"; dkim-atps=neutral X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NIZ/FT96"; dkim-atps=neutral Received: from mail-pg0-x244.google.com (mail-pg0-x244.google.com [IPv6:2607:f8b0:400e:c05::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3zlk136YCNzDrh3 for ; Tue, 20 Feb 2018 12:43:51 +1100 (AEDT) Received: by mail-pg0-x244.google.com with SMTP id m19so6552156pgn.1 for ; Mon, 19 Feb 2018 17:43:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=hRnbzntjcoWVIVTIk176wK/iiI+i0X5c3lUi8VEj4Wk=; b=NIZ/FT96OnexTB2QP+mryNspyo0Yi9O6w0n/Zv1nsKTXv5JPVaWZoWLxyxMa71Up14 2LSVVLHXnIDViEritksce2Cct6HhshNeBu7XAjs+cLqjpZYpVegcE03rh5O3ZpzcHrLx KfdFyXQ8vzPQ54kXXT+f++lBoP7E4dbGuv1nCAeBV5m9DHEG5L4DE0iBNnXJUPEfmEnd vrz15W8uJYQMZj5Uj11EfhpyLiPVLYKy/UjqYjMAcE/JoV+UlnicAoXWmh1eWVhusqR8 hMHRprom+L7STHnyNMyb9CF6+jsVXd/cDPtTvqtqe2ozcMYhu/ktV9RcEpjq5JVnp4NE 4Cuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=hRnbzntjcoWVIVTIk176wK/iiI+i0X5c3lUi8VEj4Wk=; b=Wbw58P5uJIxhYJtSzdnIF1kj6aYbhJg7Gbt0GHfVeQeEPiyAv91k6BD4tpKWY+qdqI jRmZIRPaou7Whhi4GprUGrSbvFDd/0UvMb/s0k6proGeUcpK0HzjLwhQ24AzI3xJ3KEY msPZY0xN31JRaV6GM1m5TcHDF239WexE8FVQ6wGg8ODiR/BPoGL3b9v0tGr0NCUQtKHh UA98llagj28u2YI+HWakDV+cp38wayi8oku5DV+83qzp8Hzk9JZ4gxJ28aLNXFGFSeCh axNrq6cF+6IgoXLpSHFx0NubLig/YXR7vQd/fTjUh44i30DPpAdRJCO2CUPKjpAPqjMh ByKA== X-Gm-Message-State: APf1xPDgzkxcclZzWlRdR6BH5S0OTcd8J3yfu3Y7gHgp0CynxQpQFWjS GeFiye5Wq26F+dDYQlsnWhc= X-Google-Smtp-Source: AH8x225R6sZeYcIQzCQ6WEez1TQJuzcfHOzM4+pN/MPlpACR0n+go+0m7xbNS51I4Za7TdATctLYyg== X-Received: by 10.99.107.198 with SMTP id g189mr13363150pgc.299.1519091029561; Mon, 19 Feb 2018 17:43:49 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id w22sm1517066pge.65.2018.02.19.17.43.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 17:43:48 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 20 Feb 2018 12:13:41 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Philipp Zabel , Andrew Jeffery Subject: [PATCH v2 1/3] dt-bindings: aspeed-lpc: Add reset controller Date: Tue, 20 Feb 2018 12:13:28 +1030 Message-Id: <20180220014330.23425-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180220014330.23425-1-joel@jms.id.au> References: <20180220014330.23425-1-joel@jms.id.au> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lee Jones , linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" This describes the reset controller present in the LPC address space. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley --- V2: Fix spelling mistakes --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..9bdd3e8c91ec 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,3 +135,24 @@ lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + +LPC reset control +----------------- + +The UARTs present in the ASPEED SoC can have their resets tied to the reset +state of the LPC bus. Some systems may chose to modify this configuration. + +Required properties: + + - compatible: "aspeed,ast2500-lpc-reset" or + "aspeed,ast2400-lpc-reset" + - reg: offset and length of the IP in the LHC memory region + - #reset-controller indicates the number of reset cells expected + +Example: + +lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; +}; From patchwork Tue Feb 20 01:43:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 875365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zlk1H2hGBz9s0b for ; Tue, 20 Feb 2018 12:44:03 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Mon, 19 Feb 2018 17:43:58 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id n25sm59008120pfk.152.2018.02.19.17.43.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 17:43:57 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 20 Feb 2018 12:13:50 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Philipp Zabel , Andrew Jeffery Subject: [PATCH v2 2/3] reset: simple: Enable for ASPEED systems Date: Tue, 20 Feb 2018 12:13:29 +1030 Message-Id: <20180220014330.23425-3-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180220014330.23425-1-joel@jms.id.au> References: <20180220014330.23425-1-joel@jms.id.au> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lee Jones , linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" ASPEED BMC SoCs have a reset controller in the LPC IP that can be controlled using this driver to release the UARTs from reset. No special configuration is required, so only the compatible string is added. Signed-off-by: Joel Stanley --- drivers/reset/Kconfig | 10 +++++++--- drivers/reset/reset-simple.c | 2 ++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7fc77696bb1e..18f152d251d7 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -83,14 +83,18 @@ config RESET_PISTACHIO config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX + default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, exclusive register space. - Currently this driver supports Altera SoCFPGAs, the RCC reset - controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family. + Currently this driver supports: + - Altera SoCFPGAs + - ASPEED BMC SoCs + - RCC reset controller in STM32 MCUs + - Allwinner SoCs + - ZTE's zx2967 family config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 2d4f362ef025..f7ce8910a392 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -125,6 +125,8 @@ static const struct of_device_id reset_simple_dt_ids[] = { .data = &reset_simple_active_low }, { .compatible = "zte,zx296718-reset", .data = &reset_simple_active_low }, + { .compatible = "aspeed,ast2400-lpc-reset" }, + { .compatible = "aspeed,ast2500-lpc-reset" }, { /* sentinel */ }, }; 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Mon, 19 Feb 2018 17:44:07 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id f8sm47813588pgs.51.2018.02.19.17.44.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 17:44:06 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 20 Feb 2018 12:13:58 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Philipp Zabel , Andrew Jeffery Subject: [PATCH v2 3/3] reset: simple: Allow user selection of driver Date: Tue, 20 Feb 2018 12:13:30 +1030 Message-Id: <20180220014330.23425-4-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180220014330.23425-1-joel@jms.id.au> References: <20180220014330.23425-1-joel@jms.id.au> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Lee Jones , linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Currently this driver is only user selectable if COMPILE_TEST is turned on. Users may wish to select (and deselect) it, so remove this restriction. Signed-off-by: Joel Stanley --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 18f152d251d7..7490a4370900 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -82,7 +82,7 @@ config RESET_PISTACHIO This enables the reset driver for ImgTec Pistachio SoCs. config RESET_SIMPLE - bool "Simple Reset Controller Driver" if COMPILE_TEST + bool "Simple Reset Controller Driver" default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED help This enables a simple reset controller driver for reset lines that