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Thu, 24 Mar 2022 06:21:32 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 01/14] crypto/fsl: Add support for CAAM Job ring driver model Date: Thu, 24 Mar 2022 11:50:25 +0530 Message-Id: <20220324062038.2187-2-gaurav.jain@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220324062038.2187-1-gaurav.jain@nxp.com> References: <20220324062038.2187-1-gaurav.jain@nxp.com> X-ClientProxiedBy: SGXP274CA0008.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::20) To VI1PR04MB5342.eurprd04.prod.outlook.com (2603:10a6:803:46::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 29a51053-8dbb-44b3-f7d8-08da0d5e8a61 X-MS-TrafficTypeDiagnostic: DB7PR04MB4442:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8snXhAzFBT6UIzrwZUHVnmLhuCeYJpee56eCmrVHr8ahJ1hSmGQPXcQssVTW1bioTTWMgIzRtQ3OwvyXDBlHtXuleCXKxM/x5cY5RDT/AUpLrEkUdl34uIJ8It8FZlKgROUxnXEry5luvMLg31kM9v9atg5l171KPzR5KezyWAAkQn6wH6rkZkFj4FQ79pQW5JbLJK7K8XNgoA+h3Cb8zQ2b7ubuGlEvbZ7CdkRqYjOCqGNJiyF/Ke8QDC6/7gx6BXtrUYHccZ1Gv33C0hF1ARmlElicwhq6d4OHIRp0S+7U+NFzZzt/LSd1jyXdr+4Z3J4YNH5Q0FDgdmLK4O/ljucihg7n3HbGMnK0EYhhBDvHmHqt4rLzwl1e3IIIz81D37YxCux1f+CNfK6j8QddfsSp7yuTSca3Ee3efaL0xzy29N5qya0hfvud6qckCwectRjOhyM+VvQcP7nNSxP7aVVF9KU5JiC30gEetFzJvndwV/NCChSday7l0bUEYT/H6qqqsEhvAWO7GdstU2BCbo/Glgnnr//l/QbhjsIZYyVIXZykWwYq8yeiFp7CQEqhbBuevDJrc5R83LA54qYWYZfpH5D1ZimDNJrrch8W5Aia3MDTaGL1oowiZYK94g17XS1vjGygkNvi8o6cgZvG9m/GlDyFS3YFiChlx2oL0/qHdmzfk0K8BfJ9I16Wrue66gNL/V3/0YG1BRWF9cK9dQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR04MB5342.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(2616005)(6512007)(316002)(2906002)(55236004)(6506007)(83380400001)(52116002)(30864003)(44832011)(6486002)(8676002)(36756003)(6916009)(54906003)(66946007)(66556008)(8936002)(4326008)(6666004)(5660300002)(38100700002)(38350700002)(26005)(1076003)(508600001)(186003)(86362001)(66476007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UNGOR+FTWu5X/dgMyncCivGFIrA8O7cBWaa3xANtcR+K3KC2qeCuf+PfpLO2ph34L6FkwjnqGvQUM8WckJjkPeQkp7uepFe3HI3Ay5e0CvSwL9BGSUr7RdcfaMIjzBCAIMaPehyDeN2mhoY9itVylsHikTkqwNN1iykDPEkxfYOZhibSmDRQHAKEvIThgknuEq6EF9kLo7/8jbOLEa8CM8AWh057LhA9xXpkSpK4E3+h8+l8VnCj5jFbiuATuLuki7xMC+LpnbOYG74LAmbL5rohVXC94UX/7ehL8EOjkJ/09bDL+x70y5wMOu9dN3XnL1z0fjlpBNlN+xGXEddJw1+Ovpr4nYNhvHzlLZhVNRsRJ6rEaqODPOA/43TVrp3P9g5kpnpvGQE3DPbaRFo0cJ9loi4voz8hoeG9L49eDexWvMijQphiSV4MbTnL9KmGBz82njOxACB15BvnZtqEmsV6KkaqF8Zc8k1l19EaFfpX3A9Xc58Lx6L+bsmfsoaMoLiWeS42sqEN6hbUvTsUWSxJ/I1MHKAO2uIRNhdLAlDDqPqUU3OC8R5dhqJDQREtkvh/I050WMmHf07CoPsZvFqNhnOV5FLCEaVn4D99V4xUbgnWlp/1YUcibb0391M4O3ZUDdeJVqsTJceec2Nxdkb4apTQkTA02juVTKgBnyePWesOgumzLpFPQVHXk2vsrW18QmpiVqDFH93hDUSF8LzwTWFq0qKaUIoAXuAOR8KosoodZaNxHkgxlBQ02by3TRHukXLY59NMy+LhOFhSIdGAQECjiEs6ehgpuznWstVohke8rYT5/Urh7QvAMet+SfIIq/UndOin1DOJuf54bDl0bBsUx20Iyksu1/PZVvAg5Ob7+bukySlVAMvOtls/w6ZPi99N+ZgTrZTDsKsX+7wHhoF6LTu1bIYjKz1FBM333NulRv5bQ2wPquqGD+sc3bI1yyCRkPv//JjF5uU9Y24HedTNOojVrQuEi3ymWHkYnw5YKJnXJWU4ixVa+KTc6tnazmBJl+Us43bD3kWUKd8cRwQARhj98HAGnWHy3r21k6/vdVoROSpdK8CV9OO+/rV+IK3VuKNqI+Q9C/FoVA1fdtpaRuJJsn8t685p394ERU+AfpHv2AUzM/+Y1k+iFSK1aIedoLDJzX8RV8K1vK6QWHrN7pfPmFCZUZJBPo0JZ+d5390Yw8OB+hRPNrx8Qws69NQqJJB5oLRbBi6nxY8gqCdRj9Mv3WIGUGxE9h2qaV+KaUncL88a3/wT5P/tgyIhL281+pguYwLZxrttSC8Zslwaj4lVNiTgjXqlMKEZCtph7ReZMkGCp4hWPao8QbGY+EmeSlIulYDCYMjmYDYoudUIBNM0N+dexuVVgFV3mCHrwrqq5LLbEL155dludPIglj0TlXxmgfZk5fxZQ5lervIg6XXWVhf8iD56ALD8RF+RwNHRC5WT2Oh5D4hk2AcqdKitnBLmtmv5V1JyLw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 29a51053-8dbb-44b3-f7d8-08da0d5e8a61 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5342.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 06:21:32.8765 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7tu4/ZnRItQlRZlG8WMEyqoXNBCnwiAA2NCXYonpcNe0/+SBzZT7XY/8OTRj9DZ/qHdAxJV7YsK4nKk2mitVVQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4442 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean added device tree support for job ring driver. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain Reviewed-by: Ye Li Reviewed-by: Simon Glass --- drivers/crypto/fsl/Kconfig | 1 + drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++------------- drivers/crypto/fsl/jr.h | 31 +++- 3 files changed, 241 insertions(+), 114 deletions(-) diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 94ff540111..231eb00b5f 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -2,6 +2,7 @@ config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL + select MISC if DM imply SPL_CRYPTO if (ARM && SPL) imply CMD_HASH help diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 22b649219e..8103987425 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * * Based on CAAM driver in drivers/crypto/caam in Linux */ @@ -11,7 +11,6 @@ #include #include #include -#include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" @@ -21,7 +20,10 @@ #include #include #endif +#include #include +#include +#include #include #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) @@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { #endif }; +#if CONFIG_IS_ENABLED(DM) +struct udevice *caam_dev; +#else #define SEC_ADDR(idx) \ (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) #define SEC_JR0_ADDR(idx) \ (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) +struct caam_regs caam_st; +#endif -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; +static inline u32 jr_start_reg(u8 jrid) +{ + return (1 << jrid); +} -static inline void start_jr0(uint8_t sec_idx) +static inline void start_jr(struct caam_regs *caam) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); + ccsr_sec_t *sec = caam->sec; u32 ctpr_ms = sec_in32(&sec->ctpr_ms); u32 scfgr = sec_in32(&sec->scfgr); + u32 jrstart = jr_start_reg(caam->jrid); if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) { /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx) */ if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) || (scfgr & SEC_SCFGR_VIRT_EN)) - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + sec_out32(&sec->jrstartr, jrstart); } else { /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + sec_out32(&sec->jrstartr, jrstart); } } -static inline void jr_reset_liodn(uint8_t sec_idx) +static inline void jr_disable_irq(struct jr_regs *regs) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); - sec_out32(&sec->jrliodnr[0].ls, 0); -} - -static inline void jr_disable_irq(uint8_t sec_idx) -{ - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t jrcfg = sec_in32(®s->jrcfg1); jrcfg = jrcfg | JR_INTMASK; @@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx) sec_out32(®s->jrcfg1, jrcfg); } -static void jr_initregs(uint8_t sec_idx) +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring); caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring); @@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx) sec_out32(®s->irs, JR_SIZE); if (!jr->irq) - jr_disable_irq(sec_idx); + jr_disable_irq(regs); } -static int jr_init(uint8_t sec_idx) +static int jr_init(uint8_t sec_idx, struct caam_regs *caam) { - struct jobring *jr = &jr0[sec_idx]; + struct jobring *jr = &caam->jr[sec_idx]; memset(jr, 0, sizeof(struct jobring)); - jr->jq_id = DEFAULT_JR_ID; + jr->jq_id = caam->jrid; jr->irq = DEFAULT_IRQ; #ifdef CONFIG_FSL_CORENET @@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx) memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); - start_jr0(sec_idx); - - jr_initregs(sec_idx); - - return 0; -} - -static int jr_sw_cleanup(uint8_t sec_idx) -{ - struct jobring *jr = &jr0[sec_idx]; - - jr->head = 0; - jr->tail = 0; - jr->read_idx = 0; - jr->write_idx = 0; - memset(jr->info, 0, sizeof(jr->info)); - memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t)); - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); - - return 0; -} - -static int jr_hw_reset(uint8_t sec_idx) -{ - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - uint32_t timeout = 100000; - uint32_t jrint, jrcr; - - sec_out32(®s->jrcr, JRCR_RESET); - do { - jrint = sec_in32(®s->jrint); - } while (((jrint & JRINT_ERR_HALT_MASK) == - JRINT_ERR_HALT_INPROGRESS) && --timeout); - - jrint = sec_in32(®s->jrint); - if (((jrint & JRINT_ERR_HALT_MASK) != - JRINT_ERR_HALT_INPROGRESS) && timeout == 0) - return -1; - - timeout = 100000; - sec_out32(®s->jrcr, JRCR_RESET); - do { - jrcr = sec_in32(®s->jrcr); - } while ((jrcr & JRCR_RESET) && --timeout); - - if (timeout == 0) - return -1; + start_jr(caam); + jr_initregs(sec_idx, caam); return 0; } @@ -188,10 +147,10 @@ static int jr_hw_reset(uint8_t sec_idx) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, void (*callback)(uint32_t status, void *arg), - void *arg, uint8_t sec_idx) + void *arg, uint8_t sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; int head = jr->head; uint32_t desc_word; int length = desc_len(desc_addr); @@ -263,10 +222,10 @@ static int jr_enqueue(uint32_t *desc_addr, return 0; } -static int jr_dequeue(int sec_idx) +static int jr_dequeue(int sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; int head = jr->head; int tail = jr->tail; int idx, i, found; @@ -349,14 +308,18 @@ static void desc_done(uint32_t status, void *arg) { struct result *x = arg; x->status = status; -#ifndef CONFIG_SPL_BUILD caam_jr_strstatus(status); -#endif x->done = 1; } static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif unsigned long long timeval = 0; unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT; struct result op; @@ -364,7 +327,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) memset(&op, 0, sizeof(op)); - ret = jr_enqueue(desc, desc_done, &op, sec_idx); + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam); if (ret) { debug("Error in SEC enq\n"); ret = JQ_ENQ_ERR; @@ -375,7 +338,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) udelay(1); timeval += 1; - ret = jr_dequeue(sec_idx); + ret = jr_dequeue(sec_idx, caam); if (ret) { debug("Error in SEC deq\n"); ret = JQ_DEQ_ERR; @@ -402,13 +365,62 @@ int run_descriptor_jr(uint32_t *desc) return run_descriptor_jr_idx(desc, 0); } +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) +{ + struct jobring *jr = &caam->jr[sec_idx]; + + jr->head = 0; + jr->tail = 0; + jr->read_idx = 0; + jr->write_idx = 0; + memset(jr->info, 0, sizeof(jr->info)); + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t)); + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); + + return 0; +} + +static int jr_hw_reset(struct jr_regs *regs) +{ + uint32_t timeout = 100000; + uint32_t jrint, jrcr; + + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrint = sec_in32(®s->jrint); + } while (((jrint & JRINT_ERR_HALT_MASK) == + JRINT_ERR_HALT_INPROGRESS) && --timeout); + + jrint = sec_in32(®s->jrint); + if (((jrint & JRINT_ERR_HALT_MASK) != + JRINT_ERR_HALT_INPROGRESS) && timeout == 0) + return -1; + + timeout = 100000; + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrcr = sec_in32(®s->jrcr); + } while ((jrcr & JRCR_RESET) && --timeout); + + if (timeout == 0) + return -1; + + return 0; +} + static inline int jr_reset_sec(uint8_t sec_idx) { - if (jr_hw_reset(sec_idx) < 0) + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif + if (jr_hw_reset(caam->regs) < 0) return -1; /* Clean up the jobring structure maintained by software */ - jr_sw_cleanup(sec_idx); + jr_sw_cleanup(sec_idx, caam); return 0; } @@ -418,9 +430,15 @@ int jr_reset(void) return jr_reset_sec(0); } -static inline int sec_reset_idx(uint8_t sec_idx) +int sec_reset(void) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif + ccsr_sec_t *sec = caam->sec; uint32_t mcfgr = sec_in32(&sec->mcfgr); uint32_t timeout = 100000; @@ -446,11 +464,7 @@ static inline int sec_reset_idx(uint8_t sec_idx) return 0; } -int sec_reset(void) -{ - return sec_reset_idx(0); -} -#ifndef CONFIG_SPL_BUILD + static int deinstantiate_rng(u8 sec_idx, int state_handle_mask) { u32 *desc; @@ -496,12 +510,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask) return ret; } -static int instantiate_rng(u8 sec_idx, int gen_sk) +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk) { u32 *desc; u32 rdsta_val; int ret = 0, sh_idx, size; - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -554,9 +567,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk) return ret; } -static u8 get_rng_vid(uint8_t sec_idx) +static u8 get_rng_vid(ccsr_sec_t *sec) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u8 vid; if (caam_get_era() < 10) { @@ -574,9 +586,8 @@ static u8 get_rng_vid(uint8_t sec_idx) * By default, the TRNG runs for 200 clocks per sample; * 1200 clocks per sample generates better entropy. */ -static void kick_trng(int ent_delay, uint8_t sec_idx) +static void kick_trng(int ent_delay, ccsr_sec_t *sec) { - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 val; @@ -603,10 +614,9 @@ static void kick_trng(int ent_delay, uint8_t sec_idx) sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } -static int rng_init(uint8_t sec_idx) +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) { int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 inst_handles; @@ -624,7 +634,7 @@ static int rng_init(uint8_t sec_idx) * the TRNG parameters. */ if (!inst_handles) { - kick_trng(ent_delay, sec_idx); + kick_trng(ent_delay, sec); ent_delay += 400; } /* @@ -634,7 +644,7 @@ static int rng_init(uint8_t sec_idx) * interval, leading to a sucessful initialization of * the RNG. */ - ret = instantiate_rng(sec_idx, gen_sk); + ret = instantiate_rng(sec_idx, sec, gen_sk); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("SEC%u: Failed to instantiate RNG\n", sec_idx); @@ -646,13 +656,28 @@ static int rng_init(uint8_t sec_idx) return ret; } -#endif + int sec_init_idx(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); - uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; - + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + if (!caam_dev) { + printf("caam_jr: caam not found\n"); + return -1; + } + caam = dev_get_priv(caam_dev); +#else + caam_st.sec = (void *)SEC_ADDR(sec_idx); + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + caam_st.jrid = 0; + caam = &caam_st; +#endif + ccsr_sec_t *sec = caam->sec; + uint32_t mcr = sec_in32(&sec->mcfgr); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) + uint32_t jrdid_ms = 0; +#endif #ifdef CONFIG_FSL_CORENET uint32_t liodnr; uint32_t liodn_ns; @@ -682,6 +707,11 @@ int sec_init_idx(uint8_t sec_idx) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID; + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); +#endif + jr_reset(); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SPL_BUILD @@ -693,20 +723,19 @@ int sec_init_idx(uint8_t sec_idx) liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK; liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK; - liodnr = sec_in32(&sec->jrliodnr[0].ls) & + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) & ~(JRNSLIODN_MASK | JRSLIODN_MASK); liodnr = liodnr | (liodn_ns << JRNSLIODN_SHIFT) | (liodn_s << JRSLIODN_SHIFT); - sec_out32(&sec->jrliodnr[0].ls, liodnr); + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr); #else - liodnr = sec_in32(&sec->jrliodnr[0].ls); + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls); liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif #endif - - ret = jr_init(sec_idx); + ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); return -1; @@ -719,9 +748,9 @@ int sec_init_idx(uint8_t sec_idx) pamu_enable(); #endif -#ifndef CONFIG_SPL_BUILD - if (get_rng_vid(sec_idx) >= 4) { - if (rng_init(sec_idx) < 0) { + + if (get_rng_vid(caam->sec) >= 4) { + if (rng_init(sec_idx, caam->sec) < 0) { printf("SEC%u: RNG instantiation failed\n", sec_idx); return -1; } @@ -735,7 +764,6 @@ int sec_init_idx(uint8_t sec_idx) printf("SEC%u: RNG instantiated\n", sec_idx); } -#endif return ret; } @@ -743,3 +771,76 @@ int sec_init(void) { return sec_init_idx(0); } + +#if CONFIG_IS_ENABLED(DM) +static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf) +{ + if (request != CAAM_JR_RUN_DESC) + return -ENOSYS; + + return run_descriptor_jr(buf); +} + +static int caam_jr_probe(struct udevice *dev) +{ + struct caam_regs *caam = dev_get_priv(dev); + fdt_addr_t addr; + ofnode node; + unsigned int jr_node = 0; + + caam_dev = dev; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + printf("caam_jr: crypto not found\n"); + return -EINVAL; + } + caam->sec = (ccsr_sec_t *)(uintptr_t)addr; + caam->regs = (struct jr_regs *)caam->sec; + + /* Check for enabled job ring node */ + ofnode_for_each_subnode(node, dev_ofnode(dev)) { + if (!ofnode_is_available(node)) + continue; + + jr_node = ofnode_read_u32_default(node, "reg", -1); + if (jr_node > 0) { + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node); + while (!(jr_node & 0x0F)) + jr_node = jr_node >> 4; + + caam->jrid = jr_node - 1; + break; + } + } + + if (sec_init()) + printf("\nsec_init failed!\n"); + + return 0; +} + +static int caam_jr_bind(struct udevice *dev) +{ + return 0; +} + +static const struct misc_ops caam_jr_ops = { + .ioctl = caam_jr_ioctl, +}; + +static const struct udevice_id caam_jr_match[] = { + { .compatible = "fsl,sec-v4.0" }, + { } +}; + +U_BOOT_DRIVER(caam_jr) = { + .name = "caam_jr", + .id = UCLASS_MISC, + .of_match = caam_jr_match, + .ops = &caam_jr_ops, + .bind = caam_jr_bind, + .probe = caam_jr_probe, + .priv_auto = sizeof(struct caam_regs), +}; +#endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 1047aa772c..3eb7be79da 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP * */ @@ -8,7 +9,9 @@ #define __JR_H #include +#include "fsl_sec.h" #include "type.h" +#include #define JR_SIZE 4 /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@ #define JRSLIODN_SHIFT 0 #define JRSLIODN_MASK 0x00000fff -#define JQ_DEQ_ERR -1 -#define JQ_DEQ_TO_ERR -2 -#define JQ_ENQ_ERR -3 +#define JRDID_MS_PRIM_DID BIT(0) +#define JRDID_MS_PRIM_TZ BIT(4) +#define JRDID_MS_TZ_OWN BIT(15) + +#define JQ_DEQ_ERR (-1) +#define JQ_DEQ_TO_ERR (-2) +#define JQ_ENQ_ERR (-3) #define RNG4_MAX_HANDLES 2 +enum { + /* Run caam jobring descriptor(in buf) */ + CAAM_JR_RUN_DESC, +}; + struct op_ring { caam_dma_addr_t desc; uint32_t status; @@ -102,6 +114,19 @@ struct result { uint32_t status; }; +/* + * struct caam_regs - CAAM initialization register interface + * + * Interface to caam memory map, jobring register, jobring storage. + */ +struct caam_regs { + ccsr_sec_t *sec; /*caam initialization registers*/ + struct jr_regs *regs; /*jobring configuration registers*/ + u8 jrid; /*id to identify a jobring*/ + /*Private sub-storage for a single JobR*/ + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; +}; + void caam_jr_strstatus(u32 status); int run_descriptor_jr(uint32_t *desc); From patchwork Thu Mar 24 06:20:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav Jain X-Patchwork-Id: 1608907 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; 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Thu, 24 Mar 2022 06:21:39 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . 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}; +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 2e39790766..6f70722586 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ / { @@ -104,6 +104,22 @@ u-boot,dm-spl; }; +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index ab849ebaac..52f473dc52 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include "imx8mp-u-boot.dtsi" @@ -67,6 +67,22 @@ u-boot,dm-spl; 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Thu, 24 Mar 2022 06:21:46 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 03/14] crypto/fsl: i.MX8M: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/Kconfig | 2 +- arch/arm/mach-imx/imx8m/Kconfig | 13 +++++++++++++ arch/arm/mach-imx/imx8m/soc.c | 11 ++++++++++- board/freescale/imx8mm_evk/spl.c | 10 +++++++++- board/freescale/imx8mn_evk/spl.c | 9 +++++++-- board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++-- board/freescale/imx8mq_evk/spl.c | 8 ++++++-- 7 files changed, 58 insertions(+), 9 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4567c183fb..f207e709d4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -817,7 +817,7 @@ config ARCH_IMX8M select ARM64 select GPIO_EXTRA_HEADER select MACH_IMX - select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE select SYS_I2C_MXC diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index fae7049995..f564e0dd6f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -39,6 +39,9 @@ config TARGET_IMX8MQ_EVK select BINMAN select IMX8MQ select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" @@ -52,6 +55,9 @@ config TARGET_IMX8MM_EVK select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" @@ -91,6 +97,8 @@ config TARGET_IMX8MN_EVK select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select SPL_CRYPTO if SPL config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" @@ -98,6 +106,8 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 + select FSL_CAAM + select SPL_CRYPTO if SPL config TARGET_IMX8MN_VENICE bool "Support Gateworks Venice iMX8M Nano module" @@ -112,6 +122,9 @@ config TARGET_IMX8MP_EVK select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1a5a391443..17efe37447 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2019, 2021 NXP * * Peng Fan */ @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -1210,6 +1211,14 @@ static void acquire_buildinfo(void) int arch_misc_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } acquire_buildinfo(); return 0; diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 4ef7f6f180..cf4882cd10 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -51,6 +51,14 @@ static void spl_dram_init(void) void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } puts("Normal Boot\n"); } diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 03f2a56e80..dfa81a0d65 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -49,6 +49,11 @@ void spl_board_init(void) struct udevice *dev; int ret; + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } puts("Normal Boot\n"); ret = uclass_get_device_by_name(UCLASS_CLK, diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index eca42c756e..503a752ae9 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018-2019 NXP + * Copyright 2018-2019, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -20,6 +20,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -35,6 +37,14 @@ void spl_dram_init(void) void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } /* * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does * not allow to change it. Should set the clock after PMIC diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 67d069b2b0..b28056bb48 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -22,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -199,6 +199,10 @@ int power_init_board(void) void spl_board_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + if (sec_init()) + printf("\nsec_init failed!\n"); + } puts("Normal Boot\n"); } From patchwork Thu Mar 24 06:20:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav Jain X-Patchwork-Id: 1608909 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Thu, 24 Mar 2022 06:21:53 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . 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Signed-off-by: Ye Li Reviewed-by: Fabio Estevam Reviewed-by: Gaurav Jain --- configs/mx6sabreauto_defconfig | 2 -- configs/mx6sabresd_defconfig | 4 ---- 2 files changed, 6 deletions(-) diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 1bf86d0137..aa1f0762f5 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -62,10 +62,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto" CONFIG_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 233a1652a6..4fb95943fc 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -65,12 +65,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd" CONFIG_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd" -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y From patchwork Thu Mar 24 06:20:29 2022 Content-Type: text/plain; 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Thu, 24 Mar 2022 06:22:00 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 05/14] i.MX6: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/mach-imx/mx6/Kconfig | 10 ++++++++++ arch/arm/mach-imx/mx6/soc.c | 13 +++++++++---- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 98df4d4e42..3d675fcd73 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -354,6 +354,8 @@ config TARGET_MX6SABREAUTO select DM_THERMAL select SUPPORT_SPL imply CMD_DM + select FSL_CAAM + select ARCH_MISC_INIT config TARGET_MX6SABRESD bool "mx6sabresd" @@ -364,6 +366,8 @@ config TARGET_MX6SABRESD select DM_THERMAL select SUPPORT_SPL imply CMD_DM + select FSL_CAAM + select ARCH_MISC_INIT config TARGET_MX6SLEVK bool "mx6slevk" @@ -386,6 +390,8 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL select SUPPORT_SPL + select FSL_CAAM + select ARCH_MISC_INIT config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" @@ -404,6 +410,8 @@ config TARGET_MX6UL_9X9_EVK select DM_THERMAL select SUPPORT_SPL imply CMD_DM + select FSL_CAAM + select ARCH_MISC_INIT config TARGET_MX6UL_14X14_EVK bool "mx6ul_14x14_evk" @@ -413,6 +421,8 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL imply CMD_DM + select FSL_CAAM + select ARCH_MISC_INIT config TARGET_MX6UL_ENGICAM bool "Support Engicam GEAM6UL/Is.IoT" diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 03d6b8c1ce..2434bcfa98 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -4,6 +4,7 @@ * Sascha Hauer, Pengutronix * * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include @@ -738,9 +738,14 @@ static void setup_serial_number(void) int arch_misc_init(void) { -#ifdef CONFIG_FSL_CAAM - sec_init(); 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Thu, 24 Mar 2022 06:22:07 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 06/14] i.MX7: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/Kconfig | 2 +- arch/arm/mach-imx/mx7/Kconfig | 1 + arch/arm/mach-imx/mx7/soc.c | 12 ++++++++---- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f207e709d4..c2f13e0e33 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -885,7 +885,7 @@ config ARCH_MX7 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX - select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE imply BOARD_EARLY_INIT_F diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 0cad825287..4f9f51c9b0 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -68,6 +68,7 @@ config TARGET_MX7DSABRESD select DM_THERMAL select MX7D imply CMD_DM + select FSL_CAAM config TARGET_PICO_IMX7D bool "pico-imx7d" diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index f6aec5a3aa..dc9ac31eb0 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -20,7 +21,6 @@ #include #include #include -#include #include #include @@ -356,9 +356,13 @@ int arch_misc_init(void) env_set("serial#", serial_string); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } return 0; } From patchwork Thu Mar 24 06:20:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav Jain X-Patchwork-Id: 1608912 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256 header.s=selector2 header.b=sa1/G8ch; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Thu, 24 Mar 2022 06:22:14 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 07/14] i.MX7ULP: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/Kconfig | 2 +- arch/arm/dts/imx7ulp.dtsi | 24 ++++++++++++++++++++++++ arch/arm/mach-imx/mx7ulp/Kconfig | 2 ++ arch/arm/mach-imx/mx7ulp/soc.c | 18 ++++++++++++++++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c2f13e0e33..f39f77b786 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -872,7 +872,7 @@ config ARCH_MX7ULP select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX - select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE select ROM_UNIFIED_SECTIONS diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi index 7bcd2cc346..494b9d98b2 100644 --- a/arch/arm/dts/imx7ulp.dtsi +++ b/arch/arm/dts/imx7ulp.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -198,6 +199,29 @@ }; }; + crypto: crypto@40240000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40240000 0x10000>; + ranges = <0 0x40240000 0x10000>; + clocks = <&clks IMX7ULP_CLK_CAAM>, + <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + tpm5: tpm@40260000 { compatible = "fsl,imx7ulp-tpm"; reg = <0x40260000 0x1000>; diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 15c3ab6dae..615d75bdd0 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -40,6 +40,8 @@ config TARGET_MX7ULP_EVK bool "Support mx7ulp EVK board" select MX7ULP select SYS_ARCH_TIMER + select FSL_CAAM + select ARCH_MISC_INIT endchoice diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index bc41cbc687..08bdc0c4af 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -16,6 +17,7 @@ #include #include #include +#include #define PMC0_BASE_ADDR 0x410a1000 #define PMC0_CTRL 0x28 @@ -82,6 +84,22 @@ int arch_cpu_init(void) return 0; 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Thu, 24 Mar 2022 06:22:21 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . 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Signed-off-by: Gaurav Jain Reviewed-by: Ye Li --- arch/arm/dts/fsl-imx8dx.dtsi | 61 +++++++++++++++++++++++- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 ++++++++++++- arch/arm/dts/fsl-imx8qm.dtsi | 61 +++++++++++++++++++++++- arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 ++++++++++++- 4 files changed, 186 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 7d95cf0b7d..63a56699b5 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include @@ -261,6 +261,30 @@ power-domains = <&pd_dma>; }; }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; }; i2c0: i2c@5a800000 { @@ -609,6 +633,41 @@ }; }; }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; }; &A35_0 { diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 9e0d264b71..a95209e141 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ &{/imx8qm-pm} { @@ -80,6 +80,22 @@ u-boot,dm-spl; }; +&pd_caam { + u-boot,dm-spl; +}; + +&pd_caam_jr1 { + u-boot,dm-spl; +}; + +&pd_caam_jr2 { + u-boot,dm-spl; +}; + +&pd_caam_jr3 { + u-boot,dm-spl; +}; + &gpio0 { u-boot,dm-spl; }; @@ -126,3 +142,19 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index 88aeaf65b3..517fb13cad 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include @@ -235,6 +235,30 @@ wakeup-irq = <349>; }; }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; }; i2c0: i2c@5a800000 { @@ -556,6 +580,41 @@ power-domains = <&pd_conn_enet1>; status = "disabled"; }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; }; &A53_0 { diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 701af4434d..ae037c7550 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ &{/imx8qx-pm} { @@ -80,6 +80,22 @@ u-boot,dm-spl; }; +&pd_caam { + u-boot,dm-spl; +}; + +&pd_caam_jr1 { + u-boot,dm-spl; +}; + +&pd_caam_jr2 { + u-boot,dm-spl; +}; + +&pd_caam_jr3 { + u-boot,dm-spl; +}; + &gpio0 { u-boot,dm-spl; }; @@ -126,3 +142,19 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; From patchwork Thu Mar 24 06:20:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gaurav Jain X-Patchwork-Id: 1608914 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Thu, 24 Mar 2022 06:22:28 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 09/14] crypto/fsl: i.MX8: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Signed-off-by: Horia Geantă Reviewed-by: Ye Li --- arch/arm/Kconfig | 3 ++ arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++- arch/arm/mach-imx/cmd_dek.c | 1 + arch/arm/mach-imx/imx8/Kconfig | 7 ++++ arch/arm/mach-imx/imx8/cpu.c | 18 ++++++++- board/freescale/imx8qm_mek/spl.c | 6 ++- board/freescale/imx8qxp_mek/spl.c | 6 ++- drivers/crypto/fsl/Kconfig | 2 +- drivers/crypto/fsl/jr.c | 47 ++++++++++++++++++++++- include/fsl_sec.h | 12 +++--- 10 files changed, 91 insertions(+), 16 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f39f77b786..36b7ebec58 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -806,6 +806,9 @@ config ARCH_LPC32XX config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select GPIO_EXTRA_HEADER select MACH_IMX diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index ed6e05e556..2d64b0604b 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __ASM_ARCH_IMX8_REGS_H__ @@ -47,4 +47,7 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 89da89c51d..04c4b20a84 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index b43739e5c6..f969833bab 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -8,6 +8,7 @@ config AHAB_BOOT config IMX8 bool + select HAS_CAAM config MU_BASE_SPL hex "MU base address used in SPL" @@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT select IMX8QM + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" @@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT select IMX8QXP + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL endchoice diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index ee5cc47903..991908fbd3 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #include @@ -89,6 +89,22 @@ int arch_cpu_init_dm(void) return 0; } +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + + return 0; +} +#endif + int print_bootinfo(void) { enum boot_device bt_dev = get_boot_device(); diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index 944ba745c0..332a662dee 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -24,6 +24,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index ae6b64ff6e..2fa6840056 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -1,7 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -39,6 +39,8 @@ void spl_board_init(void) { struct udevice *dev; + uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 231eb00b5f..e03fcdd9c7 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -12,7 +12,7 @@ config FSL_CAAM config CAAM_64BIT bool - default y if PHYS_64BIT && !ARCH_IMX8M + default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8103987425..1d951cf0a6 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" @@ -113,7 +114,9 @@ static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam) static int jr_init(uint8_t sec_idx, struct caam_regs *caam) { struct jobring *jr = &caam->jr[sec_idx]; - +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); +#endif memset(jr, 0, sizeof(struct jobring)); jr->jq_id = caam->jrid; @@ -138,7 +141,11 @@ static int jr_init(uint8_t sec_idx, struct caam_regs *caam) memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (!ofnode_valid(scu_node)) +#endif start_jr(caam); + jr_initregs(sec_idx, caam); return 0; @@ -673,6 +680,13 @@ int sec_init_idx(uint8_t sec_idx) caam_st.jrid = 0; caam = &caam_st; #endif +#if CONFIG_IS_ENABLED(OF_CONTROL) + ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + + if (ofnode_valid(scu_node)) + goto init; +#endif + ccsr_sec_t *sec = caam->sec; uint32_t mcr = sec_in32(&sec->mcfgr); #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) @@ -734,12 +748,19 @@ int sec_init_idx(uint8_t sec_idx) liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif +#endif +#if CONFIG_IS_ENABLED(OF_CONTROL) +init: #endif ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); return -1; } +#if CONFIG_IS_ENABLED(OF_CONTROL) + if (ofnode_valid(scu_node)) + return ret; +#endif #ifdef CONFIG_FSL_CORENET ret = sec_config_pamu_table(liodn_ns, liodn_s); @@ -773,6 +794,23 @@ int sec_init(void) } #if CONFIG_IS_ENABLED(DM) +static int jr_power_on(ofnode node) +{ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice __maybe_unused jr_dev; + struct power_domain pd; + + dev_set_ofnode(&jr_dev, node); + + /* Power on Job Ring before access it */ + if (!power_domain_get(&jr_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + return 0; +} + static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf) { if (request != CAAM_JR_RUN_DESC) @@ -785,7 +823,7 @@ static int caam_jr_probe(struct udevice *dev) { struct caam_regs *caam = dev_get_priv(dev); fdt_addr_t addr; - ofnode node; + ofnode node, scu_node; unsigned int jr_node = 0; caam_dev = dev; @@ -810,6 +848,11 @@ static int caam_jr_probe(struct udevice *dev) jr_node = jr_node >> 4; caam->jrid = jr_node - 1; + scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu"); + if (ofnode_valid(scu_node)) { + if (jr_power_on(node)) + return -EINVAL; + } break; } } diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c4121696f8..7b6e3e2c20 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -3,7 +3,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2021 NXP */ #ifndef __FSL_SEC_H @@ -194,12 +194,10 @@ typedef struct ccsr_sec { #define SEC_CHAVID_LS_RNG_SHIFT 16 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 -#define CONFIG_JRSTARTR_JR0 0x00000001 - struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 irba_l; u32 irba_h; #else @@ -214,7 +212,7 @@ struct jr_regs { u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 orba_l; u32 orba_h; #else @@ -248,7 +246,7 @@ struct jr_regs { struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -268,7 +266,7 @@ struct sg_entry { }; #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ From patchwork Thu Mar 24 06:20:34 2022 Content-Type: text/plain; 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Thu, 24 Mar 2022 06:22:34 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . 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}; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + gpio0: gpio@2300000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 52dc5a9638..72877d2ff5 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Include file for NXP Layerscape-1043A family SoC. * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * Copyright (C) 2014-2015, Freescale Semiconductor * * Mingkai Hu @@ -125,6 +125,49 @@ interrupts = <0 43 0x4>; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index a60cbf11fc..c655e002aa 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -3,6 +3,7 @@ * Device Tree Include file for Freescale Layerscape-1046A family SoC. * * Copyright (C) 2016, Freescale Semiconductor + * Copyright 2021 NXP * * Mingkai Hu */ @@ -124,6 +125,49 @@ interrupts = <0 43 0x4>; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index f73fdfda8b..9b7c54b260 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -174,6 +174,45 @@ dr_mode = "host"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 72ba52594a..a1837454f4 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -239,6 +239,45 @@ status = "disabled"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <0 139 0x4>; /* Level high type */ + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 140 0x4>; /* Level high type */ + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 141 0x4>; /* Level high type */ + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 142 0x4>; /* Level high type */ + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 143 0x4>; /* Level high type */ + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc", "simple-mfd"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 52e4d7205a..57c7d3ef71 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /* * NXP lx2160a SOC common device tree source * - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * */ @@ -27,6 +27,45 @@ clock-output-names = "sysclk"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + clockgen: clocking@1300000 { compatible = "fsl,ls2080a-clockgen"; reg = <0 0x1300000 0 0xa0000>; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 86192cbb7f..be330c130f 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -3,6 +3,7 @@ * Freescale ls1021a SOC common device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include "skeleton.dtsi" @@ -144,6 +145,45 @@ big-endian; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <7>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700000 0x100000>; + ranges = <0x0 0x1700000 0x100000>; + interrupts = ; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + + }; + clockgen: clocking@1ee1000 { #address-cells = <1>; #size-cells = <1>; From patchwork Thu Mar 24 06:20:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gaurav Jain X-Patchwork-Id: 1608916 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256 header.s=selector2 header.b=pHmOoLV/; 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Thu, 24 Mar 2022 06:22:41 +0000 From: Gaurav Jain To: u-boot@lists.denx.de, Stefano Babic Cc: Fabio Estevam , Peng Fan , Simon Glass , Michael Walle , Priyanka Jain , Ye Li , Horia Geanta , Ji Luo , Franck Lenormand , Silvano Di Ninno , Sahil malhotra , Pankaj Gupta , Varun Sethi , "NXP i . MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 11/14] Layerscape: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Priyanka Jain Reviewed-by: Michael Walle --- arch/arm/cpu/armv7/ls102xa/cpu.c | 18 ++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 11 ++++++++++- board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +------ board/freescale/ls1012aqds/ls1012aqds.c | 6 +----- board/freescale/ls1012ardb/ls1012ardb.c | 6 +----- board/freescale/ls1021aiot/ls1021aiot.c | 6 ++---- board/freescale/ls1021aqds/ls1021aqds.c | 6 +----- board/freescale/ls1021atsn/ls1021atsn.c | 7 ++----- board/freescale/ls1021atwr/ls1021atwr.c | 8 ++------ board/freescale/ls1028a/ls1028a.c | 6 +----- board/freescale/ls1043ardb/ls1043ardb.c | 6 +----- board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +------ board/freescale/ls1046aqds/ls1046aqds.c | 7 +------ board/freescale/ls1046ardb/ls1046ardb.c | 6 +----- board/freescale/ls1088a/ls1088a.c | 4 ---- board/freescale/ls2080aqds/ls2080aqds.c | 6 +----- board/freescale/ls2080ardb/ls2080ardb.c | 9 +-------- board/freescale/lx2160a/lx2160a.c | 5 ----- board/kontron/sl28/sl28.c | 3 --- configs/ls1021aiot_qspi_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1043ardb_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1043ardb_tfa_defconfig | 1 + configs/ls1046afrwy_tfa_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + 62 files changed, 88 insertions(+), 89 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d863c9625a..9fe1cd9048 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -20,6 +21,7 @@ #include #include #include +#include #include "fsl_epu.h" @@ -397,3 +399,19 @@ void arch_preboot_os(void) ctrl &= ~ARCH_TIMER_CTRL_ENABLE; asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); } + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2ded3e4efc..0fffddab71 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2020 NXP + * Copyright 2017-2021 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -49,6 +49,7 @@ #endif #endif #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1650,6 +1651,14 @@ __weak int serdes_misc_init(void) int arch_misc_init(void) { + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } serdes_misc_init(); return 0; diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 5dd19cfcd9..bc37c553a5 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2021 NXP */ #include @@ -22,7 +22,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -172,10 +171,6 @@ int board_init(void) if (current_el() == 3) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 68578e81a5..361bd5c582 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -28,7 +29,6 @@ #include #include #include -#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -150,10 +150,6 @@ int board_init(void) erratum_a010315(); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 064fb4d39f..456609d993 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -27,7 +28,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -173,10 +173,6 @@ int board_init(void) erratum_a010315(); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index bfe6137604..5ab03b3340 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -209,10 +210,7 @@ int misc_init_r(void) device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 0647622cde..2eaad9e742 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -388,9 +387,6 @@ int misc_init_r(void) #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif -#ifdef CONFIG_FSL_CAAM - return sec_init(); #endif return 0; } diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index f31e16c419..f016088670 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2019 NXP +/* Copyright 2016-2019, 2021 NXP */ #include #include @@ -238,10 +238,7 @@ int misc_init_r(void) #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index f0b441db63..a2a87eaf35 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -555,10 +554,7 @@ int misc_init_r(void) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_board_mux(); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 486a544d35..71a086ef67 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -73,10 +73,6 @@ u32 get_lpuart_clk(void) int board_init(void) { -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 1764c9336c..002869f435 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -20,7 +21,6 @@ #include #include #include -#include #include "cpld.h" #ifdef CONFIG_U_QE #include @@ -211,10 +211,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index f1c08a13f7..5a298cd311 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -20,7 +20,6 @@ #include #include #include -#include #include #include "../common/i2c_mux.h" @@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8481c45a58..e5b5441e2c 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #include @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "../common/i2c_mux.h" @@ -421,10 +420,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - return 0; } diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index d0abfe8869..25f728b9b3 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -23,7 +24,6 @@ #include #include #include "cpld.h" -#include DECLARE_GLOBAL_DATA_PTR; @@ -85,10 +85,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 63e824c374..5bf13dcdeb 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -820,9 +819,6 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 297629d5ef..5bdafebb6b 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor + * Copyright 2021 NXP */ #include #include @@ -21,7 +22,6 @@ #include #include #include -#include #include #include #include "../common/i2c_mux.h" @@ -222,10 +222,6 @@ int board_init(void) #endif #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 1975b0f47d..f5ebb934eb 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor - * Copyright 2017 NXP + * Copyright 2017, 2021 NXP */ #include #include @@ -24,7 +24,6 @@ #include #include #include -#include #include #include "../common/i2c_mux.h" @@ -288,9 +287,6 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -299,9 +295,6 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) pci_init(); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index c9835f9299..49d96d3fa2 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -593,10 +592,6 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) pci_init(); #endif diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 3c48a9141d..17bb457736 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -31,9 +31,6 @@ int board_early_init_f(void) int board_init(void) { - if (CONFIG_IS_ENABLED(FSL_CAAM)) - sec_init(); - return 0; } diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 911b4dba3a..f8de2af594 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -40,6 +40,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index f72f2b1bb5..8834e4490b 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -57,6 +57,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 925d68db8e..33ef9e871c 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index c71c8649d9..2a639e82f2 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 58629beb0c..e13e24a24f 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -74,6 +74,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index fb9f457b74..d9002390e9 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 1d6d88ff37..a3d0888615 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index f629080be2..40a9211dde 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -52,6 +52,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 38b17048c4..dea751e245 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -71,6 +71,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index eb97c18fdd..679b169f01 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -69,6 +69,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 45b05adbb4..328912e111 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 7bc1963b2f..cd2ce844ce 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index c1adc6e23f..2dd9a81849 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -47,6 +47,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 150179d633..c86843b39b 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -48,6 +48,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 016771a8f6..79b8bdc63f 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -48,6 +48,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index a8288e9fb6..18336c77b0 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_OF_CONTROL=y # CONFIG_SPL_BLK is not set CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 695505a975..efb0432b3f 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -65,6 +65,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 19e7751e78..2bf7550eba 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -65,6 +65,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index ef1a591ec0..ce5ff57999 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 8dd6ce41d6..9e73c42c45 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 3e54803107..bb8891fedc 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -73,6 +73,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 97fe2ce8bd..f0a7bc8de2 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -53,6 +53,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index dd0a726502..b97c5e9ac9 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index be40f49f6e..87e68f1ce3 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -72,6 +72,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 5820444404..e1f994d176 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -71,6 +71,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 6a89794885..e5cdb183d5 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -61,6 +61,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 94daa1f10b..130397fc07 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 19a54d1ea2..12af76d3b7 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -60,6 +60,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ef82842b64..1ea5f9a808 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 551807e879..8c5adb01e1 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_ADDR=0x60500000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y # CONFIG_DDR_SPD is not set CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 30daa5c6d0..585e0dd308 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -42,6 +42,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y # CONFIG_DDR_SPD is not set CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index bc326114cd..9a9d79b109 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -54,6 +54,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 52855d12e5..51ddd7f28a 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -55,6 +55,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index ab780c1622..f2b16ddd71 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -73,6 +73,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 8111ce6432..cadd016160 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -55,6 +55,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index b5b501c9a9..ca3c404726 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -74,6 +74,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 01451930e6..616558acdb 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -73,6 +73,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 11de0d40af..8295682d99 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -62,6 +62,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index a319bf39fc..926df893c1 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -63,6 +63,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 506b32c248..691c72862a 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -49,6 +49,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 87ab8ac421..b1a59b8357 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -68,6 +68,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 033ccc24e6..2e3ed3c3e2 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -62,6 +62,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_MPC8XXX_GPIO=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 2a3f6cb328..f57dcba826 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -47,6 +47,7 @@ CONFIG_DM=y CONFIG_SATA=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y 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imported from linux kernel. c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4 Signed-off-by: Gaurav Jain Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2041si-post.dtsi | 1 + arch/powerpc/dts/p3041si-post.dtsi | 1 + arch/powerpc/dts/p4080si-post.dtsi | 1 + arch/powerpc/dts/p5040si-post.dtsi | 1 + arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++++++++++++++++++++++ arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++++++++++++++++++++++++ arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92 ++++++++++++++++++++++++++++ arch/powerpc/dts/t1023si-post.dtsi | 1 + arch/powerpc/dts/t1042si-post.dtsi | 1 + arch/powerpc/dts/t2080si-post.dtsi | 1 + arch/powerpc/dts/t4240si-post.dtsi | 1 + 11 files changed, 257 insertions(+) create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi index 01ab395950..8819199646 100644 --- a/arch/powerpc/dts/p2041si-post.dtsi +++ b/arch/powerpc/dts/p2041si-post.dtsi @@ -11,6 +11,7 @@ /include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-sec4.2-0.dtsi" /* include used FMan blocks */ /include/ "qoriq-fman-0.dtsi" diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi index 21f322f06f..a3e8088d25 100644 --- a/arch/powerpc/dts/p3041si-post.dtsi +++ b/arch/powerpc/dts/p3041si-post.dtsi @@ -11,6 +11,7 @@ /include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-sec4.2-0.dtsi" /* include used FMan blocks */ /include/ "qoriq-fman-0.dtsi" diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi index 7c3f2fb92e..56b79b14f4 100644 --- a/arch/powerpc/dts/p4080si-post.dtsi +++ b/arch/powerpc/dts/p4080si-post.dtsi @@ -11,6 +11,7 @@ /include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-sec4.0-0.dtsi" /* include used FMan blocks */ /include/ "qoriq-fman-0.dtsi" diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi index 1efad2d017..fae3ed31a5 100644 --- a/arch/powerpc/dts/p5040si-post.dtsi +++ b/arch/powerpc/dts/p5040si-post.dtsi @@ -11,6 +11,7 @@ /include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-sec5.2-0.dtsi" /* include used FMan blocks */ /include/ "qoriq-fman-0.dtsi" diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi new file mode 100644 index 0000000000..ff348d70f1 --- /dev/null +++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v4.0"; + fsl,sec-era = <1>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi new file mode 100644 index 0000000000..57a0bc5c56 --- /dev/null +++ b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; + fsl,sec-era = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.2-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.2-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.2-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.2-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v4.2-rtic", + "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v4.2-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v4.2-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v4.2-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v4.2-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-sec5.2-0.dtsi b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi new file mode 100644 index 0000000000..e5f87effd3 --- /dev/null +++ b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + */ + +crypto: crypto@300000 { + compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <5>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupts = <92 2 0 0>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <88 2 0 0>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <89 2 0 0>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <90 2 0 0>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v5.2-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = <91 2 0 0>; + }; + + rtic@6000 { + compatible = "fsl,sec-v5.2-rtic", + "fsl,sec-v5.0-rtic", + "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v5.2-rtic-memory", + "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v5.2-rtic-memory", + "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v5.2-rtic-memory", + "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v5.2-rtic-memory", + "fsl,sec-v5.0-rtic-memory", + "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; +}; + +sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; + reg = <0x314000 0x1000>; + interrupts = <93 2 0 0>; +}; diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi index 7284eb9791..6f666a1554 100644 --- a/arch/powerpc/dts/t1023si-post.dtsi +++ b/arch/powerpc/dts/t1023si-post.dtsi @@ -14,6 +14,7 @@ /include/ "qoriq-gpio-1.dtsi" /include/ "qoriq-gpio-2.dtsi" /include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-sec5.0-0.dtsi" /* include used FMan blocks */ /include/ "qoriq-fman3l-0.dtsi" diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi index 5c60944e60..eebbbaf0e1 100644 --- a/arch/powerpc/dts/t1042si-post.dtsi +++ b/arch/powerpc/dts/t1042si-post.dtsi @@ -12,6 +12,7 @@ /include/ "qoriq-gpio-1.dtsi" /include/ "qoriq-gpio-2.dtsi" /include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-sec5.0-0.dtsi" /include/ "qoriq-fman3l-0.dtsi" /include/ "qoriq-fman3-0-1g-0.dtsi" diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi index d8ef579cb7..c06526b3db 100644 --- a/arch/powerpc/dts/t2080si-post.dtsi +++ b/arch/powerpc/dts/t2080si-post.dtsi @@ -13,6 +13,7 @@ /include/ "qoriq-gpio-1.dtsi" /include/ "qoriq-gpio-2.dtsi" /include/ "qoriq-gpio-3.dtsi" +/include/ "qoriq-sec5.2-0.dtsi" /include/ "qoriq-fman3-0.dtsi" /include/ "qoriq-fman3-0-10g-0-best-effort.dtsi" diff --git a/arch/powerpc/dts/t4240si-post.dtsi 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MX U-Boot Team" , Shengzhou Liu , Mingkai Hu , Rajesh Bhagat , Meenakshi Aggarwal , Wasim Khan , Alison Wang , Pramod Kumar , Tang Yuantian , Adrian Alonso , Vladimir Oltean , ZHIZHIKIN Andrey , Michael Trimarchi , Gaurav Jain Subject: [PATCH v11 13/14] PPC: Enable Job ring driver model. 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Signed-off-by: Gaurav Jain Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++++++++++++++++-- arch/powerpc/include/asm/u-boot-ppc.h | 17 +++++++++++++++++ arch/powerpc/include/asm/u-boot.h | 1 + configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/P3041DS_NAND_defconfig | 1 + configs/P3041DS_SDCARD_defconfig | 1 + configs/P3041DS_SPIFLASH_defconfig | 1 + configs/P3041DS_defconfig | 1 + configs/P4080DS_SDCARD_defconfig | 1 + configs/P4080DS_SPIFLASH_defconfig | 1 + configs/P4080DS_defconfig | 1 + configs/P5040DS_NAND_defconfig | 1 + configs/P5040DS_SDCARD_defconfig | 1 + configs/P5040DS_SPIFLASH_defconfig | 1 + configs/P5040DS_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + 41 files changed, 73 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e920e01b25..c64f0ac7aa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -56,6 +56,7 @@ #ifdef CONFIG_U_QE #include #endif +#include #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK /* @@ -974,8 +975,6 @@ int cpu_init_r(void) #endif #ifdef CONFIG_FSL_CAAM - sec_init(); - #if defined(CONFIG_ARCH_C29X) if ((SVR_SOC_VER(svr) == SVR_C292) || (SVR_SOC_VER(svr) == SVR_C293)) @@ -1014,6 +1013,22 @@ int cpu_init_r(void) return 0; } +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_FSL_CAAM)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize %s: %d\n", dev->name, ret); + } + + return 0; +} +#endif + void arch_preboot_os(void) { u32 msr; diff --git a/arch/powerpc/include/asm/u-boot-ppc.h b/arch/powerpc/include/asm/u-boot-ppc.h new file mode 100644 index 0000000000..372ca3e037 --- /dev/null +++ b/arch/powerpc/include/asm/u-boot-ppc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2021 NXP + * + * Gaurav Jain + */ + +#ifndef _U_BOOT_PPC_H_ +#define _U_BOOT_PPC_H_ + +#ifndef __ASSEMBLY__ + +int arch_misc_init(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _U_BOOT_PPC_H_ */ diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 19b3c0db5f..36af8e5403 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -21,5 +21,6 @@ /* Use the generic board which requires a unified bd_info */ #include #include +#include #endif /* __U_BOOT_H__ */ diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 01d61928a3..1e5cf7d874 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFFA00C21 CONFIG_SYS_OR0_PRELIM=0xFFFC0796 diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index dc56c791d1..d8ebd3f989 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xE8001001 CONFIG_SYS_OR0_PRELIM=0xF8000F85 diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 78a24503a4..b6b0d516c5 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xE8001001 CONFIG_SYS_OR0_PRELIM=0xF8000F85 diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index f6bf4daf23..64c44a125f 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xE8001001 CONFIG_SYS_OR0_PRELIM=0xF8000F85 diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index ec5850017d..790c8f7d7b 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 58a3eaea72..1f3a2b322a 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index c48976b3d0..a3f6d2dadb 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index fcc73610af..435ea1924f 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 25f7861791..def492978c 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index c32c394530..915eecbb9f 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index e3c41c316f..2e0171acf3 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 279976c04d..bf6ef1885c 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 34ebc51922..21d8a39b88 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index ea8b673304..9b765e5c3f 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index e9bf7ff014..53196434a8 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -37,6 +37,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 20ded48a35..a5ddcd8cda 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -63,6 +63,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 8a82082968..ab59d4e173 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 87d40831d9..e5b71813db 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -64,6 +64,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index de34ba7a68..f0c07249d5 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -47,6 +47,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index a755d9c702..fb7f14cc89 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -54,6 +54,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index efb46b3bf2..65e25d0645 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -53,6 +53,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 1568c797bf..ecaec29612 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -55,6 +55,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3abd079dc6..27b44c4e9f 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 1b6ef8aaa1..4e888c9510 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -58,6 +58,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 8ab1c5d680..7900670c98 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -57,6 +57,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 8fd024848a..882e159989 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index f9dbc84f92..5b574946de 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_ADDR=0xFFE20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 424b3f2cdb..1ecf12bc91 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -42,6 +42,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DYNAMIC_DDR_CLK_FREQ=y CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 1c55d30b5e..de6969fc14 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index ea9c479825..fbd72313bb 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -61,6 +61,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 5e08b82406..ae6b444351 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -63,6 +63,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 1c1fea60b5..e197995e85 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -46,6 +46,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index ae924b1817..bec2d1529a 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -63,6 +63,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index fef08931d0..3bc08f7b9c 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 0b7e71567d..0dc2b2f77f 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -64,6 +64,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index c78b21dd24..7c196e6214 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -47,6 +47,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133330000 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index ea6a528495..ec66247ec2 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -53,6 +53,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y CONFIG_DDR_CLK_FREQ=133333333 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index e17e8b129f..042039713a 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -38,6 +38,7 @@ CONFIG_ENV_ADDR=0xEFF20000 CONFIG_DM=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y +CONFIG_ARCH_MISC_INIT=y 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Signed-off-by: Gaurav Jain --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 96582fc677..404a8e9653 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1376,3 +1376,9 @@ T: git https://source.denx.de/u-boot/u-boot.git F: configs/tools-only_defconfig F: * F: */ + +CAAM +M: Gaurav Jain +S: Maintained +F: drivers/crypto/fsl/ +F: include/fsl_sec.h