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[94.253.144.57]) by smtp.googlemail.com with ESMTPSA id p23-20020a170906605700b006ccebe7f75dsm6797608ejj.123.2022.03.21.04.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Mar 2022 04:39:59 -0700 (PDT) From: Robert Marko To: openwrt-devel@lists.openwrt.org Cc: Robert Marko Subject: [PATCH] uboot-mvebu: backport patch to fix eMMC Date: Mon, 21 Mar 2022 12:39:54 +0100 Message-Id: <20220321113954.407355-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220321_044006_296169_B31FCDBE X-CRM114-Status: GOOD ( 21.59 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: v2022.01 has a regression that broke eMMC usage on most if not all Armada SoC-s, thus breaking boards like uDPU which use eMMC for storage. Fix it by backporting a recent upstream patch. Fixes: 782d4c8306c8 ("uboot-mvebu: update to version 2022.01") Signed-off-by: Robert Marko --- ...enon_sdhci-remove-wait_dat0-SDHCI-OP.patch | 64 +++++++++++++++++++ 1 file c [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:636 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: openwrt-devel@lists.openwrt.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: OpenWrt Development List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "openwrt-devel" Errors-To: openwrt-devel-bounces+incoming=patchwork.ozlabs.org@lists.openwrt.org v2022.01 has a regression that broke eMMC usage on most if not all Armada SoC-s, thus breaking boards like uDPU which use eMMC for storage. Fix it by backporting a recent upstream patch. Fixes: 782d4c8306c8 ("uboot-mvebu: update to version 2022.01") Signed-off-by: Robert Marko --- ...enon_sdhci-remove-wait_dat0-SDHCI-OP.patch | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch diff --git a/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch b/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch new file mode 100644 index 0000000000..3277638784 --- /dev/null +++ b/package/boot/uboot-mvebu/patches/013-mmc-xenon_sdhci-remove-wait_dat0-SDHCI-OP.patch @@ -0,0 +1,64 @@ +From 0f3466f52fbacce67e147b9234e6323edff26a6d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 11 Mar 2022 19:14:07 +0100 +Subject: [PATCH] mmc: xenon_sdhci: remove wait_dat0 SDHCI OP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Generic SDHCI driver received support for checking the busy status by +polling the DAT[0] level instead of waiting for the worst MMC switch time. + +Unfortunately, it appears that this does not work for Xenon controllers +despite being a part of the standard SDHCI registers and the Armada 3720 +datasheet itself telling that BIT(20) is useful for detecting the DAT[0] +busy signal. + +I have tried increasing the timeout value, but I have newer managed to +catch DAT_LEVEL bits change from 0 at all. + +This issue appears to hit most if not all SoC-s supported by Xenon driver, +at least A3720, A8040 and CN9130 have non working eMMC currently. + +So, until a better solution is found drop the wait_dat0 OP for Xenon. +I was able to only test it on A3720, but it should work for others as well. + +Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver") +Signed-off-by: Robert Marko +Reviewed-by: Marek Behún +Reviewed-by: Jaehoon Chung +Reviewed-by: Stefan Roese +--- + drivers/mmc/xenon_sdhci.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/xenon_sdhci.c ++++ b/drivers/mmc/xenon_sdhci.c +@@ -439,6 +439,8 @@ static const struct sdhci_ops xenon_sdhc + .set_ios_post = xenon_sdhci_set_ios_post + }; + ++static struct dm_mmc_ops xenon_mmc_ops; ++ + static int xenon_sdhci_probe(struct udevice *dev) + { + struct xenon_sdhci_plat *plat = dev_get_plat(dev); +@@ -452,6 +454,9 @@ static int xenon_sdhci_probe(struct udev + host->mmc->dev = dev; + upriv->mmc = host->mmc; + ++ xenon_mmc_ops = sdhci_ops; ++ xenon_mmc_ops.wait_dat0 = NULL; ++ + /* Set quirks */ + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; + +@@ -568,7 +573,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = { + .id = UCLASS_MMC, + .of_match = xenon_sdhci_ids, + .of_to_plat = xenon_sdhci_of_to_plat, +- .ops = &sdhci_ops, ++ .ops = &xenon_mmc_ops, + .bind = xenon_sdhci_bind, + .probe = xenon_sdhci_probe, + .remove = xenon_sdhci_remove,