From patchwork Thu Feb 15 17:40:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 874014 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=micronovasrl.com header.i=@micronovasrl.com header.b="aj6MPtqp"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zj3Vk6N0Pz9t3v for ; Fri, 16 Feb 2018 04:41:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6FCFCC21EC9; Thu, 15 Feb 2018 17:41:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C51EC21EA8; Thu, 15 Feb 2018 17:41:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B4A66C21EA8; Thu, 15 Feb 2018 17:41:42 +0000 (UTC) Received: from mail.micronovasrl.com (mail.micronovasrl.com [212.103.203.10]) by lists.denx.de (Postfix) with ESMTP id 4AF12C21D74 for ; Thu, 15 Feb 2018 17:41:42 +0000 (UTC) Received: from mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) by mail.micronovasrl.com (Postfix) with ESMTP id D450FB00D5E for ; Thu, 15 Feb 2018 18:41:41 +0100 (CET) Authentication-Results: mail.micronovasrl.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=micronovasrl.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=micronovasrl.com; h=x-mailer:message-id:date:date:subject:subject:to:from:from; s=dkim; t=1518716500; x=1519580501; bh=irkFo3eKnZjlPaLZa8Xg12cA lGWfGGEkBqaz+5Pq9Nc=; b=aj6MPtqpRJPUju+vVgICMiv4XEwDLffF7PImVkTm V9/QCl4pz51wHJWF8YpkN78uP65lz2GI7D2Ixws8kwA/HizIIGLmHG4kmvfMZQA9 v0L4bnWGHkW3gSx5+iErxCBT1hvm5xsE1YJCTlmbseoL+Uia9eZfzNGq30sU4sQZ DNw= X-Virus-Scanned: Debian amavisd-new at mail.micronovasrl.com Received: from mail.micronovasrl.com ([127.0.0.1]) by mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 37O695TvY-OC for ; Thu, 15 Feb 2018 18:41:40 +0100 (CET) Received: from localhost.localdomain (62-11-51-166.dialup.tiscali.it [62.11.51.166]) by mail.micronovasrl.com (Postfix) with ESMTPSA id 48A9DB0011E; Thu, 15 Feb 2018 18:41:40 +0100 (CET) From: Giulio Benetti To: Anatolij Gustschin Date: Thu, 15 Feb 2018 18:40:53 +0100 Message-Id: <1518716453-120273-1-git-send-email-giulio.benetti@micronovasrl.com> X-Mailer: git-send-email 2.7.4 Cc: u-boot@lists.denx.de, Maxime Ripard , Giulio Benetti Subject: [U-Boot] [PATCH] sunxi: video: lcdc: fix HSYNC and VSYNC polarity X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0. Invert their settings of IO_POL register. Signed-off-by: Giulio Benetti --- drivers/video/sunxi/lcdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 4cb86fb..007057c 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -132,9 +132,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, } val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); - if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= SUNXI_LCDC_TCON_HSYNC_MASK; - if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= SUNXI_LCDC_TCON_VSYNC_MASK; #ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH