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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:33 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang , Lukasz Majewski , Sean Anderson , Elaine Zhang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 01/11] clk: rockchip: rk3568: fix reset handler Date: Mon, 21 Feb 2022 20:31:20 -0500 Message-Id: <20220222013131.3114990-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. Add the missing dev_set_priv to the rk3568 clk driver. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis Reviewed-by: Kever Yang Reviewed-by: Jagan Teki Tested-by: Jagan Teki # radxa-cm3 --- drivers/clk/rockchip/clk_rk3568.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index d5e45e7602c7..c83ae22dc302 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev) glb_srst_fst); priv->glb_srst_snd_value = offsetof(struct rk3568_cru, glb_srsr_snd); + dev_set_priv(sys_child, priv); } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) From patchwork Tue Feb 22 01:31:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595797 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FPYkvE1e; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K2hVr5B5mz9sGH for ; Tue, 22 Feb 2022 12:32:36 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4E09A83C6E; Tue, 22 Feb 2022 02:32:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FPYkvE1e"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4E00083C93; Tue, 22 Feb 2022 02:31:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F01FB83C6E for ; Tue, 22 Feb 2022 02:31:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pgwipeout@gmail.com Received: by mail-qk1-x72d.google.com with SMTP id z66so13594450qke.10 for ; Mon, 21 Feb 2022 17:31:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ehHYxJmFteREp43JkGoELWgScEXPvJyd4WUXqcF0gNA=; b=FPYkvE1efeGKGQ6BCyq6bVbYUCoZkhebk5V2UzcHtjeaxKOsQ4cclmlNOlo69sdf7y AmCkw/qK7xaj2DrMTKVniPnXMkJLOXBgQ+OOFtkSb9I/mIsvdytyDVHhzNJkZPfsIfTV S65mSiB66Ojg7q+cUaWB/HhId6gJtCejs8nTj27YaoWBcdawpH75F2CNJmdWdEkG9Rlb nIwi3WbLV8+eMkYV0F8ElEuxzhCKc5PlMlyWCCS9C7qX6njjxLU1nEhlVNftKdTuqQGO 9OMfAz5e5UGWg7yj7ZsJHCN5g/QOhbHs8kD4Cv98N/ihLh3ytzp4u6YmqCufer8/ImP5 wzMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ehHYxJmFteREp43JkGoELWgScEXPvJyd4WUXqcF0gNA=; b=W7vgUeJA+htVT7bcrTLdMFPBZKHk1VjWe1mI8OAVnEJYhgbTxULYBZrbA9khTf5Sac nrAqo0TMJWt0wYkSZKhQLO5I92sHLHJFtv3eU8apm5ZYLebOhcIjDcZmsx4ipT3IjtDQ uW7wUmDM26Rpy5LG3k//2TM3Be11DvsCaNwyIgY96ESEzNPuZPaR8TM2OrBcDoAPwm9Y mK8o8h5WnhtCQ9hZIdExUZxEzzSM6fY1RHJ0bEewZ0TCUSQwiX+K4iW01oAWfHHaQHfT xm3d28F+/vitwUTQGYQVOMIY86ynxCYrJ7s1+dmP45hBBsBzPTdZ6LaxzN3r9lly1njX veBA== X-Gm-Message-State: AOAM532tUOmspGlX1LxjlB14aIw3ua52EwgLDruQVNmDvuJbfKjQG19W cSLOQgTsh7W6MZpVXzudNeg= X-Google-Smtp-Source: ABdhPJyatP6ooF6fTiPb0Rt1sRHbXbUo1KzyahnlQHdnGeK3LxbGHGb3gER/Y0iGE6cfbG9CVF6nbQ== X-Received: by 2002:a05:620a:1902:b0:5f1:8f5d:b0f2 with SMTP id bj2-20020a05620a190200b005f18f5db0f2mr14090413qkb.60.1645493494768; Mon, 21 Feb 2022 17:31:34 -0800 (PST) Received: from master-x64.sparksnet (c-98-233-193-225.hsd1.dc.comcast.net. [98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:34 -0800 (PST) From: Peter Geis To: Peng Fan , Jaehoon Chung Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 02/11] mmc: sdhci: allow disabling sdma in spl Date: Mon, 21 Feb 2022 20:31:21 -0500 Message-Id: <20220222013131.3114990-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Rockchip emmc devices have a similar issue to Rockchip dwmmc devices, where performing dma to sram causes errors with suspend/resume. Allow us to toggle sdma in spl for sdhci similar to adma support, so we can ensure dma is not used when loading the sram code. Signed-off-by: Peter Geis Reviewed-by: Jaehoon Chung Reviewed-by: Kever Yang --- drivers/mmc/Kconfig | 7 +++++++ drivers/mmc/sdhci.c | 6 +++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f04cc44e1973..1e4342285ce7 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -468,6 +468,13 @@ config MMC_SDHCI_SDMA This enables support for the SDMA (Single Operation DMA) defined in the SD Host Controller Standard Specification Version 1.00 . +config SPL_MMC_SDHCI_SDMA + bool "Support SDHCI SDMA in SPL" + depends on MMC_SDHCI + help + This enables support for the SDMA (Single Operation DMA) defined + in the SD Host Controller Standard Specification Version 1.00 in SPL. + config MMC_SDHCI_ADMA bool "Support SDHCI ADMA2" depends on MMC_SDHCI diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 766e4a6b0c5e..6285e53d12a2 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -70,7 +70,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) } } -#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) +#if (CONFIG_IS_ENABLED(MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, int *is_aligned, int trans_bytes) { @@ -177,7 +177,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) } } while (!(stat & SDHCI_INT_DATA_END)); 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:35 -0800 (PST) From: Peter Geis To: Jagan Teki Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 03/11] spi: rockchip-sfc: fix building rockchip-sfc Date: Mon, 21 Feb 2022 20:31:22 -0500 Message-Id: <20220222013131.3114990-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The rockchip-sfc driver is missing an include to build correctly. Signed-off-by: Peter Geis --- drivers/spi/rockchip_sfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index e098addddcac..851a6482985b 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include From patchwork Tue Feb 22 01:31:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595799 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=RmS0OgqN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K2hWK0bFcz9sGK for ; Tue, 22 Feb 2022 12:33:00 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B2FEF83C9C; Tue, 22 Feb 2022 02:32:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RmS0OgqN"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id ABF8583C3C; Tue, 22 Feb 2022 02:31:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ACD4D83C7E for ; Tue, 22 Feb 2022 02:31:37 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pgwipeout@gmail.com Received: by mail-qv1-xf2a.google.com with SMTP id f19so36944489qvb.6 for ; Mon, 21 Feb 2022 17:31:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9uXOoYNLD6irtNbGgSuxDeZ/T20yCJSAtixcUZ5gEd4=; b=RmS0OgqNz5VOm4UMvay/WwVjWyQRKD4ZCyx8CE9IcrBUwJEMtfl1x633AU6w2/H0St hFkvQ14eqD8djB98z1HzFruvT1XrTt1w4I8xGPiOyb/uOgo29LHoxKckG2TLuQReBont o01m3rzHiggc54gfdgeQGBDeGHkiUXidz5XVP+eMY4L5OPvw+JPfmCyaIA3cM22nVO/M znnLti+Dy17xxQmm0lqYEt0e9WltUN5OO83Sq9WfeZyWfMXb3uLzvhIgF+2TNwPjJ/gK DEGuIJU60mCbLahgfpi4zjLVaJMK4cx8ZW6Sh/JSmJ2kmi+6tR1cO4So/lWtRxUynqhb ENVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9uXOoYNLD6irtNbGgSuxDeZ/T20yCJSAtixcUZ5gEd4=; b=prMJhg+VcqZ70mGkdMdQQ1+hLF29scokGCGTCnMeElgZrzWBKiPAzf6OoS9BkzUrye pZUxdwPgqzk2g32BybTIqvKxfSl7B9xOLPxWg2i9LPJgUh4XgomlL9dmN5nuMiaLjowX SAjtwEa6b4VhPYb2CcU5m3CZDLBvV3qYJUHtTTW805xe3av5n3Itc87MbHxcePQirGf9 E/R9BZiwQJTH9poDN4Z67DXT7Atx/KowYqo0pWJBt9oqtIYLwlOhp7J2KNvwPEsl1xu+ FqnXUcoMOx0V6lp52O6EXZK7ItPYatvGnbdzkBqRw3AmujVysPFbhaHlc8Nf2NIjCRFM gopw== X-Gm-Message-State: AOAM530lIzkGzsRXvGzKJpKHMsJ+i3/UDG2HMiy6JJRGQyMCN8ykTquw 0zS7XswMXNHkquM2D4a0Q9inBGZi0Tc= X-Google-Smtp-Source: ABdhPJwa+lNPcalIOm+6oAmGfJxujmAmXaeVPPpe6aFOSL9e8ebrIXYqo4Qqz76ya3rbnU/P7qmeSg== X-Received: by 2002:a0c:fc09:0:b0:42c:42f:6ba2 with SMTP id z9-20020a0cfc09000000b0042c042f6ba2mr17653222qvo.35.1645493496454; Mon, 21 Feb 2022 17:31:36 -0800 (PST) Received: from master-x64.sparksnet (c-98-233-193-225.hsd1.dc.comcast.net. [98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:36 -0800 (PST) From: Peter Geis To: Jagan Teki Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 04/11] spi: rockchip-sfc: sanity check minimum freq Date: Mon, 21 Feb 2022 20:31:23 -0500 Message-Id: <20220222013131.3114990-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The rockchip-sfc driver sanity checks the maximum frequency, but not the minimum frequency. This causes the probe to fail when a frequency isn't defined, such as with `sf probe 0`. Clamp the minimum frequency to the rockchip default clock rate. Signed-off-by: Peter Geis --- drivers/spi/rockchip_sfc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c index 851a6482985b..d0d2dc70a417 100644 --- a/drivers/spi/rockchip_sfc.c +++ b/drivers/spi/rockchip_sfc.c @@ -164,6 +164,8 @@ /* DMA is only enabled for large data transmission */ #define SFC_DMA_TRANS_THRETHOLD (0x40) +#define SFC_MIN_SPEED (24 * 1000 * 1000) + /* Maximum clock values from datasheet suggest keeping clock value under * 150MHz. No minimum or average value is suggested. */ @@ -596,6 +598,9 @@ static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) if (speed > sfc->max_freq) speed = sfc->max_freq; + if (speed < SFC_MIN_SPEED) + speed = SFC_MIN_SPEED; + if (speed == sfc->speed) return 0; From patchwork Tue Feb 22 01:31:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595798 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=eeAxhWe7; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K2hW66wzWz9sGK for ; Tue, 22 Feb 2022 12:32:50 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A0F2C83C75; Tue, 22 Feb 2022 02:32:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="eeAxhWe7"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 65AF383C63; Tue, 22 Feb 2022 02:31:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf32.google.com (mail-qv1-xf32.google.com [IPv6:2607:f8b0:4864:20::f32]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 77C6C83C87 for ; Tue, 22 Feb 2022 02:31:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pgwipeout@gmail.com Received: by mail-qv1-xf32.google.com with SMTP id 8so827733qvf.2 for ; Mon, 21 Feb 2022 17:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b11G8hdFjBUAWjCZHzyLyd0RmAi7OhI4PCxR2fqvk6s=; b=eeAxhWe7bXd8izwEzDxI7JyL1TDkmrI+jzhSu1o0WmWU52KBDhNaTmYFwGlQOcYzf5 eJ1K5cWpGPB1rBjd8uxAkg6gQMWIyuvHPdW7+FgDjJxvTnkT2VufoMcjLk7IyJJKqGEB DDl5BYVLbzbxf8KBU4jq6+bSQlgzd/6GGGLgsyBKVkmHab/VDflf3fEOYGa2oJ0m+A2G Ijod90CSt8V33ktN6BmgFPlkICMsWz8FNI+ShQMH3AkM83IgbN6NRdHmkZ9fYZP+pHBz fraQ8SJEFMTTeLC0ru1Oj5bjMs5Q/4KmNi27aEUjf3gw0VQZZ7qTGE2CkhGd8jRLNAop loHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b11G8hdFjBUAWjCZHzyLyd0RmAi7OhI4PCxR2fqvk6s=; b=aJLlJw9HK+JSzZnXu9IXAdACvR9I9Lz/Dn1hjRj0VmN0Of9hXeBUxKkDFksAx9z6Yb d3a+jbdoytK1TbDGR4g8j31FN/GHWc/nZmaIMlLK9ARAbFaflrBgKac+fgviDQt0rKvp dtLkeY9EA45Iu98xbU+yTZIOjmFBlBpzE+COAyV9Y1s7VWpMMeabGaPxRKSbiPeW/u17 xgV4bRjU7bpftOPuYZJYyABri8v76NXPVBMv6LHFbe5al6XJHeu246W8KS9w1rvX4wS+ DPWNIaxmK26DO0NmHdMsAhP3ZODALVk5ooJAiTVSbE8MC9Bb+gdc2/+3ekSzNMatr9A5 qEEQ== X-Gm-Message-State: AOAM532FMBCAFa8J6yqpOg6qGnXULxBYMgGoPRCAcssUBi5kDpYRPZ+0 Jk+7rF7ZJpC0xRmYX8NgY5m/lBigmy4= X-Google-Smtp-Source: ABdhPJwHs7V9h9wbBnpjzpvXnDhwgkeDjFKUDyk59TPbLzD7WStZfHV8tHHXcUiHthQybF2SQ+y0TA== X-Received: by 2002:a05:622a:1903:b0:2dd:a07e:659e with SMTP id w3-20020a05622a190300b002dda07e659emr16396098qtc.360.1645493497265; Mon, 21 Feb 2022 17:31:37 -0800 (PST) Received: from master-x64.sparksnet (c-98-233-193-225.hsd1.dc.comcast.net. [98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:37 -0800 (PST) From: Peter Geis To: Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 05/11] spl: support adc drivers in spl Date: Mon, 21 Feb 2022 20:31:24 -0500 Message-Id: <20220222013131.3114990-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean In order to handle the rockchip recovery handler in spl, we need the adc code to be available in spl. Add a toggle to allow adc drivers to function in spl. Signed-off-by: Peter Geis --- common/spl/Kconfig | 5 +++++ drivers/Makefile | 1 + 2 files changed, 6 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e0d0a6f77b51..df99042e2fd6 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY ensure this information is available to the next image invoked). +config SPL_ADC + bool "Support ADC drivers in SPL" + help + Enable ADC drivers in SPL. + config SPL_CACHE bool "Support CACHE drivers" help diff --git a/drivers/Makefile b/drivers/Makefile index 4e7cf284405a..ce091ca9a7a4 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_)ADC) += adc/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ From patchwork Tue Feb 22 01:31:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595802 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:38 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 06/11] rockchip: handle bootrom recovery mode in spl Date: Mon, 21 Feb 2022 20:31:25 -0500 Message-Id: <20220222013131.3114990-7-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Fixup the bootrom recovery mode code to function in spl, so we can handle recovery mode in case u-boot loading is broken. Signed-off-by: Peter Geis --- arch/arm/mach-rockchip/Makefile | 6 +++--- arch/arm/mach-rockchip/boot_mode.c | 4 +++- arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ 3 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee6a..53aff25ce8f6 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) - # Always include boot_mode.o, as we bypass it (i.e. turn it off) # inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". -obj-y += boot_mode.o +obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o obj-$(CONFIG_MISC_INIT_R) += misc.o endif diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index 1a1a887fc2cd..43cb369465a2 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void) ret = -ENODEV; uclass_foreach_dev(dev, uc) { if (!strncmp(dev->name, "saradc", 6)) { - ret = adc_channel_single_shot(dev->name, 1, &val); + ret = adc_channel_single_shot(dev->name, 0, &val); break; } } @@ -89,6 +89,7 @@ int setup_boot_mode(void) boot_mode = readl(reg); debug("%s: boot mode 0x%08x\n", __func__, boot_mode); +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) /* Clear boot mode */ writel(BOOT_NORMAL, reg); @@ -102,6 +103,7 @@ int setup_boot_mode(void) env_set("preboot", "setenv preboot; ums mmc 0"); break; } +#endif return 0; } diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 22eeb77d41fa..4e23feb9417f 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -104,3 +104,26 @@ int arch_cpu_init(void) #endif return 0; } + +#ifdef CONFIG_SPL_BUILD + +void __weak led_setup(void) +{ +} + +void spl_board_init(void) +{ + led_setup(); + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + setup_boot_mode(); +} +#endif From patchwork Tue Feb 22 01:31:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595801 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:38 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 07/11] rockchip: rk3568: add boot device detection Date: Mon, 21 Feb 2022 20:31:26 -0500 Message-Id: <20220222013131.3114990-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable rk3568 spl to detect which device it was booted from. Signed-off-by: Peter Geis Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 4e23feb9417f..5f239d89a7a9 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,7 @@ #define SGRF_SOC_CON4 0x10 #define EMMC_HPROT_SECURE_CTRL 0x03 #define SDMMC0_HPROT_SECURE_CTRL 0x01 + /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -43,6 +45,12 @@ enum { UART2_IO_SEL_M0 = 0, }; +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", + [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", +}; + static struct mm_region rk3568_mem_map[] = { { .virt = 0x0UL, From patchwork Tue Feb 22 01:31:27 2022 Content-Type: text/plain; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:39 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 08/11] rockchip: rk3568: enable automatic clock gating Date: Mon, 21 Feb 2022 20:31:27 -0500 Message-Id: <20220222013131.3114990-9-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable automatic clock gating on rk3568, which solves a 7c temperature difference on SoQuartz compared to downstream. Signed-off-by: Peter Geis Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 5f239d89a7a9..0e0a7f5b54f2 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -25,6 +25,15 @@ #define EMMC_HPROT_SECURE_CTRL 0x03 #define SDMMC0_HPROT_SECURE_CTRL 0x01 +#define PMU_BASE_ADDR 0xfdd90000 +#define PMU_NOC_AUTO_CON0 (0x70) +#define PMU_NOC_AUTO_CON1 (0x74) +#define EDP_PHY_GRF_BASE 0xfdcb0000 +#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) +#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) +#define CPU_GRF_BASE 0xfdc30000 +#define GRF_CORE_PVTPLL_CON0 (0x10) + /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -99,6 +108,20 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD + /* + * When perform idle operation, corresponding clock can + * be opened or gated automatically. + */ + writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); + writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); + + /* Disable eDP phy by default */ + writel(0x00070007, EDP_PHY_GRF_CON10); + writel(0x0ff10ff1, EDP_PHY_GRF_CON0); + + /* Set core pvtpll ring length */ + writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); + /* Set the emmc sdmmc0 to secure */ rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 | SDMMC0_HPROT_SECURE_CTRL << 4)); From patchwork Tue Feb 22 01:31:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 1595804 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=oOI+tfc2; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:40 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 09/11] rockchip: move dwc3 config to chip specific handler Date: Mon, 21 Feb 2022 20:31:28 -0500 Message-Id: <20220222013131.3114990-10-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The dwc3 code in the mach-rockchip board file is specific to the rk3399. Move it to the rk3399 chip specific code. Signed-off-by: Peter Geis Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/board.c | 24 --------------------- arch/arm/mach-rockchip/rk3399/rk3399.c | 29 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 5304eb055c6d..b19c15c26f2e 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -127,30 +127,6 @@ int board_usb_cleanup(int index, enum usb_init_type init) } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ -#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) -#include - -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_HIGH, - .base = 0xfe800000, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, - .dis_u2_susphy_quirk = 1, - .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, -}; - -int usb_gadget_handle_interrupts(int index) -{ - dwc3_uboot_handle_interrupt(0); - return 0; -} - -int board_usb_init(int index, enum usb_init_type init) -{ - return dwc3_uboot_init(&dwc3_device_data); -} -#endif /* CONFIG_USB_DWC3_GADGET */ - #endif /* CONFIG_USB_GADGET */ #if CONFIG_IS_ENABLED(FASTBOOT) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index d40969c88898..c7e38997e521 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -284,3 +284,32 @@ void spl_board_init(void) #endif } #endif + +#if defined(CONFIG_USB_GADGET) +#include + +#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) +#include + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0xfe800000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, + .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); +} +#endif /* CONFIG_USB_DWC3_GADGET */ + +#endif /* CONFIG_USB_GADGET */ From patchwork Tue Feb 22 01:31:29 2022 Content-Type: text/plain; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:41 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 10/11] rockchip: rk3568: add dwc3 otg support Date: Mon, 21 Feb 2022 20:31:29 -0500 Message-Id: <20220222013131.3114990-11-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add the required platform data to the rk3568 chip config, in order to support dwc3 otg on this chip. Signed-off-by: Peter Geis Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 0e0a7f5b54f2..ef6bc67a88b0 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -158,3 +158,32 @@ void spl_board_init(void) setup_boot_mode(); } #endif + +#if defined(CONFIG_USB_GADGET) +#include + +#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET) +#include + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = 0xfcc00000, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .dis_u2_susphy_quirk = 1, + .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(0); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + return dwc3_uboot_init(&dwc3_device_data); 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id q12sm31597841qtx.51.2022.02.21.17.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Feb 2022 17:31:42 -0800 (PST) From: Peter Geis To: Simon Glass , Philipp Tomsich , Kever Yang Cc: Peter Geis , u-boot@lists.denx.de Subject: [PATCH v1 11/11] [RFC] rockchip: rk356x: attempt to fix ram detection Date: Mon, 21 Feb 2022 20:31:30 -0500 Message-Id: <20220222013131.3114990-12-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com> References: <20220222013131.3114990-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This patch attempts to fix ram detection on rk3568. Prior to this, the rk3568 incorrectly detected 8gb ram as 2gb. On top of this, the board panics when u-boot accesses ram above 4gb. Fix this by correcting ram detection in hopefully a backwards compatable way, and extend board_f.c to enforce an upper limit on the ram u-boot uses. This allows us to limit the ram u-boot accesses, while passing the correctly detected size to follow on software (eg linux). This has been tested on rk3566 2gb, 4gb, and 8gb configurations, as well as rk3399 4gb configurations. I do not have other configurations available, and I do not have the insights into rockchip ram handling to tell if this is the correct way to go about this. Signed-off-by: Peter Geis --- arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++++ arch/arm/mach-rockchip/sdram.c | 19 +++++++++++------ common/board_f.c | 7 +++++++ include/configs/rk3568_common.h | 5 +++++ 5 files changed, 55 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 92f35309e4a6..58393cc623f8 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -264,6 +264,7 @@ config ROCKCHIP_RK3568 select SYSCON select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + imply OF_SYSTEM_SETUP help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index ef6bc67a88b0..8d2a59bc649d 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -187,3 +188,31 @@ int board_usb_init(int index, enum usb_init_type init) #endif /* CONFIG_USB_DWC3_GADGET */ #endif /* CONFIG_USB_GADGET */ + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret; + int areas = 1; + u64 start[2], size[2]; + + /* Reserve the io address space. */ + if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) { + start[0] = gd->bd->bi_dram[0].start; + size[0] = SDRAM_LOWER_ADDR_MAX - gd->bd->bi_dram[0].start; + + /* Add the upper 4GB address space */ + start[1] = SDRAM_UPPER_ADDR_MIN; + size[1] = gd->ram_top - SDRAM_UPPER_ADDR_MIN; + areas = 2; + + ret = fdt_set_usable_memory(blob, start, size, areas); + if (ret) { + printf("Cannot set usable memory\n"); + return ret; + } + } + + return 0; +}; +#endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 705ec7ba6450..52974e6dc333 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -3,6 +3,8 @@ * Copyright (C) 2017 Rockchip Electronics Co., Ltd. */ +#define DEBUG + #include #include #include @@ -98,8 +100,7 @@ size_t rockchip_sdram_size(phys_addr_t reg) SYS_REG_COL_MASK); cs1_col = cs0_col; bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & - SYS_REG_VERSION_MASK) == 0x2) { + if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) >= 0x2) { cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & SYS_REG_CS1_COL_MASK); if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & @@ -136,7 +137,7 @@ size_t rockchip_sdram_size(phys_addr_t reg) SYS_REG_BW_MASK)); row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; - if (dram_type == DDR4) { + if ((dram_type == DDR4) && (sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) != 0x3){ dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK; bg = (dbw == 2) ? 2 : 1; @@ -176,9 +177,11 @@ size_t rockchip_sdram_size(phys_addr_t reg) * 2. update board_get_usable_ram_top() and dram_init_banksize() * to reserve memory for peripheral space after previous update. */ + +#ifndef __aarch64__ if (size_mb > (SDRAM_MAX_SIZE >> 20)) size_mb = (SDRAM_MAX_SIZE >> 20); - +#endif return (size_t)size_mb << 20; } @@ -208,6 +211,10 @@ int dram_init(void) ulong board_get_usable_ram_top(ulong total_size) { unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; - - return (gd->ram_top > top) ? top : gd->ram_top; +#ifdef SDRAM_UPPER_ADDR_MIN + if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) + return gd->ram_top; + else +#endif + return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/common/board_f.c b/common/board_f.c index a68760092ac1..933ba7aedac0 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -344,7 +344,14 @@ static int setup_dest_addr(void) #endif gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->mon_len); +#ifdef SDRAM_LOWER_ADDR_MAX + if (gd->ram_top > SDRAM_LOWER_ADDR_MAX) + gd->relocaddr = SDRAM_LOWER_ADDR_MAX; + else + gd->relocaddr = gd->ram_top; +#else gd->relocaddr = gd->ram_top; +#endif debug("Ram top: %08lX\n", (ulong)gd->ram_top); #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) /* diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 25d7c5cc8fff..8dd1b033017b 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -27,6 +27,11 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 +#ifdef CONFIG_OF_SYSTEM_SETUP +#define SDRAM_LOWER_ADDR_MAX 0xf0000000 +#define SDRAM_UPPER_ADDR_MIN 0x100000000 +#endif + #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00c00000\0" \