From patchwork Thu Feb 15 07:59:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Messerklinger X-Patchwork-Id: 873697 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zhpbg0k8Lz9t1t for ; Thu, 15 Feb 2018 19:00:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6E81FC220D9; Thu, 15 Feb 2018 08:00:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72C0DC22094; Thu, 15 Feb 2018 08:00:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D2110C22055; Thu, 15 Feb 2018 08:00:06 +0000 (UTC) Received: from mail2.br-automation.com (mail.br-automation.com [213.33.116.60]) by lists.denx.de (Postfix) with ESMTPS id 4AB44C21C3F for ; Thu, 15 Feb 2018 08:00:06 +0000 (UTC) X-AuditID: c0a80110-925ff70000000e86-9e-5a853e05d848 Received: from brsmtp01.br-automation.com (Unknown_Domain [192.168.1.60]) by mail2.br-automation.com () with SMTP id 47.D2.03718.50E358A5; Thu, 15 Feb 2018 09:00:05 +0100 (CET) MIME-Version: 1.0 From: Bernhard Messerklinger To: u-boot@lists.denx.de Date: Thu, 15 Feb 2018 08:59:53 +0100 Message-Id: <20180215075953.5015-1-bernhard.messerklinger@br-automation.com> X-Mailer: git-send-email 2.16.1 X-MIMETrack: Itemize by SMTP Server on BRSMTPINTERN2/InternSMTP(Release 9.0.1FP5|November 22, 2015) at 15/02/2018 09:00:01, Serialize by Router on BRSMTPINTERN2/InternSMTP(Release 9.0.1FP5|November 22, 2015) at 15/02/2018 09:00:06, Serialize complete at 15/02/2018 09:00:06, Itemize by SMTP Server on BRSMTP01/Eggelsberg/AT/B&R(Release 9.0.1FP5|November 22, 2015) at 15.02.2018 09:00:04 X-TNEFEvaluated: 1 X-Disclaimed: 39659 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsVyYAWjjS6rXWuUwe6rhhZTe+Itvm3Zxmgx d+02dou3ezvZLQ5P/cBosffeZ0aLE20f2B3YPWY3XGTx2DnrLrvHh49xHoe/LmTxOHtnB6PH xnc7mDxOTP/OEsAexWWTkpqTWZZapG+XwJUx42MHY8Ff3oobc7YwNjCu5O5i5OSQEDCR2Hp0 G2MXIxeHkMAmRomvjVcYQRK8AoISJ2c+Yeli5OBgE3CXeDrRGCQsIiAh8av/Klg9s8ANJomF 37+wgySEBSwlds97xAJiswioSuy/9IAFYo6PRPPfTlYQm1lAW2LZwtfMEIvlJQ6/aWIFGSQh 0MEscWfNDnaIhJDE6cVnmUEWSwgIS/SuyZzAyDcLyUmzkIxawMi0ilE8NzEzx0gvqUg3sbQk PzexJDM/Ty85P3cTIyRkBXYw7n6jfYhRgINRiYc3JKklSog1say4MvcQowQHs5II7wa51igh 3pTEyqrUovz4otKc1OJDjNIcLErivDlJxlFCAumJJanZqakFqUUwWSYOTqkGxj7T17bvRE1c Vyo/M46Ky6xrPV+/InHmZC7+dc1Hfp/0/n643V9K7eO28IWPP59hd+9d53g10uZmuECuh4RO TaTn2hPfexdoqT2V2u54SotjVsnnH01rcyLnzDKI4Vw9Vyzu79zcR8rBl66UrK7VPB03Y/2H cP3Q2bMl5FxmdG/ivOYvYrR7tRJLcUaioRZzUXEiALqT6/hVAgAA Cc: "xypron.glpk@gmx.de" , Hou Zhiqiang Subject: [U-Boot] [PATCH] pci: Fix decode regions for memory banks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Since memory banks may not be located behind each other we need to add them separately. Signed-off-by: Bernhard Messerklinger Reviewed-by: Hannes Schmelzer --- drivers/pci/pci-uclass.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 5a24eb6428..ad43e8a27c 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -815,7 +815,6 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, ofnode node) { int pci_addr_cells, addr_cells, size_cells; - phys_addr_t base = 0, size; int cells_per_record; const u32 *prop; int len; @@ -874,6 +873,21 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, } /* Add a region for our local memory */ +#ifdef CONFIG_NR_DRAM_BANKS + bd_t *bd = gd->bd; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + pci_set_region(hose->regions + hose->region_count++, + bd->bi_dram[i].start, + bd->bi_dram[i].start, + bd->bi_dram[i].size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + } + } +#else + phys_addr_t base = 0, size; + size = gd->ram_size; #ifdef CONFIG_SYS_SDRAM_BASE base = CONFIG_SYS_SDRAM_BASE; @@ -882,6 +896,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, size = gd->pci_ram_top - base; pci_set_region(hose->regions + hose->region_count++, base, base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); +#endif return 0; }