From patchwork Mon Jan 31 11:01:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1586607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=Bwmiav8/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JnQG66vrfz9s07 for ; Mon, 31 Jan 2022 22:05:33 +1100 (AEDT) Received: from localhost ([::1]:42182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUUz-0001tt-L5 for incoming@patchwork.ozlabs.org; Mon, 31 Jan 2022 06:05:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEURm-0001tJ-By for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:10 -0500 Received: from [2a00:1450:4864:20::130] (port=34321 helo=mail-lf1-x130.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEURk-00041r-Cm for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:09 -0500 Received: by mail-lf1-x130.google.com with SMTP id p27so26078845lfa.1 for ; Mon, 31 Jan 2022 03:02:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xZHH89LsVmLHUEqQmJxUYBMXp2gD032NRq/kWsZbaZA=; b=Bwmiav8/JATZaEKoAFpUUiXkvXaK3+n+xb63qKZCJ4IvGx+kWo8Uvd3tMNhdaBWpj+ 2nNPCD5o+95sqGcYRWVT5DHTiM5lGC+0MqYdBgcRjlGVxCYaLMop1pwtXOtzk85X5sP2 OKTLGnsPpqOcv5LSbvdmf4SSaMFYCgKtdJmw9RO5QnseWqGWv9GWkPs4Rv8E1Ud2PEcJ g01Jo7BPIxRZlaqLSr24vjhVIFV50vDkeUIK/1BXp30YoG1YWK5MvKxWg5JHO5WCNKjp uJ8yVVju5Nd/zyVEoYv74oJeAzluxxgp5Oexa2tBMy27w3cwmD055Uj7MFxaUoIZKI8p iqLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xZHH89LsVmLHUEqQmJxUYBMXp2gD032NRq/kWsZbaZA=; b=6A/Eoyv4fqZmn/Z/be1aGeQ3U2rHTqp8a4RY+koezq0pGfRrZO/n3MXIPnBdNY4HT0 sotzVmkZmGN4AJDN6OaFPwfOSb3+b+NtVzaX0V6MNcUh+K4LdznrCV97hwQhQ6zAr+CB KqVzr+ORKIkX+E6V79O77uRMkbZf03YErPgDA30A9D4dHK/HC1a5ivP9ar/xLuHvGcdE nQf9DQB3zltUeOjyXDt01XL+NC/lFiawT6T8S1nYeUZ+f0btTlqa5O3cdj6yk9+PNAxp aR15Sp1YT8tljFYEGsAuS9y656ojm2nbdvK58qD1Y5TopmCJELMf2IAd7X7D1Gysc2r4 N8qQ== X-Gm-Message-State: AOAM533dJECUnU552ol41xIl33CmktsdvZTnCAvqx8YnHAB2/82gtAuP GchuoAw/a2BKg23yqvs30m+EXDuqiLp/5Q0q X-Google-Smtp-Source: ABdhPJxZEUxKpgYU1gsHJoNfQ/zXtkQVjuPTXOkh6KHZPYpyc6/znuR6Zr8LBKWFDTYLLC1AAF+cqA== X-Received: by 2002:a05:6512:2241:: with SMTP id i1mr15101336lfu.622.1643626926231; Mon, 31 Jan 2022 03:02:06 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:05 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Date: Mon, 31 Jan 2022 12:01:55 +0100 Message-Id: <20220131110201.2303275-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::130 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x130.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philipp Tomsich Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v4) Changes in v4: - use a typedef into 'RISCVCPUConfig' (instead of the explicit 'struct RISCVCPUConfig') to comply with the coding standard (as suggested in Richard's review of v3) Changes in v3: - (new patch) refactor 'struct RISCVCPUConfig' target/riscv/cpu.h | 78 ++++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55635d68d5..1175915c0d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,46 @@ struct RISCVCPUClass { DeviceReset parent_reset; }; +struct RISCVCPUConfig { + bool ext_i; + bool ext_e; + bool ext_g; + bool ext_m; + bool ext_a; + bool ext_f; + bool ext_d; + bool ext_c; + bool ext_s; + bool ext_u; + bool ext_h; + bool ext_j; + bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; + bool ext_counters; + bool ext_ifencei; + bool ext_icsr; + bool ext_zfh; + bool ext_zfhmin; + bool ext_zve32f; + bool ext_zve64f; + + char *priv_spec; + char *user_spec; + char *bext_spec; + char *vext_spec; + uint16_t vlen; + uint16_t elen; + bool mmu; + bool pmp; + bool epmp; + uint64_t resetvec; +}; + +typedef struct RISCVCPUConfig RISCVCPUConfig; + /** * RISCVCPU: * @env: #CPURISCVState @@ -320,43 +360,7 @@ struct RISCVCPU { char *dyn_vreg_xml; /* Configuration Settings */ - struct { - bool ext_i; - bool ext_e; - bool ext_g; - bool ext_m; - bool ext_a; - bool ext_f; - bool ext_d; - bool ext_c; - bool ext_s; - bool ext_u; - bool ext_h; - bool ext_j; - bool ext_v; - bool ext_zba; - bool ext_zbb; - bool ext_zbc; - bool ext_zbs; - bool ext_counters; - bool ext_ifencei; - bool ext_icsr; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; - - char *priv_spec; - char *user_spec; - char *bext_spec; - char *vext_spec; - uint16_t vlen; - uint16_t elen; - bool mmu; - bool pmp; - bool epmp; - uint64_t resetvec; - } cfg; + RISCVCPUConfig cfg; }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) From patchwork Mon Jan 31 11:01:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1586609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=Qk/gzuA3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:06 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Date: Mon, 31 Jan 2022 12:01:56 +0100 Message-Id: <20220131110201.2303275-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" As the number of extensions is growing, copying them individiually into the DisasContext will scale less and less... instead we populate a pointer to the RISCVCPUConfig structure in the DisasContext. This adds an extra indirection when checking for the availability of an extension (compared to copying the fields into DisasContext). While not a performance problem today, we can always (shallow) copy the entire structure into the DisasContext (instead of putting a pointer to it) if this is ever deemed necessary. Signed-off-by: Philipp Tomsich Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v5: - use the typedef in DisasContext instead of the naked struct for RISCVCPUConfig Changes in v3: - (new patch) copy pointer to element cfg into DisasContext target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0bbe80875..49e40735ce 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -76,6 +76,7 @@ typedef struct DisasContext { int frm; RISCVMXL ol; bool virt_enabled; + const RISCVCPUConfig *cfg_ptr; bool ext_ifencei; bool ext_zfh; bool ext_zfhmin; @@ -908,6 +909,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #endif ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ + ctx->cfg_ptr = &(cpu->cfg); ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->ext_zfh = cpu->cfg.ext_zfh; ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; From patchwork Mon Jan 31 11:01:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1586617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=WAEMnR2K; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JnQN51tWSz9sFN for ; Mon, 31 Jan 2022 22:10:44 +1100 (AEDT) Received: from localhost ([::1]:48948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUa2-0006z1-Ly for incoming@patchwork.ozlabs.org; Mon, 31 Jan 2022 06:10:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEURq-0001uP-LO for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:15 -0500 Received: from [2a00:1450:4864:20::130] (port=37614 helo=mail-lf1-x130.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEURm-00042O-GO for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:13 -0500 Received: by mail-lf1-x130.google.com with SMTP id n8so26031645lfq.4 for ; Mon, 31 Jan 2022 03:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5fkjd2RtBCe7xx4Yx1gDVgUFpdSIxSf69Mx7ruFr8oU=; b=WAEMnR2KuZaHdccD0GlKhwLFFlVni/ZhKxdhtyvReh+6D2Yi0MOT8sUO70ZAcbeQQ8 lyr7hGfRAjSlVyb+Pa3FcnAazOZPT8kzmwR/ZQ2HadGJMQHFvJmseNPt2KmRvtte4iqH SY9t77nSCnvasXyS97LQDaqYzsfIkswobiTHq8T+nu2pGgb4xZ4gaDfeoEu4dR4iGK4O h/vYKr80upC4Off9YQMJl89kTYMd0BxdKWyOgqB4WCy0SqVNf9YdAxaEkSP9xpnwkUif 7cLHUNZobTlnM289zRJZK7syFT3+E3efC6giPfo62TO6H3/17Mnc/wfrugFxeJwFk2kn 1+XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5fkjd2RtBCe7xx4Yx1gDVgUFpdSIxSf69Mx7ruFr8oU=; b=NZDCxRHB+iJM1dodjqQC3bUbzZroxKiTZxLtM5hMALWyUiHGt9G/KeE/I9PdtyhEw6 6sH5e+kj/VW+YSnmugiN/beP0dv2FzvBTWU+2+NUAYM5Jv8WaHjX2y3h7CLqJ1uHzO+A ceD5+seEpcEuxYRk3Mda+2UbBb/lElOvffIwPRvdsA2iNEI78SDEmjFIppmWiLivrUie 4FbLN0wyfZR2wi+rUKjPAApf34rTt/QBSS/KHwMs2z7bXtjGU0dMGWSQKCzMYt8yOTVd a36yumeLcWFUPwIpKPpXM6pzw3f3b40BBHv/nDTNHoiGrOvPLb8B14LHe8wIItVKp7vr 4ufA== X-Gm-Message-State: AOAM531k3KN2/XOxQuCxMEyl9sxS+wVUiBjROtDr4wp/B+eJli6k7NqV ULEMAPkJ4qKy+l0adRDVH0aijmNkNLa/kCf9 X-Google-Smtp-Source: ABdhPJzLsrhyvzK1nqhHQBJ9gsAaTpQXWZuCgje4dmbj1+Pnj5P05DqlB6VkzBIdafZ/T1u+e8WBkg== X-Received: by 2002:ac2:44ac:: with SMTP id c12mr15454019lfm.589.1643626928258; Mon, 31 Jan 2022 03:02:08 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:07 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 3/7] target/riscv: access configuration through cfg_ptr in DisasContext Date: Mon, 31 Jan 2022 12:01:57 +0100 Message-Id: <20220131110201.2303275-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::130 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x130.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow copies (in DisasContext) of some of the elements available in the RISCVCPUConfig structure. This commit redirects accesses to use the cfg_ptr copied into DisasContext and removes the shallow copies. Signed-off-by: Philipp Tomsich Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - (new patch) test extension-availability through cfg_ptr in DisasContext, removing the fields that have been copied into DisasContext directly target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++++----------- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- target/riscv/translate.c | 14 --- 4 files changed, 55 insertions(+), 69 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 3cd1b3f877..f1342f30f8 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -806,7 +806,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a) static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { - if (!ctx->ext_ifencei) { + if (!ctx->cfg_ptr->ext_ifencei) { return false; } diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f85a9e83b4..ff09e345ad 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -74,7 +74,7 @@ static bool require_zve32f(DisasContext *s) } /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve32f ? s->sew <= MO_32 : true; + return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true; } static bool require_scale_zve32f(DisasContext *s) @@ -85,7 +85,7 @@ static bool require_scale_zve32f(DisasContext *s) } /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <= MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true; } static bool require_zve64f(DisasContext *s) @@ -96,7 +96,7 @@ static bool require_zve64f(DisasContext *s) } /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <= MO_32 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true; } static bool require_scale_zve64f(DisasContext *s) @@ -107,7 +107,7 @@ static bool require_scale_zve64f(DisasContext *s) } /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <= MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true; } /* Destination vector register group cannot overlap source mask register. */ @@ -174,7 +174,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) TCGv s1, dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || s->cfg_ptr->ext_zve64f)) { return false; } @@ -210,7 +210,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) TCGv dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || s->cfg_ptr->ext_zve64f)) { return false; } @@ -248,7 +248,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a) /* vector register offset from env */ static uint32_t vreg_ofs(DisasContext *s, int reg) { - return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8; + return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8; } /* check functions */ @@ -318,7 +318,7 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, * when XLEN=32. (Section 18.2) */ if (get_xl(s) == MXL_RV32) { - ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true); + ret &= (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? eew != MO_64 : true); } return ret; @@ -454,7 +454,7 @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm) { return (s->lmul <= 2) && (s->sew < MO_64) && - ((s->sew + 1) <= (s->elen >> 4)) && + ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) && require_align(vd, s->lmul + 1) && require_vm(vm, vd); } @@ -482,7 +482,7 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, { return (s->lmul <= 2) && (s->sew < MO_64) && - ((s->sew + 1) <= (s->elen >> 4)) && + ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) && require_align(vs2, s->lmul + 1) && require_align(vd, s->lmul) && require_vm(vm, vd); @@ -661,7 +661,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. */ - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -819,7 +819,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, mask = tcg_temp_new_ptr(); base = get_gpr(s, rs1, EXT_NONE); stride = get_gpr(s, rs2, EXT_NONE); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -925,7 +925,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, mask = tcg_temp_new_ptr(); index = tcg_temp_new_ptr(); base = get_gpr(s, rs1, EXT_NONE); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); @@ -1065,7 +1065,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); base = get_gpr(s, rs1, EXT_NONE); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -1120,7 +1120,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, uint32_t data = FIELD_DP32(0, VDATA, NF, nf); dest = tcg_temp_new_ptr(); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); base = get_gpr(s, rs1, EXT_NONE); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -1185,7 +1185,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) static inline uint32_t MAXSZ(DisasContext *s) { int scale = s->lmul - 3; - return scale < 0 ? s->vlen >> -scale : s->vlen << scale; + return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale; } static bool opivv_check(DisasContext *s, arg_rmrr *a) @@ -1220,7 +1220,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); } mark_vs_dirty(s); gen_set_label(over); @@ -1262,7 +1262,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1425,7 +1425,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1508,7 +1508,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); @@ -1587,7 +1587,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1663,7 +1663,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1843,7 +1843,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1963,7 +1963,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a) * are not included for EEW=64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); + (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true); } static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) @@ -1976,7 +1976,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) * are not included for EEW=64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); + (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true); } GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) @@ -2046,7 +2046,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); gen_set_label(over); } @@ -2083,7 +2083,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) }; tcg_gen_ext_tl_i64(s1_i64, s1); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1_i64, cpu_env, desc); @@ -2123,7 +2123,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) s1 = tcg_constant_i64(simm); dest = tcg_temp_new_ptr(); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, cpu_env, desc); @@ -2176,7 +2176,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a) * for EEW=64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); + (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true); } static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a) @@ -2187,7 +2187,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a) * for EEW=64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); + (!has_ext(s, RVV) && s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true); } GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check) @@ -2275,7 +2275,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2302,7 +2302,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -2391,7 +2391,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2464,7 +2464,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2583,7 +2583,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -2696,7 +2696,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); dest = tcg_temp_new_ptr(); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew - 1](dest, t1, cpu_env, desc); @@ -2782,7 +2782,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2831,7 +2831,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2896,7 +2896,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2947,7 +2947,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2986,7 +2986,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && (s->sew < MO_64) && - ((s->sew + 1) <= (s->elen >> 4)); + ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)); } GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) @@ -3034,7 +3034,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, fn); \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ @@ -3067,7 +3067,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); dst = dest_gpr(s, a->rd); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3099,7 +3099,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); dst = dest_gpr(s, a->rd); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3134,7 +3134,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ - cpu_env, s->vlen / 8, s->vlen / 8, \ + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -3174,7 +3174,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) }; tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); return true; @@ -3200,7 +3200,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) gen_helper_vid_v_w, gen_helper_vid_v_d, }; tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3554,7 +3554,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) if (a->vm && s->vl_eq_vlmax) { int scale = s->lmul - (s->sew + 3); - int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax = scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale; TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { @@ -3586,7 +3586,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) if (a->vm && s->vl_eq_vlmax) { int scale = s->lmul - (s->sew + 3); - int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax = scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale; if (a->rs1 >= vlmax) { tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); @@ -3638,7 +3638,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3657,7 +3657,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ if (require_rvv(s) && \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ - uint32_t maxsz = (s->vlen >> 3) * LEN; \ + uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \ if (s->vstart == 0) { \ /* EEW = 8 */ \ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ @@ -3742,7 +3742,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq) tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5a7cac8958..608c51da2c 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -17,13 +17,13 @@ */ #define REQUIRE_ZFH(ctx) do { \ - if (!ctx->ext_zfh) { \ + if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ } while (0) #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ - if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ } while (0) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 49e40735ce..f19d5cd0c0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -77,11 +77,6 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool ext_ifencei; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; bool hlsx; /* vector extension */ bool vill; @@ -99,8 +94,6 @@ typedef struct DisasContext { */ int8_t lmul; uint8_t sew; - uint16_t vlen; - uint16_t elen; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -910,13 +903,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->cfg_ptr = &(cpu->cfg); - ctx->ext_ifencei = cpu->cfg.ext_ifencei; - ctx->ext_zfh = cpu->cfg.ext_zfh; - ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; - ctx->ext_zve32f = cpu->cfg.ext_zve32f; - ctx->ext_zve64f = cpu->cfg.ext_zve64f; - ctx->vlen = cpu->cfg.vlen; - ctx->elen = cpu->cfg.elen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:08 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 4/7] target/riscv: access cfg structure through DisasContext Date: Mon, 31 Jan 2022 12:01:58 +0100 Message-Id: <20220131110201.2303275-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Zb[abcs] support code still uses the RISCV_CPU macros to access the configuration information (i.e., check whether an extension is available/enabled). Now that we provide this information directly from DisasContext, we can access this directly via the cfg_ptr field. Signed-off-by: Philipp Tomsich Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied into DisasContext) instead of going throuhg RISCV_CPU target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 810431a1d6..f9bd3b7ec4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -19,25 +19,25 @@ */ #define REQUIRE_ZBA(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \ + if (ctx->cfg_ptr->ext_zba) { \ return false; \ } \ } while (0) #define REQUIRE_ZBB(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \ + if (ctx->cfg_ptr->ext_zbb) { \ return false; \ } \ } while (0) #define REQUIRE_ZBC(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \ + if (ctx->cfg_ptr->ext_zbc) { \ return false; \ } \ } while (0) #define REQUIRE_ZBS(ctx) do { \ - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \ + if (ctx->cfg_ptr->ext_zbs) { \ return false; \ } \ } while (0) From patchwork Mon Jan 31 11:01:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1586640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=tPQQVfDo; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JnQtH4M02z9s0r for ; Mon, 31 Jan 2022 22:33:27 +1100 (AEDT) Received: from localhost ([::1]:47420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nEUvy-0001Lt-FY for incoming@patchwork.ozlabs.org; Mon, 31 Jan 2022 06:33:23 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59646) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nEURt-0001va-KW for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:17 -0500 Received: from [2a00:1450:4864:20::12e] (port=45870 helo=mail-lf1-x12e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nEURn-00042j-Vn for qemu-devel@nongnu.org; Mon, 31 Jan 2022 06:02:17 -0500 Received: by mail-lf1-x12e.google.com with SMTP id o12so25964558lfg.12 for ; Mon, 31 Jan 2022 03:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vi1Tgy/IbE0IvvHZZuVY5QrlYxeUvg3PBjevFW4of4Y=; b=tPQQVfDoC+Mho1i25LFTupK9rbbHxTBFVxo7AyIfESn/5WFilpf6UqmwjK33dgLoPV FJrS/B220UuzkyMM88fSq2w/KKRfRBxCXznkfNHPPOVluA0PWo8XIIOgOHGBKedsQcOi burUpUbWfjWKUW1GIdvLGd50uGsneke7GiHhOFKIHdfS/jaANZCm/4ZlKnPVDGI1c9OZ 7qsKN6/lZg6Vdz/pd0X6ETRG5qjgFw/pHqsjFjymdrXJaYjf/w/GQhPbixkN5sDVEXE7 92gYFAQfLd7EZNCuq1tzUkyB2qi+y/hOjQvsZLydbn9ndUifpadm0RYzIynw/izCCcFo 3M0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vi1Tgy/IbE0IvvHZZuVY5QrlYxeUvg3PBjevFW4of4Y=; b=6pgBMoDNXZFgauGXPWwO32cCZ0ykLX61irb+r/vh4qOiYR7nl1DfDJd2s55Fliy4iH 5PMbIaYdU8SOwJ6uY3WiThUtGvCKn0zFX6j5AWqnAunCn2fjzzlNxBL97aQfkJyBZfiT ybcsTfiV2eNWr5adeKwAPoktY/1rcG94XLUn4JU31sBSznzU8eJ+SUP11MM5U7he45FD QDyJr1Q7pGTBNC9Pdx5oD554QSC5ukp72z9vM6xbqJ6YSFO3WUPIX8HPLisJfcmVFtwx cO+LzmOURrWUa3/2kPZA0ztiyPwddMH6pAKr3pmJx+CRQj0/cqlenSmRpL5uSU4jQdwV V0nw== X-Gm-Message-State: AOAM5327bOHveKl3OndlZ1/B2qkCJAyjID+kbXlDFcm0CHGCxKz2RwhL qQdcMyIxn+Mhijg+TZED5+YlbFxfqbxb9wzt X-Google-Smtp-Source: ABdhPJxpweDmbFgUecv63L8IcpR0z8HkpgMcWF0NKE9bujveH2DJw7TI6XZuZU2K+HpeovuPPuvlZg== X-Received: by 2002:a05:6512:52b:: with SMTP id o11mr15062836lfc.267.1643626930055; Mon, 31 Jan 2022 03:02:10 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:09 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 5/7] target/riscv: iterate over a table of decoders Date: Mon, 31 Jan 2022 12:01:59 +0100 Message-Id: <20220131110201.2303275-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To split up the decoder into multiple functions (both to support vendor-specific opcodes in separate files and to simplify maintenance of orthogonal extensions), this changes decode_op to iterate over a table of decoders predicated on guard functions. This commit only adds the new structure and the table, allowing for the easy addition of additional decoders in the future. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v4) Changes in v4: - add braces to comply with coding standard (as suggested by Richard) - merge the two if-statements to reduce clutter after (now that the braces have been added) Changes in v3: - expose only the DisasContext* to predicate functions - mark the table of decoder functions as static - drop the inline from always_true_p, until the need arises (i.e., someone finds a use for it and calls it directly) - rewrite to drop the 'handled' temporary in iterating over the decoder table, removing the assignment in the condition of the if Changes in v2: - (new patch) iterate over a table of guarded decoder functions target/riscv/translate.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f19d5cd0c0..30b1b68341 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -111,6 +111,11 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa_ext & ext; } +static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) +{ + return true; +} + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -855,15 +860,26 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { - /* check for compressed insn */ + /* + * A table with predicate (i.e., guard) functions and decoder functions + * that are tested in-order until a decoder matches onto the opcode. + */ + static const struct { + bool (*guard_func)(DisasContext *); + bool (*decode_func)(DisasContext *, uint32_t); + } decoders[] = { + { always_true_p, decode_insn32 }, + }; + + /* Check for compressed insn */ if (extract16(opcode, 0, 2) != 3) { if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { ctx->opcode = opcode; ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (!decode_insn16(ctx, opcode)) { - gen_exception_illegal(ctx); + if (decode_insn16(ctx, opcode)) { + return; } } } else { @@ -873,10 +889,16 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) ctx->base.pc_next + 2)); ctx->opcode = opcode32; ctx->pc_succ_insn = ctx->base.pc_next + 4; - if (!decode_insn32(ctx, opcode32)) { - gen_exception_illegal(ctx); + + for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { + if (decoders[i].guard_func(ctx) && + decoders[i].decode_func(ctx, opcode32)) { + return; + } } } + + gen_exception_illegal(ctx); } static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) From patchwork Mon Jan 31 11:02:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1586625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull.eu header.i=@vrull.eu header.a=rsa-sha256 header.s=google header.b=dzsQTKjN; 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Mon, 31 Jan 2022 03:02:10 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:10 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 6/7] target/riscv: Add XVentanaCondOps custom extension Date: Mon, 31 Jan 2022 12:02:00 +0100 Message-Id: <20220131110201.2303275-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::229 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x229.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This adds the decoder and translation for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf This commit then also adds a guard-function (has_XVentanaCondOps_p) and the decoder function to the table of decoders, enabling the support for the XVentanaCondOps extension. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - rename to trans_xventanacondops.c.inc (i.e. with the '.c') - (in MATERIALISE_EXT_PREDICATE) don't annotate the predicate function for testing the availability of individual extensions as 'inline' and don't make CPURISCVState* visible to these predicate functions Changes in v2: - Split off decode table into XVentanaCondOps.decode - Wire up XVentanaCondOps in the decoder-table target/riscv/XVentanaCondOps.decode | 25 ++++++++++++ target/riscv/cpu.c | 3 ++ target/riscv/cpu.h | 3 ++ .../insn_trans/trans_xventanacondops.c.inc | 39 +++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 12 ++++++ 6 files changed, 83 insertions(+) create mode 100644 target/riscv/XVentanaCondOps.decode create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode new file mode 100644 index 0000000000..5aef7c3d72 --- /dev/null +++ b/target/riscv/XVentanaCondOps.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the XVentanaCondOps extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VTx-family custom instructions +# Custom ISA extensions for Ventana Micro Systems RISC-V cores +# (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# *** RV64 Custom-3 Extension *** +vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r +vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1cb0436187..6df07b8289 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -734,6 +734,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1175915c0d..aacc997d56 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -329,6 +329,9 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; + /* Vendor-specific custom extensions */ + bool ext_XVentanaCondOps; + char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc new file mode 100644 index 0000000000..b8a5d031b5 --- /dev/null +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc @@ -0,0 +1,39 @@ +/* + * RISC-V translation routines for the XVentanaCondOps extension. + * + * Copyright (c) 2021-2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_NE); +} + +static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_EQ); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a3997ed580..91f0ac32ff 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -4,6 +4,7 @@ dir = meson.current_source_dir() gen = [ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']), decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), + decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] riscv_ss = ss.source_set() diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 30b1b68341..eaf5a72c81 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,6 +116,14 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) return true; } +#define MATERIALISE_EXT_PREDICATE(ext) \ + static bool has_ ## ext ## _p(DisasContext *ctx) \ + { \ + return ctx->cfg_ptr->ext_ ## ext ; \ + } + +MATERIALISE_EXT_PREDICATE(XVentanaCondOps); + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -854,9 +862,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_xventanacondops.c.inc" /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +/* Include decoders for factored-out extensions */ +#include "decode-XVentanaCondOps.c.inc" static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { @@ -869,6 +880,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] = { { always_true_p, decode_insn32 }, + { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u22sm1952759lfl.26.2022.01.31.03.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 03:02:11 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v5 7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Date: Mon, 31 Jan 2022 12:02:01 +0100 Message-Id: <20220131110201.2303275-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> References: <20220131110201.2303275-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Greg Favor , Richard Henderson , Kito Cheng , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The XVentanaCondOps extension is supported by VRULL on behalf of the Ventana Micro. Add myself as a point-of-contact. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - add a MAINTAINERS entry for XVentanaCondOps MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b43344fa98..2e0b2ae947 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -286,6 +286,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XVentanaCondOps extension +M: Philipp Tomsich +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/XVentanaCondOps.decode +F: target/riscv/insn_trans/trans_xventanacondops.c.inc + RENESAS RX CPUs R: Yoshinori Sato S: Orphan