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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones , katie.morris@in-advantage.com Subject: [RFC v6 net-next 1/9] pinctrl: ocelot: allow pinctrl-ocelot to be loaded as a module Date: Sat, 29 Jan 2022 14:02:13 -0800 Message-Id: <20220129220221.2823127-2-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220129220221.2823127-1-colin.foster@in-advantage.com> References: <20220129220221.2823127-1-colin.foster@in-advantage.com> X-ClientProxiedBy: CO1PR15CA0113.namprd15.prod.outlook.com (2603:10b6:101:21::33) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 370ede25-dde9-401d-6efe-08d9e3731143 X-MS-TrafficTypeDiagnostic: BYAPR10MB2968:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pu6WBvYENCWU0KK/udd+R7dkJCBTtWBn1HSF56NCM/Gf3s5bA88lxhfgjGqmUcZjkMe3ALXn4CU8XO+TWoJyYPeNLzrrB0vCR5fI3rs2WUaOd70MkmMwCc2dqrY3x4Uprm8xvj0t6lfccT72P7EVQe30inGWGZYu2Xp9YTdvGy1gR0U8bUV4Kk561ltZfDhzRiaIan2XL0QabN3BiNoXDGLBz0r6OFHQzrsykQjh5wnmwLChU/rH8J4p23nJEq1440zn+5JYMxLd5veo2CJG6rvB/Uffw1J60GCkkIpxxZ/q2br80jjtiv6BCewz29weHT9JtX9IzTNAwGwZkQ/yTzdfHoq2Yc9wzYf44e21c0shVlu4V6oih9BS43hS3SKU9A593u2ZITMQ8VVvPEKDu0/7yeO1txmeKmF8hNeUYx73PufW8m15DSpKjCyDzLod2lMY819Y7SY5Sxys8YPSELWV3GPLSw+50h190IX+Oax8frMdlAp6GCJV+588ZuS+wVrEUBQ8ryi3pphOdW9649whTeiK7v39d1NuMtOywTLuGapyacCZwRbDdjMzPR0pvLYytRln731ZtElLuefpZSQ44mA43pQWKI+eDAAsZ5lq8OIbNyJ2ez1sPMGPg9TDorZkZ6siNyTYAzuvPcZAQLXcz8ppOwCg9TFlAb2XxL1UrjtPIxNjdfLPHOeaayBOpnUWUqsM/cc+LPGqy0NMxA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(136003)(376002)(346002)(42606007)(396003)(39830400003)(366004)(186003)(508600001)(5660300002)(6486002)(1076003)(86362001)(66946007)(8676002)(66476007)(26005)(4326008)(66556008)(8936002)(7416002)(107886003)(6506007)(38350700002)(6512007)(2906002)(44832011)(6666004)(2616005)(52116002)(38100700002)(83380400001)(316002)(36756003)(54906003)(20210929001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0NY9U/yZwx87PXhfbfQLQZOdvXhDIPveF9yB9BOuIcDL+TkbrHMGR+elznOyPvrFtin6/li802jQORRHxos/SYGsdXzqsrCe15xBBcwPhM4zBEMfHFFwASdTCenxw5Zbyrt9deg/UqBPgbcwPezUcCQGWtmcIPvfZl3TT1FcKPkcAjg4hKSUdfvQvKtl1XmCvzZBZUDYSR79l6MPP+EqQurf+JQ2IqV3b6wRqUTmrYCB2xLKAKgE2LAYWRQsSV5PXxzB987QXkSPJGCGgv9WmIYhMDLbyq0u17f9Op9S42ABkqWfhhRdkakk88eco7I94Uy0JobVMnHAgViScsOy3zWEkZqONdGRAyNzeQl0iZNnDmIemiU4CJYtDgZ5xVSqPTXYIlPl8bzv3/YSCB4NOQur1AIOrpmVCmGOn7X5rrPYRZF49GzqFoDaTEtzONdM2XAxrMKY6ICrQEjZ+rOVpC/z3PslivY3lOjkzo5KFYLiDY74Egof3cjPaQBCk189KDzAWtRA8fzthk1rE823JB9WYHJj+bYXYr7llgLO5vQUTVA8BWNgSTGMlyaTeikKpp8nY0S9RwhsIxAyeM5Wjl19YMN3dvh40BKCjtqHCAwgXQXdjzeg0cFCZ4yivls3mdh0LXYaUqadZ+heiXrmwSYhz3/ZixPrlbxgEBwBsb8eCOc5Hh/L4t14z0DGFkPGi0Ovpd8NGj9iDSS9zX1OSv4W/ZAeJAwLjfCzkNiHUs9bsa8MD5B6JnAlaoV24G/V2W0Ydr9SpoFqQH6KjFv1uu59fY7XnfStsFf5PT3CEvw0xWzrAXHgVSSQCI79n1htzlEGVc4PWJrW9ZOGropznKZU3bazTCalYaX4/+FwCAQ0MKArsAGpogAemDEfsKquvWmMAPNalPL1wI+e1Ng4e3QQAC0OMndKGltbL4r1nDiZHVDWQt78n3o/EWVsokBabtSya+Hx1InJsaJiANSHv31fupjBN8ScE77agzJ/XBKzA7N47hWivTWdJslQtaRS23PTzE32pB52OjpDSjp5sCxvtCLVaJemt1T1iq4XmAu3BYgmHbs4dZhoHO6YM3e+W+rqci5A2uA8/B0RxAAXCrSV4B9/ipnGAj+oeTEPnt8wjB8DjX5b8q3sDyC+9Z9o6J06dvqWDb5NWfFTcRXwcGnswPCcBWFvh90avtquFrzQF52FKj2cxfziwblQIcjTeos37SQp8ymt8thmUFzjptZHykMQ/6Xw0NMDH50Mgq7V3gcvLz4lq4LNRXxW5vZvxkvRGFsjaAxNAWMTSc9P7lSAXdUM3462PtkH1U2AuJ5ENKUszLFH4iC8KVXswQNoC+PKq2Zxtk4DNM/kbvU9B+5fJfDzqDx5qbZtZoJPq1zTnHv/UDCnH5ofgByTNSLovaeONozUtHJqWBK1r1wsj1wMAhJql6jpS4WKLsghbrwT5Ro26opccECK/LDdAZDA412DW9Q/USTMHMeXzpbnJ/O70S0RykQ3+NmA0/kAuynx4FCKwQ6CCJFq3wxsLdcP8ETGAnyn9gbFZdDDK4NWO2ihYHl0uLtacgL7AIo8chpr4GKd/fk1xF2pSjCyQq8n2bSRAhZq6tBM6VsIth4I/Tq7fS/U/mQ5YsamajokvOegysyYaLK/++c+AUzgrIIbnOnfD0rVvzb64dg1WyKCiQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 370ede25-dde9-401d-6efe-08d9e3731143 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 22:02:40.2511 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1Y5umALmqAN7fCOOnbUECdEx9W41GtjChETwP4hoqBdTk0KFoQNwOL9yC5Q+frqbhZoO7SCbb7QxB0I72W4DpuukpEWEjr/LKd4eddKKSrY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR10MB2968 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Work is being done to allow external control of Ocelot chips. When pinctrl drivers are used internally, it wouldn't make much sense to allow them to be loaded as modules. In the case where the Ocelot chip is controlled externally, this scenario becomes practical. Signed-off-by: Colin Foster Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-ocelot.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6fc56d6598e2..1b367f423ceb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -311,7 +311,7 @@ config PINCTRL_MICROCHIP_SGPIO LED controller. config PINCTRL_OCELOT - bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs" + tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs" depends on OF depends on HAS_IOMEM select GPIOLIB diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fc969208d904..b6ad3ffb4596 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1778,6 +1778,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, }; +MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) { @@ -1866,3 +1867,6 @@ static struct platform_driver ocelot_pinctrl_driver = { .probe = ocelot_pinctrl_probe, }; builtin_platform_driver(ocelot_pinctrl_driver); + +MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver"); +MODULE_LICENSE("Dual MIT/GPL"); From patchwork Sat Jan 29 22:02:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 1586288 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=inadvantage.onmicrosoft.com header.i=@inadvantage.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-inadvantage-onmicrosoft-com header.b=YEqFS63v; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones , katie.morris@in-advantage.com Subject: [RFC v6 net-next 2/9] pinctrl: microchip-sgpio: allow sgpio driver to be used as a module Date: Sat, 29 Jan 2022 14:02:14 -0800 Message-Id: <20220129220221.2823127-3-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220129220221.2823127-1-colin.foster@in-advantage.com> References: <20220129220221.2823127-1-colin.foster@in-advantage.com> X-ClientProxiedBy: CO1PR15CA0113.namprd15.prod.outlook.com (2603:10b6:101:21::33) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5c2ff40b-5511-42e4-047f-08d9e37311bd X-MS-TrafficTypeDiagnostic: BYAPR10MB2968:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:294; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: biH2OV0zx8jl+yfiZcT2+3R5Vxu4jEih2X+dCSPflr5ze8Q8zdlYliNQuI19JpihNN2P2Xpm5DRouuL+CtI9halLr5VZREqkgXfyi661LIlfRW9MKAQyY0vcXWRmzo4QD9uFAIjg8cNMFJygfzIA2VfwI6WOcQn9IVSYQA/yKSe7CoiBXjHDATslUQbdDBjohEGejEg5bl64Rror+zAI8MosikFrcRqhJNsWwqN5WHr3gmj28bZvkqgM4gXBrbS3dfM9B0Is2AY8l6qrnAUoEO2aOhYGkRwtjKFN78gjf1FDx3IngkCYPke7hosDQegcaLnHsuZbRMRjmesP9SPQTbvRFyygszNL3YhAGFQPHFutl33YJsVptoiHXrlXhLjzPwxPoZNzvmhiOyLez1OqUur/JjzFQVMPEQO6MKPCA/k38tLjqTPATZvlbpxTwOMs3CLnXjtF0e7vwmGml6Kt0bFoUvK4iCTfGOHL9oe71vsCdLTK8Ov19Ro8b9LZKBlljowQlJ9eFb5uU8Zafh+uCASrhmrekHnidOBwmjHMXqku8DMWFFh4t5/W3FIx0PolCG8l0EvRMYwKWTiSzl1VQXF3OdAcbSo7cDbQ1RVkzVqj1QQ08cSUha9y8/qbstb43H13xP+KwjARgrGf2vB/Hd0titXMXGmmRgn6gg3iB1oWvsyN9leFf8PJ85OSLV/x X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(136003)(376002)(346002)(42606007)(396003)(39830400003)(366004)(186003)(508600001)(5660300002)(6486002)(1076003)(86362001)(66946007)(8676002)(66476007)(26005)(4326008)(66556008)(8936002)(7416002)(107886003)(6506007)(38350700002)(6512007)(2906002)(44832011)(6666004)(2616005)(52116002)(38100700002)(83380400001)(316002)(36756003)(54906003)(20210929001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ycvr+AfwIzoiY9yBOyiBzwlUChKLcLN+n9AG1G50L5xf0IFrO/Rw4Cy6KqT+D/GUs1imXlnMcXkWLBU1nC/EOMfGgQGH6ezg8wecwG0+XXWS+4u0KPfOhqPcNNSIiAbSDdk4xDh43I6l/nuricVeQDW3nrCqbu9TV4oUVNP/j8M/wI/UBOdbL77woWt4775R2qifIOcWnbz/prb9iFflbUADJJ+aDMG8AjuskjLI8Bw4lKvXnyd2pzbgUyuKzZ/tdcnlK5apkwl01TB2otQ5ZphOdCccBbfrYh6QOQOYqHYVf9LayGtJ6qmzvM4GGVAEj+aVSRj2NOnovB/N9HNt/IP3Xm0uTX6Sx5Swwjd59BhO+2jLXAmUro2UP11Pb2JlQRoMnxkD9tPTCsPDUhruEW+Z2IyDfYnrbRwmQYLSRgySKqbdyeBAHugcmpdaG0su2gkzYPz1+td65wXy+EwILBge3jgKObfaa2GtCkI5S7SbRu4z01SGq6TXpMUP/gCUkqAjbp7g+Z2jGKuUDmZ6Uq+PIOVMNi/6kBmOFq2LFQ2GUmCaTCt3eoaOqclHK59pSwWPTIN0i7dX+LMeKHOabF3MnSryQ9PJaFH+ImoDZQtxRUoOHWieaLyT27AAjtb/cJm9oImEOy3DnGIZs8EitMJRC4Q6cDtGpxQlBsa5bGHtZs/0Bo5kw0CArl3Yoa5YiOM6W4F4B+02jc5/WsDmT5UCu8Hzle1/S2aN/+oK+1qwO4hmPaP9nAEnABPbj5B1IjmVGVbJZFILW35Ea5073K8/kq/dsw3bMvszZ5l26QJCd/xgu+J/u8MILEwQLjGgj2NdZ4CMteh+6zWi6tZt2/D1BPgPckzyTvb4FvC20JUcX40oN87ETkj12ex9aZzi2J47XzBmYI4HIKzQ5MtMywNgUMTxYX9EHcTKMxWZaHq+fD8H5N+tRoCdOcGWJHXSW0ufxlLzFWE0vhd5iBfBIfaIt5cu2uuMR4l1R8N/lVf8DLr12gSdJspp2aRrp65HR5Y90xMxl0oQPWTSfLj7sZBTMtF9sb+SEgf+SGI0LybyT8LBNSsj2byykvI7MU3pDJvj9WIxFfDlOlkNmcGJaMWGjopZpUqjIHxb9CVRztiz7rRtybUUz33xZPoHnE7qtGAJylM7SZzyizAumvQ48brMvjn0RHDSHJX2MneHadOlcOEeQ+XhIwzbCE0YI221iRLMMZpsUEiNmYP57cHnQiyKQ6wwslX9ygt6qud3FKjJxxxdtis0qslO3cbaerSNtXEWdbpmWH+TOe4lMtTUF9ujgjsIgwUODtpG3YNQIkAupz6tMje23XhAG90MBCOLvxkN9FzaJUqc9Cb7qeZJj2Yn6+atYaWYciCURRtcnO59FbWeSXKs4+Ss6Zk4WyqywoY3+qQOhip4UZijSrJl/tO9BPEWv1zaWcahCUy5AsR1w1abmwqvtvzmO7pD2xc0RReZB+07F7xNwCKM55q3WVn2dvC27x7J+7IUYkF6H72xpoiWYLFeE4O/wWioFowqB6RuAiD1iHm+Bi5Jdok6e9x5zW5U2FnuLP139tHs4Zy9C3mb8egxEE6VPCOUjqDljUD4HmGWAoptYRIcc9AuEBxk+s9yymC+HnafRCGfx2mFo1ZUbwUEql1+l9zwni+ocyWIQ9TzMoky+LMx8+OECg== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c2ff40b-5511-42e4-047f-08d9e37311bd X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 22:02:40.9386 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: h5kPQtnJkMfsBU0pjJnPWBWB+2KFCbDYqY1S4+S32LfVaenY8oKheEXKWhQEf4wzusiGWjAkZmJ26S4vAKnDeAOfLCsS4k57NXAOBXJFYw8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR10MB2968 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As the commit message suggests, this simply adds the ability to select SGPIO pinctrl as a module. This becomes more practical when the SGPIO hardware exists on an external chip, controlled indirectly by I2C or SPI. This commit enables that level of control. Signed-off-by: Colin Foster Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/pinctrl-microchip-sgpio.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1b367f423ceb..7ff00c560775 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -292,7 +292,7 @@ config PINCTRL_MCP23S08 corresponding interrupt-controller. config PINCTRL_MICROCHIP_SGPIO - bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + tristate "Pinctrl driver for Microsemi/Microchip Serial GPIO" depends on OF depends on HAS_IOMEM select GPIOLIB diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 8e081c90bdb2..8db3caf15cf2 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -912,6 +912,7 @@ static const struct of_device_id microchip_sgpio_gpio_of_match[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match); static struct platform_driver microchip_sgpio_pinctrl_driver = { .driver = { @@ -922,3 +923,6 @@ static struct platform_driver microchip_sgpio_pinctrl_driver = { .probe = microchip_sgpio_probe, }; builtin_platform_driver(microchip_sgpio_pinctrl_driver); + +MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Sat Jan 29 22:02:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 1586290 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=inadvantage.onmicrosoft.com header.i=@inadvantage.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-inadvantage-onmicrosoft-com header.b=YDHCh6VK; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- drivers/net/mdio/mdio-mscc-miim.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 7d2abaf2b2c9..6b14f3cf3891 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -220,6 +220,7 @@ EXPORT_SYMBOL(mscc_miim_setup); static int mscc_miim_probe(struct platform_device *pdev) { struct regmap *mii_regmap, *phy_regmap = NULL; + struct device *dev = &pdev->dev; void __iomem *regs, *phy_regs; struct mscc_miim_dev *miim; struct resource *res; @@ -228,38 +229,37 @@ static int mscc_miim_probe(struct platform_device *pdev) regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(regs)) { - dev_err(&pdev->dev, "Unable to map MIIM registers\n"); + dev_err(dev, "Unable to map MIIM registers\n"); return PTR_ERR(regs); } - mii_regmap = devm_regmap_init_mmio(&pdev->dev, regs, - &mscc_miim_regmap_config); + mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config); if (IS_ERR(mii_regmap)) { - dev_err(&pdev->dev, "Unable to create MIIM regmap\n"); + dev_err(dev, "Unable to create MIIM regmap\n"); return PTR_ERR(mii_regmap); } /* This resource is optional */ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { - phy_regs = devm_ioremap_resource(&pdev->dev, res); + phy_regs = devm_ioremap_resource(dev, res); if (IS_ERR(phy_regs)) { - dev_err(&pdev->dev, "Unable to map internal phy registers\n"); + dev_err(dev, "Unable to map internal phy registers\n"); return PTR_ERR(phy_regs); } - phy_regmap = devm_regmap_init_mmio(&pdev->dev, phy_regs, + phy_regmap = devm_regmap_init_mmio(dev, phy_regs, &mscc_miim_regmap_config); if (IS_ERR(phy_regmap)) { - dev_err(&pdev->dev, "Unable to create phy register regmap\n"); + dev_err(dev, "Unable to create phy register regmap\n"); return PTR_ERR(phy_regmap); } } - ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0); + ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0); if (ret < 0) { - dev_err(&pdev->dev, "Unable to setup the MDIO bus\n"); + dev_err(dev, "Unable to setup the MDIO bus\n"); return ret; } @@ -267,9 +267,9 @@ static int mscc_miim_probe(struct platform_device *pdev) miim->phy_regs = phy_regmap; miim->phy_reset_offset = 0; - ret = of_mdiobus_register(bus, pdev->dev.of_node); + ret = of_mdiobus_register(bus, dev->of_node); if (ret < 0) { - dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); + dev_err(dev, "Cannot register MDIO bus (%d)\n", ret); return ret; } From patchwork Sat Jan 29 22:02:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 1586291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=inadvantage.onmicrosoft.com header.i=@inadvantage.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-inadvantage-onmicrosoft-com header.b=Xi5LJrgD; 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This commit exposes that variable so it can be utilized. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/seville_vsc9953.c | 3 ++- drivers/net/mdio/mdio-mscc-miim.c | 10 ++++++---- include/linux/mdio/mdio-mscc-miim.h | 3 ++- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index 8c1c9da61602..c6264e9f4c37 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -1021,7 +1021,8 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus", ocelot->targets[GCB], - ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]); + ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK], + NULL, 0); if (rc) { dev_err(dev, "failed to setup MDIO bus\n"); diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 6b14f3cf3891..07baf8390744 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -188,7 +188,8 @@ static const struct regmap_config mscc_miim_regmap_config = { }; int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name, - struct regmap *mii_regmap, int status_offset) + struct regmap *mii_regmap, int status_offset, + struct regmap *phy_regmap, int phy_offset) { struct mscc_miim_dev *miim; struct mii_bus *bus; @@ -210,6 +211,8 @@ int mscc_miim_setup(struct device *dev, struct mii_bus **pbus, const char *name, miim->regs = mii_regmap; miim->mii_status_offset = status_offset; + miim->phy_regs = phy_regmap; + miim->phy_reset_offset = phy_offset; *pbus = bus; @@ -257,15 +260,14 @@ static int mscc_miim_probe(struct platform_device *pdev) } } - ret = mscc_miim_setup(dev, &bus, "mscc_miim", mii_regmap, 0); + ret = mscc_miim_setup(&pdev->dev, &bus, "mscc_miim", mii_regmap, 0, + phy_regmap, 0); if (ret < 0) { dev_err(dev, "Unable to setup the MDIO bus\n"); return ret; } miim = bus->priv; - miim->phy_regs = phy_regmap; - miim->phy_reset_offset = 0; ret = of_mdiobus_register(bus, dev->of_node); if (ret < 0) { diff --git a/include/linux/mdio/mdio-mscc-miim.h b/include/linux/mdio/mdio-mscc-miim.h index 5b4ed2c3cbb9..5a95e43f73f9 100644 --- a/include/linux/mdio/mdio-mscc-miim.h +++ b/include/linux/mdio/mdio-mscc-miim.h @@ -14,6 +14,7 @@ int mscc_miim_setup(struct device *device, struct mii_bus **bus, const char *name, struct regmap *mii_regmap, - int status_offset); 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An example of this would be if a regmap were directly memory-mapped or an external bus. In the memory-mapped case a call to devm_regmap_init_mmio would return the correct regmap. In the case of an MFD, the regmap would need to be requested from the parent device. This addition allows the driver to correctly reason about these scenarios. Signed-off-by: Colin Foster --- drivers/mfd/mfd-core.c | 6 ++++++ include/linux/mfd/core.h | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c index 684a011a6396..2ba6a692499b 100644 --- a/drivers/mfd/mfd-core.c +++ b/drivers/mfd/mfd-core.c @@ -33,6 +33,12 @@ static struct device_type mfd_dev_type = { .name = "mfd_device", }; +int device_is_mfd(struct platform_device *pdev) +{ + return (!strcmp(pdev->dev.type->name, mfd_dev_type.name)); +} +EXPORT_SYMBOL(device_is_mfd); + int mfd_cell_enable(struct platform_device *pdev) { const struct mfd_cell *cell = mfd_get_cell(pdev); diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h index 0bc7cba798a3..c0719436b652 100644 --- a/include/linux/mfd/core.h +++ b/include/linux/mfd/core.h @@ -10,6 +10,7 @@ #ifndef MFD_CORE_H #define MFD_CORE_H +#include #include #define MFD_RES_SIZE(arr) (sizeof(arr) / sizeof(struct resource)) @@ -123,6 +124,15 @@ struct mfd_cell { int num_parent_supplies; }; +#ifdef CONFIG_MFD_CORE +int device_is_mfd(struct platform_device *pdev); +#else +static inline int device_is_mfd(struct platform_device *pdev) +{ + return 0; +} +#endif + /* * Convenience functions for clients using shared cells. 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This should allow any ocelot driver (pinctrl, miim, etc.) to be used externally, provided they utilize regmaps. Signed-off-by: Colin Foster --- drivers/mfd/Kconfig | 19 ++ drivers/mfd/Makefile | 3 + drivers/mfd/ocelot-core.c | 165 +++++++++++ drivers/mfd/ocelot-spi.c | 325 ++++++++++++++++++++++ drivers/mfd/ocelot.h | 36 +++ drivers/net/mdio/mdio-mscc-miim.c | 21 +- drivers/pinctrl/pinctrl-microchip-sgpio.c | 22 +- drivers/pinctrl/pinctrl-ocelot.c | 29 +- include/soc/mscc/ocelot.h | 11 + 9 files changed, 614 insertions(+), 17 deletions(-) create mode 100644 drivers/mfd/ocelot-core.c create mode 100644 drivers/mfd/ocelot-spi.c create mode 100644 drivers/mfd/ocelot.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ba0b3eb131f1..57bbf2d11324 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -948,6 +948,25 @@ config MFD_MENF21BMC This driver can also be built as a module. If so the module will be called menf21bmc. +config MFD_OCELOT + tristate "Microsemi Ocelot External Control Support" + select MFD_CORE + help + Say yes here to add support for Ocelot chips (VSC7511, VSC7512, + VSC7513, VSC7514) controlled externally. + + All four of these chips can be controlled internally (MMIO) or + externally via SPI, I2C, PCIe. This enables control of these chips + over one or more of these buses. + +config MFD_OCELOT_SPI + tristate "Microsemi Ocelot SPI interface" + depends on MFD_OCELOT + depends on SPI_MASTER + select REGMAP_SPI + help + Say yes here to add control to the MFD_OCELOT chips via SPI. + config EZX_PCAP bool "Motorola EZXPCAP Support" depends on SPI_MASTER diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index df1ecc4a4c95..12513843067a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -120,6 +120,9 @@ obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o obj-$(CONFIG_MFD_CORE) += mfd-core.o +obj-$(CONFIG_MFD_OCELOT) += ocelot-core.o +obj-$(CONFIG_MFD_OCELOT_SPI) += ocelot-spi.o + obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c new file mode 100644 index 000000000000..590489481b8c --- /dev/null +++ b/drivers/mfd/ocelot-core.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * MFD core driver for the Ocelot chip family. + * + * The VSC7511, 7512, 7513, and 7514 can be controlled internally via an + * on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is + * intended to be the bus-agnostic glue between, for example, the SPI bus and + * the MFD children. + * + * Copyright 2021 Innovative Advantage Inc. + * + * Author: Colin Foster + */ + +#include +#include +#include + +#include + +#include "ocelot.h" + +#define GCB_SOFT_RST (0x0008) + +#define SOFT_CHIP_RST (0x1) + +static const struct resource vsc7512_gcb_resource = { + .start = 0x71070000, + .end = 0x7107022b, + .name = "devcpu_gcb", +}; + +static int ocelot_reset(struct ocelot_core *core) +{ + int ret; + + /* + * Reset the entire chip here to put it into a completely known state. + * Other drivers may want to reset their own subsystems. The register + * self-clears, so one write is all that is needed + */ + ret = regmap_write(core->gcb_regmap, GCB_SOFT_RST, SOFT_CHIP_RST); + if (ret) + return ret; + + msleep(100); + + /* + * A chip reset will clear the SPI configuration, so it needs to be done + * again before we can access any more registers + */ + ret = ocelot_spi_initialize(core); + + return ret; +} + +static struct regmap *ocelot_devm_regmap_init(struct ocelot_core *core, + struct device *dev, + const struct resource *res) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(dev, res->name); + if (!regmap) + regmap = ocelot_spi_devm_get_regmap(core, dev, res); + + return regmap; +} + +struct regmap *ocelot_get_regmap_from_resource(struct device *dev, + const struct resource *res) +{ + struct ocelot_core *core = dev_get_drvdata(dev); + + return ocelot_devm_regmap_init(core, dev, res); +} +EXPORT_SYMBOL(ocelot_get_regmap_from_resource); + +static const struct resource vsc7512_miim1_resources[] = { + { + .start = 0x710700c0, + .end = 0x710700e3, + .name = "gcb_miim1", + .flags = IORESOURCE_MEM, + }, +}; + +static const struct resource vsc7512_pinctrl_resources[] = { + { + .start = 0x71070034, + .end = 0x7107009f, + .name = "gcb_gpio", + .flags = IORESOURCE_MEM, + }, +}; + +static const struct resource vsc7512_sgpio_resources[] = { + { + .start = 0x710700f8, + .end = 0x710701f7, + .name = "gcb_sio", + .flags = IORESOURCE_MEM, + }, +}; + +static const struct mfd_cell vsc7512_devs[] = { + { + .name = "pinctrl-ocelot", + .of_compatible = "mscc,ocelot-pinctrl", + .num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources), + .resources = vsc7512_pinctrl_resources, + }, + { + .name = "pinctrl-sgpio", + .of_compatible = "mscc,ocelot-sgpio", + .num_resources = ARRAY_SIZE(vsc7512_sgpio_resources), + .resources = vsc7512_sgpio_resources, + }, + { + .name = "ocelot-miim1", + .of_compatible = "mscc,ocelot-miim", + .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), + .resources = vsc7512_miim1_resources, + }, +}; + +int ocelot_core_init(struct ocelot_core *core) +{ + struct device *dev = core->dev; + int ret; + + dev_set_drvdata(dev, core); + + core->gcb_regmap = ocelot_devm_regmap_init(core, dev, + &vsc7512_gcb_resource); + if (!core->gcb_regmap) + return -ENOMEM; + + /* Prepare the chip */ + ret = ocelot_reset(core); + if (ret) { + dev_err(dev, "ocelot mfd reset failed with code %d\n", ret); + return ret; + } + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, vsc7512_devs, + ARRAY_SIZE(vsc7512_devs), NULL, 0, NULL); + if (ret) { + dev_err(dev, "error adding mfd devices\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(ocelot_core_init); + +int ocelot_remove(struct ocelot_core *core) +{ + return 0; +} +EXPORT_SYMBOL(ocelot_remove); + +MODULE_DESCRIPTION("Ocelot Chip MFD driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c new file mode 100644 index 000000000000..1e268a4dfa17 --- /dev/null +++ b/drivers/mfd/ocelot-spi.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * SPI core driver for the Ocelot chip family. + * + * This driver will handle everything necessary to allow for communication over + * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions + * are to prepare the chip's SPI interface for a specific bus speed, and a host + * processor's endianness. This will create and distribute regmaps for any MFD + * children. + * + * Copyright 2021 Innovative Advantage Inc. + * + * Author: Colin Foster + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "ocelot.h" + +struct ocelot_spi { + int spi_padding_bytes; + struct spi_device *spi; + struct ocelot_core core; + struct regmap *cpuorg_regmap; +}; + +#define DEV_CPUORG_IF_CTRL (0x0000) +#define DEV_CPUORG_IF_CFGSTAT (0x0004) + +static const struct resource vsc7512_dev_cpuorg_resource = { + .start = 0x71000000, + .end = 0x710002ff, + .name = "devcpu_org", +}; + +#define VSC7512_BYTE_ORDER_LE 0x00000000 +#define VSC7512_BYTE_ORDER_BE 0x81818181 +#define VSC7512_BIT_ORDER_MSB 0x00000000 +#define VSC7512_BIT_ORDER_LSB 0x42424242 + +static struct ocelot_spi *core_to_ocelot_spi(struct ocelot_core *core) +{ + return container_of(core, struct ocelot_spi, core); +} + +static int ocelot_spi_init_bus(struct ocelot_spi *ocelot_spi) +{ + struct spi_device *spi; + struct device *dev; + u32 val, check; + int err; + + spi = ocelot_spi->spi; + dev = &spi->dev; + +#ifdef __LITTLE_ENDIAN + val = VSC7512_BYTE_ORDER_LE; +#else + val = VSC7512_BYTE_ORDER_BE; +#endif + + err = regmap_write(ocelot_spi->cpuorg_regmap, DEV_CPUORG_IF_CTRL, val); + if (err) + return err; + + val = ocelot_spi->spi_padding_bytes; + err = regmap_write(ocelot_spi->cpuorg_regmap, DEV_CPUORG_IF_CFGSTAT, + val); + if (err) + return err; + + check = val | 0x02000000; + + err = regmap_read(ocelot_spi->cpuorg_regmap, DEV_CPUORG_IF_CFGSTAT, + &val); + if (err) + return err; + + if (check != val) + return -ENODEV; + + return 0; +} + +int ocelot_spi_initialize(struct ocelot_core *core) +{ + struct ocelot_spi *ocelot_spi = core_to_ocelot_spi(core); + + return ocelot_spi_init_bus(ocelot_spi); +} +EXPORT_SYMBOL(ocelot_spi_initialize); + +static unsigned int ocelot_spi_translate_address(unsigned int reg) +{ + return cpu_to_be32((reg & 0xffffff) >> 2); +} + +struct ocelot_spi_regmap_context { + u32 base; + struct ocelot_spi *ocelot_spi; +}; + +static int ocelot_spi_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ocelot_spi_regmap_context *regmap_context = context; + struct ocelot_spi *ocelot_spi = regmap_context->ocelot_spi; + struct spi_transfer tx, padding, rx; + struct spi_message msg; + struct spi_device *spi; + unsigned int addr; + u8 *tx_buf; + + WARN_ON(!val); + + spi = ocelot_spi->spi; + + addr = ocelot_spi_translate_address(reg + regmap_context->base); + tx_buf = (u8 *)&addr; + + spi_message_init(&msg); + + memset(&tx, 0, sizeof(struct spi_transfer)); + + /* Ignore the first byte for the 24-bit address */ + tx.tx_buf = &tx_buf[1]; + tx.len = 3; + + spi_message_add_tail(&tx, &msg); + + if (ocelot_spi->spi_padding_bytes > 0) { + u8 dummy_buf[16] = {0}; + + memset(&padding, 0, sizeof(struct spi_transfer)); + + /* Just toggle the clock for padding bytes */ + padding.len = ocelot_spi->spi_padding_bytes; + padding.tx_buf = dummy_buf; + padding.dummy_data = 1; + + spi_message_add_tail(&padding, &msg); + } + + memset(&rx, 0, sizeof(struct spi_transfer)); + rx.rx_buf = val; + rx.len = 4; + + spi_message_add_tail(&rx, &msg); + + return spi_sync(spi, &msg); +} + +static int ocelot_spi_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ocelot_spi_regmap_context *regmap_context = context; + struct ocelot_spi *ocelot_spi = regmap_context->ocelot_spi; + struct spi_transfer tx[2] = {0}; + struct spi_message msg; + struct spi_device *spi; + unsigned int addr; + u8 *tx_buf; + + spi = ocelot_spi->spi; + + addr = ocelot_spi_translate_address(reg + regmap_context->base); + tx_buf = (u8 *)&addr; + + spi_message_init(&msg); + + /* Ignore the first byte for the 24-bit address and set the write bit */ + tx_buf[1] |= BIT(7); + tx[0].tx_buf = &tx_buf[1]; + tx[0].len = 3; + + spi_message_add_tail(&tx[0], &msg); + + memset(&tx[1], 0, sizeof(struct spi_transfer)); + tx[1].tx_buf = &val; + tx[1].len = 4; + + spi_message_add_tail(&tx[1], &msg); + + return spi_sync(spi, &msg); +} + +static const struct regmap_config ocelot_spi_regmap_config = { + .reg_bits = 24, + .reg_stride = 4, + .val_bits = 32, + + .reg_read = ocelot_spi_reg_read, + .reg_write = ocelot_spi_reg_write, + + .max_register = 0xffffffff, + .use_single_write = true, + .use_single_read = true, + .can_multi_write = false, + + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_NATIVE, +}; + +struct regmap * +ocelot_spi_devm_get_regmap(struct ocelot_core *core, struct device *dev, + const struct resource *res) +{ + struct ocelot_spi *ocelot_spi = core_to_ocelot_spi(core); + struct ocelot_spi_regmap_context *context; + struct regmap_config regmap_config; + struct regmap *regmap; + + context = devm_kzalloc(dev, sizeof(*context), GFP_KERNEL); + if (IS_ERR(context)) + return ERR_CAST(context); + + context->base = res->start; + context->ocelot_spi = ocelot_spi; + + memcpy(®map_config, &ocelot_spi_regmap_config, + sizeof(ocelot_spi_regmap_config)); + + regmap_config.name = res->name; + regmap_config.max_register = res->end - res->start; + + regmap = devm_regmap_init(dev, NULL, context, ®map_config); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + return regmap; +} + +static int ocelot_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct ocelot_spi *ocelot_spi; + int err; + + ocelot_spi = devm_kzalloc(dev, sizeof(*ocelot_spi), GFP_KERNEL); + + if (!ocelot_spi) + return -ENOMEM; + + if (spi->max_speed_hz <= 500000) { + ocelot_spi->spi_padding_bytes = 0; + } else { + /* + * Calculation taken from the manual for IF_CFGSTAT:IF_CFG. + * Register access time is 1us, so we need to configure and send + * out enough padding bytes between the read request and data + * transmission that lasts at least 1 microsecond. + */ + ocelot_spi->spi_padding_bytes = 1 + + (spi->max_speed_hz / 1000000 + 2) / 8; + } + + ocelot_spi->spi = spi; + + spi->bits_per_word = 8; + + err = spi_setup(spi); + if (err < 0) { + dev_err(&spi->dev, "Error %d initializing SPI\n", err); + return err; + } + + ocelot_spi->cpuorg_regmap = + ocelot_spi_devm_get_regmap(&ocelot_spi->core, dev, + &vsc7512_dev_cpuorg_resource); + if (!ocelot_spi->cpuorg_regmap) + return -ENOMEM; + + ocelot_spi->core.dev = dev; + + /* + * The chip must be set up for SPI before it gets initialized and reset. + * This must be done before calling init, and after a chip reset is + * performed. + */ + err = ocelot_spi_init_bus(ocelot_spi); + if (err) { + dev_err(dev, "Error %d initializing Ocelot SPI bus\n", err); + return err; + } + + err = ocelot_core_init(&ocelot_spi->core); + if (err < 0) { + dev_err(dev, "Error %d initializing Ocelot MFD\n", err); + return err; + } + + return 0; +} + +static int ocelot_spi_remove(struct spi_device *spi) +{ + return 0; +} + +const struct of_device_id ocelot_spi_of_match[] = { + { .compatible = "mscc,vsc7512_mfd_spi" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ocelot_spi_of_match); + +static struct spi_driver ocelot_spi_driver = { + .driver = { + .name = "ocelot_mfd_spi", + .of_match_table = of_match_ptr(ocelot_spi_of_match), + }, + .probe = ocelot_spi_probe, + .remove = ocelot_spi_remove, +}; +module_spi_driver(ocelot_spi_driver); + +MODULE_DESCRIPTION("Ocelot Chip MFD SPI driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("Dual MIT/GPL"); diff --git a/drivers/mfd/ocelot.h b/drivers/mfd/ocelot.h new file mode 100644 index 000000000000..8bb2b57002be --- /dev/null +++ b/drivers/mfd/ocelot.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include +#include + +struct ocelot_core { + struct device *dev; + struct regmap *gcb_regmap; +}; + +void ocelot_get_resource_name(char *name, const struct resource *res, + int size); +int ocelot_core_init(struct ocelot_core *core); +int ocelot_remove(struct ocelot_core *core); + +#if IS_ENABLED(CONFIG_MFD_OCELOT_SPI) +struct regmap *ocelot_spi_devm_get_regmap(struct ocelot_core *core, + struct device *dev, + const struct resource *res); +int ocelot_spi_initialize(struct ocelot_core *core); +#else +static inline struct regmap *ocelot_spi_devm_get_regmap( + struct ocelot_core *core, struct device *dev, + const struct resource *res) +{ + return NULL; +} + +static inline int ocelot_spi_initialize(struct ocelot_core *core) +{ + return -EOPNOTSUPP; +} +#endif diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 07baf8390744..8e54bde06fd5 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -11,11 +11,13 @@ #include #include #include +#include #include #include #include #include #include +#include #define MSCC_MIIM_REG_STATUS 0x0 #define MSCC_MIIM_STATUS_STAT_PENDING BIT(2) @@ -230,13 +232,20 @@ static int mscc_miim_probe(struct platform_device *pdev) struct mii_bus *bus; int ret; - regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(regs)) { - dev_err(dev, "Unable to map MIIM registers\n"); - return PTR_ERR(regs); - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!device_is_mfd(pdev)) { + regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regs)) { + dev_err(dev, "Unable to map MIIM registers\n"); + return PTR_ERR(regs); + } - mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config); + mii_regmap = devm_regmap_init_mmio(dev, regs, + &mscc_miim_regmap_config); + } else { + mii_regmap = ocelot_get_regmap_from_resource(dev->parent, res); + } if (IS_ERR(mii_regmap)) { dev_err(dev, "Unable to create MIIM regmap\n"); diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 8db3caf15cf2..53df095b33e0 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include "core.h" #include "pinconf.h" @@ -137,7 +139,9 @@ static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) { - return priv->properties->regoff[rno] + off; + int stride = regmap_get_reg_stride(priv->regs); + + return (priv->properties->regoff[rno] + off) * stride; } static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) @@ -818,6 +822,7 @@ static int microchip_sgpio_probe(struct platform_device *pdev) struct fwnode_handle *fwnode; struct reset_control *reset; struct sgpio_priv *priv; + struct resource *res; struct clk *clk; u32 __iomem *regs; u32 val; @@ -850,11 +855,18 @@ static int microchip_sgpio_probe(struct platform_device *pdev) return -EINVAL; } - regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(regs)) - return PTR_ERR(regs); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!device_is_mfd(pdev)) { + regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); + } else { + priv->regs = ocelot_get_regmap_from_resource(dev->parent, res); + } - priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index b6ad3ffb4596..d5485c6a0e20 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include "core.h" #include "pinconf.h" @@ -1123,6 +1125,9 @@ static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +#if defined(REG) +#undef REG +#endif #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32))) static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -1805,6 +1810,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; struct regmap *pincfg; + struct resource *res; void __iomem *base; int ret; struct regmap_config regmap_config = { @@ -1819,16 +1825,27 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) info->desc = (struct pinctrl_desc *)device_get_match_data(dev); - base = devm_ioremap_resource(dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); - if (IS_ERR(base)) - return PTR_ERR(base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) { + dev_err(dev, "Failed to get resource\n"); + return PTR_ERR(res); + } info->stride = 1 + (info->desc->npins - 1) / 32; - regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; + if (!device_is_mfd(pdev)) { + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap_config.max_register = + OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; + + info->map = devm_regmap_init_mmio(dev, base, ®map_config); + } else { + info->map = ocelot_get_regmap_from_resource(dev->parent, res); + } - info->map = devm_regmap_init_mmio(dev, base, ®map_config); if (IS_ERR(info->map)) { dev_err(dev, "Failed to create regmap\n"); return PTR_ERR(info->map); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 5c3a3597f1d2..70fae9c8b649 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -969,4 +969,15 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, } #endif +#if IS_ENABLED(CONFIG_MFD_OCELOT) +struct regmap *ocelot_get_regmap_from_resource(struct device *dev, + const struct resource *res); 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones , katie.morris@in-advantage.com Subject: [RFC v6 net-next 7/9] net: mscc: ocelot: expose ocelot wm functions Date: Sat, 29 Jan 2022 14:02:19 -0800 Message-Id: <20220129220221.2823127-8-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220129220221.2823127-1-colin.foster@in-advantage.com> References: <20220129220221.2823127-1-colin.foster@in-advantage.com> X-ClientProxiedBy: CO1PR15CA0113.namprd15.prod.outlook.com (2603:10b6:101:21::33) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 43c83174-7fa9-408f-06b1-08d9e37313f2 X-MS-TrafficTypeDiagnostic: BYAPR10MB2968:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 647ghaljNp8PxQuUonSpA9jDLl66UacaB/W9Or7ukhhxqsGO8qCvKRHTIusO/U1qJiqWJ/TRjovfNc+u/hoQ3muLbOAc9RQd5fxTHBOj/MOnQH9xxav+QA+Z7f6QDnNm0o7nBPxS4Rsj9tnaPfeIH6ptpjgGIXPh6S14kXrQBkHcJEdg/35+OGS2XR8gcZup/LE8hiLTFNsUxGbco7gSTjJw/wfMRVBsNKWeEci3HekL6alqa+Otcr1DJwdYto29MI12hoqfE0EVKp2d73H5tT4TvwNpjQOD8cXkZ7vvAgrfnhEBE28iJevkC/nC7XGPMfEJvzi/CadB5qkZHDnyiqWhBhqrvr71K8O7fRV5wFxJs87cX1XEwL37KjL2ivT74/Qa4KV/lA+oGrbdOw4Vb9ndH3yRVjvobJXQeL8LmoxWpDJamKmIEMiX0MhVyooUcqVvRDO9bUjAcBlkRfMVLOlxCPqVceH/Gz6q7l3zXpvo7gnXcT2kQ4dk4e5nMShAVwkgzHVz0aeTrIMu0+QvbKV8vcnLWQ1VEjm3N8P5KmF/LG2SdMGc1jTbsq/G+tdmfPO55vuS/iSkkSJdjU/xx/sIP9qU+HrKmm4+KcN7t7ZNGi5QgPzxN6ujpwsSpyoRbzHkH7NaTT9kLManeD+ZcF0LUWoAyZNcyIPks5b1dQH4GXp6bgjScHZFBGGuTkA9qz7c2yEG+iJhAFUI7ubROA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(136003)(376002)(346002)(42606007)(396003)(39830400003)(366004)(186003)(508600001)(5660300002)(6486002)(1076003)(86362001)(66946007)(8676002)(66476007)(26005)(4326008)(66556008)(8936002)(7416002)(107886003)(6506007)(38350700002)(6512007)(2906002)(44832011)(6666004)(2616005)(52116002)(38100700002)(83380400001)(316002)(36756003)(54906003)(20210929001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2ywiPSI29HSbdU2UDuvbn4Egih1S+NBTJPW606IG1vH54nvk3opgIPsrXFDXjFamFkfCEBvsQYPiddskvmvll+DlKkjSqaxSjU3Ramuog1gbiu5D0N1wGeoQmdjdbasoAMdbR/C1IMToPGH8KH5dZHe1RxW/4o0dVmvmzAckScKThZwAipRAkUJkHM5X9FjZeyr2vDCK5c/NHuV6Yyg7iLtpdQAAPlj02YOcDlVfccydwkQ3grmrq+STJWSrnNkSrqhHItppSPmSjvJQCVa2FQvIXmpeB75uERK2Cfyzl2gsVuT3D/6M/VYdwetw0SrvuPDApIEtm42hg6HVr3DFI9m2z5OD8EIaWRYdXg1ltAQagKhWYmmxgsbzYjN5MbHMZM7toYulY0laZ63vtFs1g7ODr50xyXt+oYPdXPlyw7DY+8uZSnf0WJkHYZMrItuVyxT6HUd1lm+E0c3T0nMURgZMqz8qlDFPQihj2SBM9XtlMZr94PT7yeO7uH8DxSmHm20F67tx5m8i4K9ZZiRCUTR40sDg/R9JuuyLKLMG1/BjGM0vNKbNTuW7kJo/IabBZHjTeSiVHWW9QwOHRHTSQHJ7qdErk2AwtQc+x2RrUeQ6YTnauXBUHw8a8ja8SU46/9mgTjZe2HLmMOVg3vwpMt5/ZcMl0UpF/RW6poZu8sI6ZKS5NRxnPR52cJJSvBVUVOKnQ4CTNR7eaJldpj4n+NfMXRc83BvsLJPOdN49rNY24RB2zAaBdJoocjaTj9Q2A9oD72dT6nrDoSGZBA2OmpcaptEZyu3X7MKOqohmcCq4FiObF1LpCbSWZ64QUnQE4xKmBR0cYCuW3GRF1h6txkZXktGNx6NxiWM+Eod7aNGLqF+Aq6X5pG8BXrnhTveXRdW9AOxHX8LNdtJ4WqGn7C2RgTDvhEJtfb67064l+koXEN6tWi72yBBc0XC9QO2OgojNJZWhyEGGWAN6aenxrt1/Gcjcgc7jDbFSXe5bRZFRkmXwgv3EViIZtIDjyVeZnSh8ICzShHqmuBHgu5g27Ba1Pz99xWjfbIxUW57nn1aMuHcDPfRWhSGmo9wPg4UDx1+8cIL2wK9rU6/KmZBXkt6CJmf7F0wZFzeWkmiMcJM8jeyCY7oza49/ARsXW2UmTPpFZHMjU+hes49OiOdxTSu34fZfUC9dH92DjlHZUJYJuWzZobhcNTLdYSeTGtbhMgoPGbw6MNai/3cNLBI10sdTDTrhLqPgrN7jueY/PvqFOPZg/fJVqaF9ajPaJp3fj+xocML3erikLnf0d6d2JUpTBMIZeWtFUuwKOtHTPpasr9EtOESam/KOatFlpm+xThVHV6fc52fY7zXFehOq0FRh28N65Xr0GpbTJ/8rbQm4NmJNW4XUhicTDbG7n8AIIPKuTAhDVbDO5wOgGPjXl8mffjTB66KfhE3Ida3esrJcvRvwH+yogUC9e6n8jhaMRjYR7XsugJABaArfPBnomcgTkVjXbvYbDz6W3j9wkydOsXSXAu/0ExkrQQw4jQ66us3rySrTWec5PqRgdPwyBY59dLPeamjt08p4oTaqAf4TtCD4BMvZxbQWS2pSU1bOivd37uANCnEacq0vt7CyVQzT6SmLC01dgCt4+0SchhLgmknq1hmmRsMWc8RT87JvB1v3RpinzrvrNKXPDr1//Q== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43c83174-7fa9-408f-06b1-08d9e37313f2 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 22:02:44.6570 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PgOkL0J5Wr5QaI+xDVbmZSt8eWMs2ucx/2dIw6GFwQVv9SxhJjn/gGaUmvOKshcfRwU+ZxON/nNdsT3g90rdsRySUQ6mDFyPR2kmSn+MhS0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR10MB2968 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Expose ocelot_wm functions so they can be shared with other drivers. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- drivers/net/ethernet/mscc/ocelot_devlink.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 28 ------------------- include/soc/mscc/ocelot.h | 5 ++++ 3 files changed, 36 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_devlink.c b/drivers/net/ethernet/mscc/ocelot_devlink.c index b8737efd2a85..d9ea75a14f2f 100644 --- a/drivers/net/ethernet/mscc/ocelot_devlink.c +++ b/drivers/net/ethernet/mscc/ocelot_devlink.c @@ -487,6 +487,37 @@ static void ocelot_watermark_init(struct ocelot *ocelot) ocelot_setup_sharing_watermarks(ocelot); } +/* Watermark encode + * Bit 8: Unit; 0:1, 1:16 + * Bit 7-0: Value to be multiplied with unit + */ +u16 ocelot_wm_enc(u16 value) +{ + WARN_ON(value >= 16 * BIT(8)); + + if (value >= BIT(8)) + return BIT(8) | (value / 16); + + return value; +} +EXPORT_SYMBOL(ocelot_wm_enc); + +u16 ocelot_wm_dec(u16 wm) +{ + if (wm & BIT(8)) + return (wm & GENMASK(7, 0)) * 16; + + return wm; +} +EXPORT_SYMBOL(ocelot_wm_dec); + +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) +{ + *inuse = (val & GENMASK(23, 12)) >> 12; + *maxuse = val & GENMASK(11, 0); +} +EXPORT_SYMBOL(ocelot_wm_stat); + /* Pool size and type are fixed up at runtime. Keeping this structure to * look up the cell size multipliers. */ diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 4f4a495a60ad..5e526545ef67 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -307,34 +307,6 @@ static int ocelot_reset(struct ocelot *ocelot) return 0; } -/* Watermark encode - * Bit 8: Unit; 0:1, 1:16 - * Bit 7-0: Value to be multiplied with unit - */ -static u16 ocelot_wm_enc(u16 value) -{ - WARN_ON(value >= 16 * BIT(8)); - - if (value >= BIT(8)) - return BIT(8) | (value / 16); - - return value; -} - -static u16 ocelot_wm_dec(u16 wm) -{ - if (wm & BIT(8)) - return (wm & GENMASK(7, 0)) * 16; - - return wm; -} - -static void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse) -{ - *inuse = (val & GENMASK(23, 12)) >> 12; - *maxuse = val & GENMASK(11, 0); -} - static const struct ocelot_ops ocelot_ops = { .reset = ocelot_reset, .wm_enc = ocelot_wm_enc, diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 70fae9c8b649..8b8ebede5a01 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -812,6 +812,11 @@ void ocelot_deinit(struct ocelot *ocelot); void ocelot_init_port(struct ocelot *ocelot, int port); void ocelot_deinit_port(struct ocelot *ocelot, int port); +/* Watermark interface */ +u16 ocelot_wm_enc(u16 value); +u16 ocelot_wm_dec(u16 wm); +void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse); + /* DSA callbacks */ void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data); void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data); From patchwork Sat Jan 29 22:02:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 1586295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=inadvantage.onmicrosoft.com header.i=@inadvantage.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-inadvantage-onmicrosoft-com header.b=xsR+Ddsp; dkim-atps=neutral Authentication-Results: ozlabs.org; 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Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones , katie.morris@in-advantage.com Subject: [RFC v6 net-next 8/9] net: dsa: felix: add configurable device quirks Date: Sat, 29 Jan 2022 14:02:20 -0800 Message-Id: <20220129220221.2823127-9-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220129220221.2823127-1-colin.foster@in-advantage.com> References: <20220129220221.2823127-1-colin.foster@in-advantage.com> X-ClientProxiedBy: CO1PR15CA0113.namprd15.prod.outlook.com (2603:10b6:101:21::33) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7261dedc-d4d0-403e-89cb-08d9e3731458 X-MS-TrafficTypeDiagnostic: BYAPR10MB2968:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Qnijt0nQ3SJZu7yJKWHIGLNNeQVinmJ0SFAj2O4LuibcAjgHE9/oyQiIIB15y9hAQhmoLQq0ot/RLzx4TbpriSuSJnHMJRnKjsplmdxnbe9DoVUuca7DiIyz1xBaTplqUS+UueoL+HAdKpZ2Su13UkCn2FSkepEBiJBN2VxVEIL4NfWijlKzQjjWVtfmfoJFYEf5+9BizdDlPfJgjtheGh+7Z8m8DSpmFvJtOOuBhm49bJiuFPc8nxlTBF2TZ5F8V0PoSESsYtXkLZA5anOXiVzedkaNrPZ+gQ7dYRYGkjY/poLFW5bh3sZLVRU1cMA1gPghZvqo/ihU32UcennQatn6aIRo22hBah7otRbSCwbGt8dp9NQ1zbTGEn52Pu6QsSvcvHxPSheX/sJOJESpUFA5qxAWzwB+2p57FrZTf12/G5qCFdA1h0hrmLrJkZGS1GWYe5VYDoR6Dtlaw9byE4itkAV00+CzhftmFzWDl8C9e5xJAOm37TPqGe1LXieTcddhBhxOucY87POyisbRTJCnUd27UD8cYRqMyjj6eFABwOVpQ/tYV7Q3aUCo/VQgvs1vOcsxoWNGsMRLywf/Sy6Hw0A1EaAyJyQ0ReVPoS8hzAeLWBSvMICs55ZA3hkGO+oE2ElOfQ3Bg/A9+O+uzcqLsbmF8XYZzT6UbzpctvA4U7E20ZuGWAHjOZqYvD7DuMHyfOO32gcwGlBRfBZ5Sg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(136003)(376002)(346002)(42606007)(396003)(39840400004)(366004)(186003)(508600001)(5660300002)(6486002)(1076003)(86362001)(66946007)(8676002)(66476007)(26005)(4326008)(66556008)(8936002)(7416002)(107886003)(6506007)(38350700002)(6512007)(2906002)(44832011)(6666004)(2616005)(52116002)(38100700002)(83380400001)(316002)(36756003)(54906003)(20210929001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: M7hQPUiyolR9tyoCUtQDPaGyCny7t/fyGn+GndiGp4PiCkM8Asr72Q5N1xGVSrg2CwVPClcZRPkAwZlLp66ggHug0YVxXwDz5tIfbrx5biXxlNUyeeSNmXeoKpz+ByadBj/z1Jnznzcwfw4RWBtnAsn4ZL0dzYbZy7A6fqoEBOWLY+UHqtx9a8jyRYwlWw3CX27/4Ru3wmUnMwyAP026tBNaO6CkHh6MqdGNEldMNlppEy23QekDMtMiKSt4txKZoH2uyaGJ5DkeHzB4Dl+j+UlHbfWK3ChReF71FBTTOEoukiSLQHj+4rqggstUL9olkUMRXSmXPo++lddWGuCwbKIsV7/I1MqyzFpuiHzLpSIWU7kDINn1YUo77lFS+fhawirkWH/aOiZhWKoOjwppxWCS3FbXQzjZr6tySzAnmUAuiQ/yyP1fgaS5v8NFsVyt9yQcUYld++U0ugP2wNLIbiNtKGitGDoBvRwEy39SFICwq7x1a5xW7/X7d7VdgJz4mOgfxvxpEZOmyUddt8KXNx+Exh5e74rj76YtWBdVQknxamayQQ3NZ7vQy8DLtyT/Rh7qqvAtExZO9+bDL6JsPJR6e+C9eg9mWUTkBmxqzBqwAawX58+xasmvUrspFcLodwaORjiuzjJj1pKQApiR8D6mluwEAevmIR4GGokhpXX6Gm/xZ1ZysUFnHNo901LcshX75rSr03MBwaHEAj+sHISZwmy+Js93lx4i/PLMRqFULZSBS7J1DrpUnLgVybrNDjqcCDbDgtOjEffOIWBU91yKscfTgHIKu9zVq5/aHrwDE7elcB82cUOeYT9yWACmey48c2+CJuTKABwV8HaqukzTEOl4NnmYCaxktqQXRfpUSA4JQMfisIILZ0pIfPJS9ygSXbAKxEbxhs1ZETIjTkfql2Awldg//rqlyCDZuY3N/CAe0NOCKEVDvzv42B1NokCVraX3/PSJQwI0C/0q1RwQ3Bzuf1a2SfWO13oY96muHmALCjrqpRT2PR2XAxGuKLw6+ky/0Ye7uesZK9gKn2CCIT+srUS46JpwAfESK6gR3pCWgyC3W6IdxrxoRYZy5CWc3sZhlhVsK3GUXkCoD1K3/uq887brCgZtPz7JoZ7BjgufC5ZtFTQp5iAP3i78Y62yfErAqi54IK4tDsDHlEETsvhouUnwr+PMjYjVew3OQpcU17cRwTuB+vl5sgyArXLe/fAxQYFGulrDCh3xagGl92b/IhFJ5a9GZ3r7LjTZr5nopZAc+MkbfR17UW6iAUVTLUl4zpVXI/grUsFAIcy41UtlkW5XrgVvv6ZDbPiYnz9XXXyJx+5uQUORF6/0PK4ELaBwPVvlkfNRpsz3YKRsIHw7Hecgz7EIQ3EUV9DUDWHRsOSKt4H4SQievQuBe0IWJk0861aEG5N5PwwW7rN3MeZvdi7rIYrKVBQOdG+ngJCNqyESo5yBp2WGKCiV0ix6EWnCndTs9NFq66AoFJOE35ecuuR+SsNpy75m1JjdS3OQS4YCvGYEjbPasxr9EEh7gB6angTa9sI1kKo/W6U4D8dXVdjabEAVkClyVY33DwFDUFtkwwqbq4pa5Ooa9uHabIMU7asapBRRl+LNCNTDdg7krjHt0ZtLwB/7Mq8aae1xAQOPbqQYtS0H/0sfJjZtjMsM5XkvFEojuZFSMQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7261dedc-d4d0-403e-89cb-08d9e3731458 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 22:02:45.3445 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CV4r4G4enX6jp66VspLvXD57vCbDixx2bMNAkXv2AT9MBTppxHts2ZhaazwRmdthYx3TKoCO98jFhlRQXM8slppLDYH9M4buOGfkOyc7cbw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR10MB2968 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The define FELIX_MAC_QUIRKS was used directly in the felix.c shared driver. Other devices (VSC7512 for example) don't require the same quirks, so they need to be configured on a per-device basis. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- drivers/net/dsa/ocelot/felix.c | 7 +++++-- drivers/net/dsa/ocelot/felix.h | 1 + drivers/net/dsa/ocelot/felix_vsc9959.c | 1 + drivers/net/dsa/ocelot/seville_vsc9953.c | 1 + 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index 9957772201d5..4c086bcf111b 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -850,9 +850,12 @@ static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, phy_interface_t interface) { struct ocelot *ocelot = ds->priv; + struct felix *felix; + + felix = ocelot_to_felix(ocelot); ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, - FELIX_MAC_QUIRKS); + felix->info->quirks); } static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, @@ -867,7 +870,7 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, interface, speed, duplex, tx_pause, rx_pause, - FELIX_MAC_QUIRKS); + felix->info->quirks); if (felix->info->port_sched_speed_set) felix->info->port_sched_speed_set(ocelot, port, speed); diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h index 9395ac119d33..f35894b06ce5 100644 --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h @@ -26,6 +26,7 @@ struct felix_info { u16 vcap_pol_base2; u16 vcap_pol_max2; const struct ptp_clock_info *ptp_caps; + u32 quirks; /* Some Ocelot switches are integrated into the SoC without the * extraction IRQ line connected to the ARM GIC. By enabling this diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index bf8d38239e7e..7e88480cc103 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -2231,6 +2231,7 @@ static const struct felix_info felix_info_vsc9959 = { .num_mact_rows = 2048, .num_ports = 6, .num_tx_queues = OCELOT_NUM_TC, + .quirks = FELIX_MAC_QUIRKS, .quirk_no_xtr_irq = true, .ptp_caps = &vsc9959_ptp_caps, .mdio_bus_alloc = vsc9959_mdio_bus_alloc, diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c index c6264e9f4c37..aa31f741634e 100644 --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c @@ -1100,6 +1100,7 @@ static const struct felix_info seville_info_vsc9953 = { .vcap_pol_max = VSC9953_VCAP_POLICER_MAX, .vcap_pol_base2 = VSC9953_VCAP_POLICER_BASE2, .vcap_pol_max2 = VSC9953_VCAP_POLICER_MAX2, + .quirks = FELIX_MAC_QUIRKS, .num_mact_rows = 2048, .num_ports = 10, .num_tx_queues = OCELOT_NUM_TC, From patchwork Sat Jan 29 22:02:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 1586296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=inadvantage.onmicrosoft.com header.i=@inadvantage.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-inadvantage-onmicrosoft-com header.b=ckf+tLWL; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JmSxf5DvTz9sPC for ; Sun, 30 Jan 2022 09:03:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353388AbiA2WC7 (ORCPT ); Sat, 29 Jan 2022 17:02:59 -0500 Received: from mail-dm3nam07on2115.outbound.protection.outlook.com ([40.107.95.115]:64192 "EHLO NAM02-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1353320AbiA2WCt (ORCPT ); Sat, 29 Jan 2022 17:02:49 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=j3oSsh8THE6lJsTe1vq8n20SPyzyyYj2foU+xgLro09k2wxFqx2lUnwKS7ZQqkQeqHrbMnWLSYlSc8tPQAyYXl3d239wRPpTUektoIhB2pVfwzi63Y850dMxMy+I8RN2AE/Yw6vV4zCXX3zmW1WnuoNaSmrRbjPL052zA8K7fHGqZ1ng8pRtXubHKROI1OdfY5nS8QvTkdGkEwabvY5TBc7uzq1LE+dHzDaLw7OWXoJ0ox5ZvKvXFaR3qxbNcxInugJFL04Gu/5k8kz1i0NlfwAsoZ68jhLBtS3to73cM4D+He22R/zfec3/lMjygnGDwXu6FDEKEMmNZ67ePYrxew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+jBsLBxId7mR5rihhs3Mlgj8tXBRT9r6EaKHf+IhkeA=; b=KUUoECI7mL8cHPPSC0bZgFMlfc1rQFWSSqvE7fxsIfYEpXpuLMxL/uAVWQceL+0ZebTWl801Apw28tg/jJ5o2MumlecsTk+SX/+3hi7EX6F7wB9LoFVoSKlyCwnn1V2r609F1c0vInwQqYFklwoUHrzNx967QGnEZf73XccBp2b8Lg7bgEWjkM7mftgUd+HEm+B5qHbE9PkbsgaSAwaFUf5HFJftBmR6x28Scf1EG7nMieejX5ONvexLBUJLG+GjmumpzHqQjgzHpMR3NPw4MS50/h510a1E6LmDXgNR+2bD9XSURWZeoxveKhiwSK6dZ8OQYuVctKq84xbSWWxfMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=inadvantage.onmicrosoft.com; s=selector2-inadvantage-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+jBsLBxId7mR5rihhs3Mlgj8tXBRT9r6EaKHf+IhkeA=; b=ckf+tLWLRXpdVhMOM0HrXgsxSiMjSNW1mi6ls94YCu0eaQuGcYPgwVPgQ4qhWkTOw8OwZoCSOGdaIkYhzXjB41llDXptsxhUnRbmHGC2FUhbEqg62ZOeCLdmRwFzbdslNPDcfFc6eIOrsKC66KXywCoNhQf3WpbHWxiMsbovjbI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=in-advantage.com; Received: from MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) by BYAPR10MB2968.namprd10.prod.outlook.com (2603:10b6:a03:85::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4930.18; Sat, 29 Jan 2022 22:02:46 +0000 Received: from MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f]) by MWHPR1001MB2351.namprd10.prod.outlook.com ([fe80::2d52:2a96:7e6c:460f%4]) with mapi id 15.20.4930.020; Sat, 29 Jan 2022 22:02:46 +0000 From: Colin Foster To: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Steen Hegelund , Lars Povlsen , Linus Walleij , Russell King , Heiner Kallweit , Jakub Kicinski , "David S. Miller" , Florian Fainelli , Vivien Didelot , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones , katie.morris@in-advantage.com Subject: [RFC v6 net-next 9/9] net: dsa: ocelot: add external ocelot switch control Date: Sat, 29 Jan 2022 14:02:21 -0800 Message-Id: <20220129220221.2823127-10-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220129220221.2823127-1-colin.foster@in-advantage.com> References: <20220129220221.2823127-1-colin.foster@in-advantage.com> X-ClientProxiedBy: CO1PR15CA0113.namprd15.prod.outlook.com (2603:10b6:101:21::33) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f15f9a1b-69cc-4ff7-0cdf-08d9e37314bf X-MS-TrafficTypeDiagnostic: BYAPR10MB2968:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Oss/mGPDhr8LrTpeRjqBPUzvBukWIqnSIlnFxRLOrW8sdDTpwgvRvbLqnIiFW/lmZ1GaZWX+pp2OneZ2uV/Uy4CazSSDYyEMhlTazmMhqn2qM5qSTfaJOnmICpIgtr1LbecIMKsbEKS/zK6U7mkrzBDA4bT+rAH1wl+BYOnGpdt1CxF8U03hHbezHzc2XTUGIXu//V717XrCkV/zKO+ovSCIvi/HNgmHimxRzc1L8FnRh6du72d5D+zKxIgJc7q6JOE/pUXyV1/xxNlH/T9c78NVoOejTwdf90f767qY7p5YnFSJMnyAVbneRGCULJInvfUPfWfcopMcHIb4IpejmnWu0WaRpLvrPzKbzKyR6S8j7vjGXDSea4NCwZf4JajLBZVy6AaWRAsne+jUMx53DfyX2SK582t6ezwdy7b5uCtkSLZ1tQjjHIbwBj0KoYVaRCl0VsVxLF67xHM2rYeLhcUt6yeA1vxIuh0jMNTEYqvsc0o9canaEQ9sIPxO/PqhvWD9B2KruLkGpvB5DVvXhmWSxs/5whMUgxFCuazbC4C8cm/v+ryb0MHHK7Ial9zkeA7EA0hhSgPGmyur3VsNe3mqwSVgCExPgwgFb6djmEyh7q/F8qNuEyl8XTZCtSZVnU9/yn56ariBuC5wKFyX8PsM+h21nn6p6Abr6na0Al2+PIpNHGvPfH7Y3K5yqNedSb2Vwko/zQe2YZ0D/qcenQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(136003)(376002)(346002)(42606007)(396003)(39830400003)(366004)(186003)(508600001)(5660300002)(6486002)(1076003)(86362001)(66946007)(8676002)(66476007)(26005)(4326008)(66556008)(8936002)(7416002)(107886003)(6506007)(38350700002)(6512007)(2906002)(30864003)(44832011)(6666004)(2616005)(52116002)(38100700002)(83380400001)(316002)(36756003)(54906003)(20210929001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nAXFlq78aSVXmQennnxClZlbQ416poxp/frdsgsQ8zmzlxDKJVLOSIKdJkH2+dO6iyd0aJ8njubOqBl8pOwi63T6woRcpjeEp2gIxhLESFstFMxbu9SsP+Lq5Zzukj+L+BUEGsfplhXGUS+QiKojkad8kb3AIL2WuN8yREOHEs2iJ+Z/ry+AHUEu5dkhjP4NMK9iLHoXCz5rKS2ggLj+gmbwd9BkzEZ50mgN2AN+VfEbcli+PwOEVu/qlMPPUAUYzXn56h4ijQc59rmaZmIt6ziQZOLcFG/jIz+wugaxOVVELGgG5desqIrmQubNpnyB9psqCbMzb1X5UvL7LixSc0diNTdXmCbraZ50Yg15plmSYKvLlABDAsHlrYKrXLfm9FqHR7RYHgRgGqh7wrTpAIfWw+BSFeq48YXRsHTxWkjjq8ujslsaKlrnXiM4kTvxuQj4ytaOrW2ee0Ys0hksEZOu/HxFOr2DChw3XsnAe7harVxx6u+VTbQ5ZwgDAyvtxv1EsCD27lU/J8CNfcApHeMWUcDS2pN+0Axk5YiugVd3EA9Xr7fmhychYvROZ6jeqnihK0doiubNPi7Cpm0xmBHpfYTJcT/sr55Q0m3LPr0nkzyxThdJ6E+myXUV7JZ4rYqziftstlETtwAMQbMFDIFnTNk7QmqI75KG5QhW1Bgnz+DgRU3VqByfxBW4ovqMC9IZqpWJtpEU6J68NmMiYyUidPAKt/VWcQ6AROSeAWlL7N/zVRuKVZjvVW8T63nfl3MHTrKDA31tBzuatMUqokL0fyGN9BeWbhO1lxus/qcYvMv9KMcA37d6VSP03gwcowb3xoQBDtoNKzIOGJitdrkexrSpaPr1+5H8Wmzczx9/neJugZKEvmtLdojaLr7m7i+AzY9SQB4bOuXOBPJ/o48yvlmQr3P7XvxD9ECqTQmG/flfE3QxeGifNPzoZvKhilnpiJImi/JIgmg5Dn7Bd8qws6a30GQCHqIqULqQKiOW30161VnCgpeThn+2cIpfaZ0Z6ts3q5PXqBXgmcwxDdmlW39AWuu0XS2/uUr+ICH4+TJC9+VuizT0kBmW67Gc8j3YugUionZOOdcfttaGTyh2jKwsZxD1/jP10RtgSod8qrC3V6hixYyvDC4Nl/r0Mx+IgDgJoYsq7RW/rjyg2boANC1fGYMB+/EgCeXgZaAjimlSJ9MCAtj1274IuyCFRzBjVYL+aGzP4pVGHmF7UfKTvGY6wtjweq+1jN0DSqjtlWEx7JT6PVycO0+hWQNDy7FES1XdoTfqwdMym7xEXSYXKKROFgeFnOxwesI1F8RxvFzeavb51pQA+U3QWbDCjhn7lZm5ljFGQsFImhg5g7XBbCzUycOblzw9MCfwDEdNXgnjOXJQwe9mS2oK3CzX+I0kyWjYIpiRWi3eg6J0pxG4br6c3W2bQpyUzVRtUjxagnHTuBcBGSGZYvq7cBG64a/6/pfOQTB0dr59MwhDbjiky6KxCHQDksGTEu/1bSnlq97L+ko6D+OC3kim4cVRWvx1KXD336VgV9nu3Dqzg7CsVUVnG5TXkfuG+OhzqJvXSun3x5fOx8FGrSGFo7eF9oijsIvX2TtPGY/VpGSrBdsc0mda0YWQuu4Jylsa8OQAwXZq/g9SUTIpLAjI5BQF3VAVGFaF4T7QVvYEnYwmffb3I3Lw4jboBKtqQfxei+s= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: f15f9a1b-69cc-4ff7-0cdf-08d9e37314bf X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2022 22:02:46.0632 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: thVyjXSDjb7LbfL6GeRunIB8lLgnRmSl1reJuMMAP+pWb+ePcYVnzEM6YqU/GpdPnRfJI36uTw4Am9DH9/QB0qhLh2foR01F8m2WG8DJeLQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR10MB2968 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add control of an external VSC7512 chip by way of the ocelot-mfd interface. Currently the four copper phy ports are fully functional. Communication to external phys is also functional, but the SGMII / QSGMII interfaces are currently non-functional. Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 4 + drivers/net/dsa/ocelot/Kconfig | 14 + drivers/net/dsa/ocelot/Makefile | 5 + drivers/net/dsa/ocelot/ocelot_ext.c | 681 ++++++++++++++++++++++++++++ include/soc/mscc/ocelot.h | 2 + 5 files changed, 706 insertions(+) create mode 100644 drivers/net/dsa/ocelot/ocelot_ext.c diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 590489481b8c..17a77d618e92 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -122,6 +122,10 @@ static const struct mfd_cell vsc7512_devs[] = { .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), .resources = vsc7512_miim1_resources, }, + { + .name = "ocelot-ext-switch", + .of_compatible = "mscc,vsc7512-ext-switch", + }, }; int ocelot_core_init(struct ocelot_core *core) diff --git a/drivers/net/dsa/ocelot/Kconfig b/drivers/net/dsa/ocelot/Kconfig index 220b0b027b55..f40b2c7171ad 100644 --- a/drivers/net/dsa/ocelot/Kconfig +++ b/drivers/net/dsa/ocelot/Kconfig @@ -1,4 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_MSCC_OCELOT_EXT + tristate "Ocelot External Ethernet switch support" + depends on NET_DSA && SPI + depends on NET_VENDOR_MICROSEMI + select MDIO_MSCC_MIIM + select MFD_OCELOT_CORE + select MSCC_OCELOT_SWITCH_LIB + select NET_DSA_TAG_OCELOT_8021Q + select NET_DSA_TAG_OCELOT + help + This driver supports the VSC7511, VSC7512, VSC7513 and VSC7514 chips + when controlled through SPI. It can be used with the Microsemi dev + boards and an external CPU or custom hardware. + config NET_DSA_MSCC_FELIX tristate "Ocelot / Felix Ethernet switch support" depends on NET_DSA && PCI diff --git a/drivers/net/dsa/ocelot/Makefile b/drivers/net/dsa/ocelot/Makefile index f6dd131e7491..d7f3f5a4461c 100644 --- a/drivers/net/dsa/ocelot/Makefile +++ b/drivers/net/dsa/ocelot/Makefile @@ -1,11 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_NET_DSA_MSCC_FELIX) += mscc_felix.o +obj-$(CONFIG_NET_DSA_MSCC_OCELOT_EXT) += mscc_ocelot_ext.o obj-$(CONFIG_NET_DSA_MSCC_SEVILLE) += mscc_seville.o mscc_felix-objs := \ felix.o \ felix_vsc9959.o +mscc_ocelot_ext-objs := \ + felix.o \ + ocelot_ext.o + mscc_seville-objs := \ felix.o \ seville_vsc9953.o diff --git a/drivers/net/dsa/ocelot/ocelot_ext.c b/drivers/net/dsa/ocelot/ocelot_ext.c new file mode 100644 index 000000000000..6fdff016673e --- /dev/null +++ b/drivers/net/dsa/ocelot/ocelot_ext.c @@ -0,0 +1,681 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2021 Innovative Advantage Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "felix.h" + +#define VSC7512_NUM_PORTS 11 + +#define OCELOT_SPI_PORT_MODE_INTERNAL (1 << 0) +#define OCELOT_SPI_PORT_MODE_SGMII (1 << 1) +#define OCELOT_SPI_PORT_MODE_QSGMII (1 << 2) + +const u32 vsc7512_port_modes[VSC7512_NUM_PORTS] = { + OCELOT_SPI_PORT_MODE_INTERNAL, + OCELOT_SPI_PORT_MODE_INTERNAL, + OCELOT_SPI_PORT_MODE_INTERNAL, + OCELOT_SPI_PORT_MODE_INTERNAL, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, + OCELOT_SPI_PORT_MODE_SGMII, + OCELOT_SPI_PORT_MODE_SGMII | OCELOT_SPI_PORT_MODE_QSGMII, +}; + +struct ocelot_ext_data { + struct felix felix; + const u32 *port_modes; +}; + +static const u32 vsc7512_gcb_regmap[] = { + REG(GCB_SOFT_RST, 0x0008), + REG(GCB_MIIM_MII_STATUS, 0x009c), + REG(GCB_PHY_PHY_CFG, 0x00f0), + REG(GCB_PHY_PHY_STAT, 0x00f4), +}; + +static const u32 *vsc7512_regmap[TARGET_MAX] = { + [ANA] = vsc7514_ana_regmap, + [QS] = vsc7514_qs_regmap, + [QSYS] = vsc7514_qsys_regmap, + [REW] = vsc7514_rew_regmap, + [SYS] = vsc7514_sys_regmap, + [S0] = vsc7514_vcap_regmap, + [S1] = vsc7514_vcap_regmap, + [S2] = vsc7514_vcap_regmap, + [PTP] = vsc7514_ptp_regmap, + [GCB] = vsc7512_gcb_regmap, + [DEV_GMII] = vsc7514_dev_gmii_regmap, +}; + +#define VSC7512_BYTE_ORDER_LE 0x00000000 +#define VSC7512_BYTE_ORDER_BE 0x81818181 +#define VSC7512_BIT_ORDER_MSB 0x00000000 +#define VSC7512_BIT_ORDER_LSB 0x42424242 + +static struct ocelot_ext_data *felix_to_ocelot_ext(struct felix *felix) +{ + return container_of(felix, struct ocelot_ext_data, felix); +} + +static struct ocelot_ext_data *ocelot_to_ocelot_ext(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + + return felix_to_ocelot_ext(felix); +} + +static void ocelot_ext_reset_phys(struct ocelot *ocelot) +{ + ocelot_write(ocelot, 0, GCB_PHY_PHY_CFG); + ocelot_write(ocelot, 0x1ff, GCB_PHY_PHY_CFG); + mdelay(500); +} + +static int ocelot_ext_reset(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct device *dev = ocelot->dev; + struct device_node *mdio_node; + int retries = 100; + int err, val; + + ocelot_ext_reset_phys(ocelot); + + mdio_node = of_get_child_by_name(dev->of_node, "mdio"); + if (!mdio_node) + dev_info(ocelot->dev, + "mdio children not found in device tree\n"); + + err = of_mdiobus_register(felix->imdio, mdio_node); + if (err) { + dev_err(ocelot->dev, "error registering MDIO bus\n"); + return err; + } + + felix->ds->slave_mii_bus = felix->imdio; + + /* We might need to reset the switch core here, if that is possible */ + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], 1); + if (err) + return err; + + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_MEM_ENA], 1); + if (err) + return err; + + do { + msleep(1); + regmap_field_read(ocelot->regfields[SYS_RESET_CFG_MEM_INIT], + &val); + } while (val && --retries); + + if (!retries) + return -ETIMEDOUT; + + err = regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); + + return err; +} + +static u32 ocelot_offset_from_reg_base(struct ocelot *ocelot, u32 target, + u32 reg) +{ + return ocelot->map[target][reg & REG_MASK]; +} + +static const struct ocelot_ops vsc7512_ops = { + .reset = ocelot_ext_reset, + .wm_enc = ocelot_wm_enc, + .wm_dec = ocelot_wm_dec, + .wm_stat = ocelot_wm_stat, + .port_to_netdev = felix_port_to_netdev, + .netdev_to_port = felix_netdev_to_port, +}; + +static const struct resource vsc7512_target_io_res[TARGET_MAX] = { + [ANA] = { + .start = 0x71880000, + .end = 0x7188ffff, + .name = "ana", + }, + [QS] = { + .start = 0x71080000, + .end = 0x710800ff, + .name = "qs", + }, + [QSYS] = { + .start = 0x71800000, + .end = 0x719fffff, + .name = "qsys", + }, + [REW] = { + .start = 0x71030000, + .end = 0x7103ffff, + .name = "rew", + }, + [SYS] = { + .start = 0x71010000, + .end = 0x7101ffff, + .name = "sys", + }, + [S0] = { + .start = 0x71040000, + .end = 0x710403ff, + .name = "s0", + }, + [S1] = { + .start = 0x71050000, + .end = 0x710503ff, + .name = "s1", + }, + [S2] = { + .start = 0x71060000, + .end = 0x710603ff, + .name = "s2", + }, + [GCB] = { + .start = 0x71070000, + .end = 0x7107022b, + .name = "devcpu_gcb", + }, +}; + +static const struct resource vsc7512_port_io_res[] = { + { + .start = 0x711e0000, + .end = 0x711effff, + .name = "port0", + }, + { + .start = 0x711f0000, + .end = 0x711fffff, + .name = "port1", + }, + { + .start = 0x71200000, + .end = 0x7120ffff, + .name = "port2", + }, + { + .start = 0x71210000, + .end = 0x7121ffff, + .name = "port3", + }, + { + .start = 0x71220000, + .end = 0x7122ffff, + .name = "port4", + }, + { + .start = 0x71230000, + .end = 0x7123ffff, + .name = "port5", + }, + { + .start = 0x71240000, + .end = 0x7124ffff, + .name = "port6", + }, + { + .start = 0x71250000, + .end = 0x7125ffff, + .name = "port7", + }, + { + .start = 0x71260000, + .end = 0x7126ffff, + .name = "port8", + }, + { + .start = 0x71270000, + .end = 0x7127ffff, + .name = "port9", + }, + { + .start = 0x71280000, + .end = 0x7128ffff, + .name = "port10", + }, +}; + +static const struct reg_field vsc7512_regfields[REGFIELD_MAX] = { + [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), + [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), + [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), + [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), + [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), + [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), + [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), + [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), + [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), + [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), + [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), + [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), + [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), + [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), + [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), + [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), + [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), + [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), + [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), + [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), + [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), + [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), + [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), + [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), + [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), + [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), + [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), + [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), + [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), + [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), + [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), + [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), + [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), + [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 1, 1), + [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), + [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), + [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), + [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), + [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), + [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), + [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), + /* Replicated per number of ports (12), register size 4 per port */ + [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), + [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), + [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), + [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), + [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), + [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), + [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), + [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), + [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), + [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), + [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), + [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), +}; + +static const struct ocelot_stat_layout vsc7512_stats_layout[] = { + { .offset = 0x00, .name = "rx_octets", }, + { .offset = 0x01, .name = "rx_unicast", }, + { .offset = 0x02, .name = "rx_multicast", }, + { .offset = 0x03, .name = "rx_broadcast", }, + { .offset = 0x04, .name = "rx_shorts", }, + { .offset = 0x05, .name = "rx_fragments", }, + { .offset = 0x06, .name = "rx_jabbers", }, + { .offset = 0x07, .name = "rx_crc_align_errs", }, + { .offset = 0x08, .name = "rx_sym_errs", }, + { .offset = 0x09, .name = "rx_frames_below_65_octets", }, + { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, + { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, + { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, + { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, + { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, + { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, + { .offset = 0x10, .name = "rx_pause", }, + { .offset = 0x11, .name = "rx_control", }, + { .offset = 0x12, .name = "rx_longs", }, + { .offset = 0x13, .name = "rx_classified_drops", }, + { .offset = 0x14, .name = "rx_red_prio_0", }, + { .offset = 0x15, .name = "rx_red_prio_1", }, + { .offset = 0x16, .name = "rx_red_prio_2", }, + { .offset = 0x17, .name = "rx_red_prio_3", }, + { .offset = 0x18, .name = "rx_red_prio_4", }, + { .offset = 0x19, .name = "rx_red_prio_5", }, + { .offset = 0x1A, .name = "rx_red_prio_6", }, + { .offset = 0x1B, .name = "rx_red_prio_7", }, + { .offset = 0x1C, .name = "rx_yellow_prio_0", }, + { .offset = 0x1D, .name = "rx_yellow_prio_1", }, + { .offset = 0x1E, .name = "rx_yellow_prio_2", }, + { .offset = 0x1F, .name = "rx_yellow_prio_3", }, + { .offset = 0x20, .name = "rx_yellow_prio_4", }, + { .offset = 0x21, .name = "rx_yellow_prio_5", }, + { .offset = 0x22, .name = "rx_yellow_prio_6", }, + { .offset = 0x23, .name = "rx_yellow_prio_7", }, + { .offset = 0x24, .name = "rx_green_prio_0", }, + { .offset = 0x25, .name = "rx_green_prio_1", }, + { .offset = 0x26, .name = "rx_green_prio_2", }, + { .offset = 0x27, .name = "rx_green_prio_3", }, + { .offset = 0x28, .name = "rx_green_prio_4", }, + { .offset = 0x29, .name = "rx_green_prio_5", }, + { .offset = 0x2A, .name = "rx_green_prio_6", }, + { .offset = 0x2B, .name = "rx_green_prio_7", }, + { .offset = 0x40, .name = "tx_octets", }, + { .offset = 0x41, .name = "tx_unicast", }, + { .offset = 0x42, .name = "tx_multicast", }, + { .offset = 0x43, .name = "tx_broadcast", }, + { .offset = 0x44, .name = "tx_collision", }, + { .offset = 0x45, .name = "tx_drops", }, + { .offset = 0x46, .name = "tx_pause", }, + { .offset = 0x47, .name = "tx_frames_below_65_octets", }, + { .offset = 0x48, .name = "tx_frames_65_to_127_octets", }, + { .offset = 0x49, .name = "tx_frames_128_255_octets", }, + { .offset = 0x4A, .name = "tx_frames_256_511_octets", }, + { .offset = 0x4B, .name = "tx_frames_512_1023_octets", }, + { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", }, + { .offset = 0x4D, .name = "tx_frames_over_1526_octets", }, + { .offset = 0x4E, .name = "tx_yellow_prio_0", }, + { .offset = 0x4F, .name = "tx_yellow_prio_1", }, + { .offset = 0x50, .name = "tx_yellow_prio_2", }, + { .offset = 0x51, .name = "tx_yellow_prio_3", }, + { .offset = 0x52, .name = "tx_yellow_prio_4", }, + { .offset = 0x53, .name = "tx_yellow_prio_5", }, + { .offset = 0x54, .name = "tx_yellow_prio_6", }, + { .offset = 0x55, .name = "tx_yellow_prio_7", }, + { .offset = 0x56, .name = "tx_green_prio_0", }, + { .offset = 0x57, .name = "tx_green_prio_1", }, + { .offset = 0x58, .name = "tx_green_prio_2", }, + { .offset = 0x59, .name = "tx_green_prio_3", }, + { .offset = 0x5A, .name = "tx_green_prio_4", }, + { .offset = 0x5B, .name = "tx_green_prio_5", }, + { .offset = 0x5C, .name = "tx_green_prio_6", }, + { .offset = 0x5D, .name = "tx_green_prio_7", }, + { .offset = 0x5E, .name = "tx_aged", }, + { .offset = 0x80, .name = "drop_local", }, + { .offset = 0x81, .name = "drop_tail", }, + { .offset = 0x82, .name = "drop_yellow_prio_0", }, + { .offset = 0x83, .name = "drop_yellow_prio_1", }, + { .offset = 0x84, .name = "drop_yellow_prio_2", }, + { .offset = 0x85, .name = "drop_yellow_prio_3", }, + { .offset = 0x86, .name = "drop_yellow_prio_4", }, + { .offset = 0x87, .name = "drop_yellow_prio_5", }, + { .offset = 0x88, .name = "drop_yellow_prio_6", }, + { .offset = 0x89, .name = "drop_yellow_prio_7", }, + { .offset = 0x8A, .name = "drop_green_prio_0", }, + { .offset = 0x8B, .name = "drop_green_prio_1", }, + { .offset = 0x8C, .name = "drop_green_prio_2", }, + { .offset = 0x8D, .name = "drop_green_prio_3", }, + { .offset = 0x8E, .name = "drop_green_prio_4", }, + { .offset = 0x8F, .name = "drop_green_prio_5", }, + { .offset = 0x90, .name = "drop_green_prio_6", }, + { .offset = 0x91, .name = "drop_green_prio_7", }, +}; + +static void vsc7512_phylink_validate(struct ocelot *ocelot, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct ocelot_port *ocelot_port = ocelot->ports[port]; + + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + if (state->interface != PHY_INTERFACE_MODE_NA && + state->interface != ocelot_port->phy_mode) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + return; + } + + phylink_set_port_modes(mask); + + phylink_set(mask, Pause); + phylink_set(mask, Autoneg); + phylink_set(mask, Asym_Pause); + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Full); + + bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int vsc7512_prevalidate_phy_mode(struct ocelot *ocelot, int port, + phy_interface_t phy_mode) +{ + struct ocelot_ext_data *ocelot_ext = ocelot_to_ocelot_ext(ocelot); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + if (ocelot_ext->port_modes[port] & + OCELOT_SPI_PORT_MODE_INTERNAL) + return 0; + return -EOPNOTSUPP; + case PHY_INTERFACE_MODE_SGMII: + if (ocelot_ext->port_modes[port] & OCELOT_SPI_PORT_MODE_SGMII) + return 0; + return -EOPNOTSUPP; + case PHY_INTERFACE_MODE_QSGMII: + if (ocelot_ext->port_modes[port] & OCELOT_SPI_PORT_MODE_QSGMII) + return 0; + return -EOPNOTSUPP; + default: + return -EOPNOTSUPP; + } +} + +static int vsc7512_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + return -EOPNOTSUPP; +} + +static struct vcap_props vsc7512_vcap_props[] = { + [VCAP_ES0] = { + .action_type_width = 0, + .action_table = { + [ES0_ACTION_TYPE_NORMAL] = { + .width = 73, + .count = 1, + }, + }, + .target = S0, + .keys = vsc7514_vcap_es0_keys, + .actions = vsc7514_vcap_es0_actions, + }, + [VCAP_IS1] = { + .action_type_width = 0, + .action_table = { + [IS1_ACTION_TYPE_NORMAL] = { + .width = 78, + .count = 4, + }, + }, + .target = S1, + .keys = vsc7514_vcap_is1_keys, + .actions = vsc7514_vcap_is1_actions, + }, + [VCAP_IS2] = { + .action_type_width = 1, + .action_table = { + [IS2_ACTION_TYPE_NORMAL] = { + .width = 49, + .count = 2, + }, + [IS2_ACTION_TYPE_SMAC_SIP] = { + .width = 6, + .count = 4, + }, + }, + .target = S2, + .keys = vsc7514_vcap_is2_keys, + .actions = vsc7514_vcap_is2_actions, + }, +}; + +static struct regmap *vsc7512_regmap_init(struct ocelot *ocelot, + struct resource *res) +{ + struct device *dev = ocelot->dev; + struct regmap *regmap; + + regmap = ocelot_get_regmap_from_resource(dev->parent, res); + if (IS_ERR(regmap)) + return ERR_CAST(regmap); + + return regmap; +} + +static int vsc7512_mdio_bus_alloc(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct device *dev = ocelot->dev; + u32 mii_offset, phy_offset; + struct mii_bus *bus; + int err; + + mii_offset = ocelot_offset_from_reg_base(ocelot, GCB, + GCB_MIIM_MII_STATUS); + + phy_offset = ocelot_offset_from_reg_base(ocelot, GCB, GCB_PHY_PHY_CFG); + + err = mscc_miim_setup(dev, &bus, "ocelot_ext MDIO bus", + ocelot->targets[GCB], mii_offset, + ocelot->targets[GCB], phy_offset); + if (err) { + dev_err(dev, "failed to setup MDIO bus\n"); + return err; + } + + felix->imdio = bus; + + return err; +} + + +static void vsc7512_mdio_bus_free(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + + if (felix->imdio) + mdiobus_unregister(felix->imdio); +} + +static const struct felix_info ocelot_ext_info = { + .target_io_res = vsc7512_target_io_res, + .port_io_res = vsc7512_port_io_res, + .regfields = vsc7512_regfields, + .map = vsc7512_regmap, + .ops = &vsc7512_ops, + .stats_layout = vsc7512_stats_layout, + .num_stats = ARRAY_SIZE(vsc7512_stats_layout), + .vcap = vsc7512_vcap_props, + .num_mact_rows = 1024, + .num_ports = VSC7512_NUM_PORTS, + .num_tx_queues = OCELOT_NUM_TC, + .mdio_bus_alloc = vsc7512_mdio_bus_alloc, + .mdio_bus_free = vsc7512_mdio_bus_free, + .phylink_validate = vsc7512_phylink_validate, + .prevalidate_phy_mode = vsc7512_prevalidate_phy_mode, + .port_setup_tc = vsc7512_port_setup_tc, + .init_regmap = vsc7512_regmap_init, +}; + +static int ocelot_ext_probe(struct platform_device *pdev) +{ + struct ocelot_ext_data *ocelot_ext; + struct dsa_switch *ds; + struct ocelot *ocelot; + struct felix *felix; + struct device *dev; + int err; + + dev = &pdev->dev; + + ocelot_ext = devm_kzalloc(dev, sizeof(struct ocelot_ext_data), + GFP_KERNEL); + + if (!ocelot_ext) + return -ENOMEM; + + dev_set_drvdata(dev, ocelot_ext); + + ocelot_ext->port_modes = vsc7512_port_modes; + felix = &ocelot_ext->felix; + + ocelot = &felix->ocelot; + ocelot->dev = dev; + + ocelot->num_flooding_pgids = 1; + + felix->info = &ocelot_ext_info; + + ds = kzalloc(sizeof(*ds), GFP_KERNEL); + if (!ds) { + err = -ENOMEM; + dev_err(dev, "Failed to allocate DSA switch\n"); + return err; + } + + ds->dev = dev; + ds->num_ports = felix->info->num_ports; + ds->num_tx_queues = felix->info->num_tx_queues; + + ds->ops = &felix_switch_ops; + ds->priv = ocelot; + felix->ds = ds; + felix->tag_proto = DSA_TAG_PROTO_OCELOT; + + err = dsa_register_switch(ds); + + if (err) { + dev_err(dev, "Failed to register DSA switch: %d\n", err); + goto err_register_ds; + } + + return 0; + +err_register_ds: + kfree(ds); + return err; +} + +static int ocelot_ext_remove(struct platform_device *pdev) +{ + struct ocelot_ext_data *ocelot_ext; + struct felix *felix; + + ocelot_ext = dev_get_drvdata(&pdev->dev); + felix = &ocelot_ext->felix; + + dsa_unregister_switch(felix->ds); + + kfree(felix->ds); + + devm_kfree(&pdev->dev, ocelot_ext); + + return 0; +} + +const struct of_device_id ocelot_ext_switch_of_match[] = { + { .compatible = "mscc,vsc7512-ext-switch" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ocelot_ext_switch_of_match); + +static struct platform_driver ocelot_ext_switch_driver = { + .driver = { + .name = "ocelot-ext-switch", + .of_match_table = of_match_ptr(ocelot_ext_switch_of_match), + }, + .probe = ocelot_ext_probe, + .remove = ocelot_ext_remove, +}; +module_platform_driver(ocelot_ext_switch_driver); + +MODULE_DESCRIPTION("External Ocelot Switch driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 8b8ebede5a01..62cd61d4142e 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -399,6 +399,8 @@ enum ocelot_reg { GCB_MIIM_MII_STATUS, GCB_MIIM_MII_CMD, GCB_MIIM_MII_DATA, + GCB_PHY_PHY_CFG, + GCB_PHY_PHY_STAT, DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, DEV_PORT_MISC, DEV_EVENTS,