From patchwork Thu Jan 27 15:46:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=GPWmK26o; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6ZJ39Bwz9t6g for ; Fri, 28 Jan 2022 04:11:34 +1100 (AEDT) Received: from localhost ([::1]:42502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD8J0-000373-9f for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 12:11:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6z2-0005mo-NX for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:48 -0500 Received: from [2a00:1450:4864:20::331] (port=38789 helo=mail-wm1-x331.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6z0-0008Ev-3m for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:48 -0500 Received: by mail-wm1-x331.google.com with SMTP id o30-20020a05600c511e00b0034f4c3186f4so6210733wms.3 for ; Thu, 27 Jan 2022 07:46:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZZJxnO0wXp3VlaW8QIoFJ6AD9P5ehX63O95QyB7R9Xw=; b=GPWmK26oRrRzo6qTxk1QnyLLJT4NOZ51/eaym8TtSnugj4hGzL90ExvfuzVc9g6u+f HrXACdgG3x9s3GHGKk8CbyemjfkS7+buruDKHg4tiHwujMWmwWagbBd0yth7bdLVndNd /H1Fmrcs0R3PCHv362NQL8bxgUGLeOuFTUAygmFUXaL1A3YPjFkeCHwmF/zNl5SpBnSn ojlNLnF582zccAm9AG0aluK5Iz03heLu5uKwJpSs6rrFPS+w5srepzXtsWO/2rs5HiFl H5PK4lyY6HjoTKkjrLBUtndHlj0/CEOaU0bZLHNXUTSbTkugLZ3M6igxI3ngvGn161Bs WYDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZZJxnO0wXp3VlaW8QIoFJ6AD9P5ehX63O95QyB7R9Xw=; b=L/ZOQ7uzIrv2FKuJizpataMvzsyOpbup946mWv3VncIRwvzJDRLzXgEYWloxqMa7ju PPUhHsWCx+mf08K79eVclwdk97/ANjvgWBrqxxXKykQMY9M8SxKd4FiBYiOMpM/UIpwq wuE2757sexdPRIpKWbOIQ/2Krh+7SRpv9eIa4pkJ2UbmKaAnBfPIg07jw7hNxwfgyU2K 3KuMYGBiqcIzeSZ63TrEOIGoAe+Y4sDoYhWVGaxXpcoVdEkeMyRvGoPHEDF7+HsscDC+ uzz2CfXJuPGMPP/2W3U+Mu7bk7qfNVy0AWAm6ZIiSQ5bYdTho2nltaBn7M7XvwxNGL+0 8wAw== X-Gm-Message-State: AOAM531DzqvPr31OWA0HAcifmOMEf24CaPdu2Oy1JZTwi5AgVG4TTWkH gXj7Xn/YxioK3IWCel6vxDY7OA== X-Google-Smtp-Source: ABdhPJz+jcWzgkOcpwEuwX2uDv1cWRhnotOCJ9gwLl4eUVfb2yWuBXVo6uX+YQFRBCClzjzFSiG5Gw== X-Received: by 2002:a05:600c:a4b:: with SMTP id c11mr12437091wmq.135.1643298404398; Thu, 27 Jan 2022 07:46:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/16] target/arm: make psci-conduit settable after realize Date: Thu, 27 Jan 2022 15:46:24 +0000 Message-Id: <20220127154639.2090164-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::331 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We want to allow the psci-conduit property to be set after realize, because the parts of the code which are best placed to decide if it's OK to enable QEMU's builtin PSCI emulation (the board code and the arm_load_kernel() function are distant from the code which creates and realizes CPUs (typically inside an SoC object's init and realize method) and run afterwards. Since the DEFINE_PROP_* macros don't have support for creating properties which can be changed after realize, change the property to be created with object_property_add_uint32_ptr(), which is what we already use in this function for creating settable-after-realize properties like init-svtor and init-nsvtor. Note that it doesn't conceptually make sense to change the setting of the property after the machine has been completely initialized, beacuse this would mean that the behaviour of the machine when first started would differ from its behaviour when the system is subsequently reset. (It would also require the underlying state to be migrated, which we don't do.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index cdbc4cdd012..5a9c02a2561 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1317,6 +1317,11 @@ void arm_cpu_post_init(Object *obj) OBJ_PROP_FLAG_READWRITE); } + /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ + object_property_add_uint32_ptr(obj, "psci-conduit", + &cpu->psci_conduit, + OBJ_PROP_FLAG_READWRITE); + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { @@ -1987,7 +1992,6 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) } static Property arm_cpu_properties[] = { - DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), From patchwork Thu Jan 27 15:46:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585182 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Cn44QfOn; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl5Q43v4Pz9t6h for ; Fri, 28 Jan 2022 03:19:24 +1100 (AEDT) Received: from localhost ([::1]:47388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD7UY-0005Vb-Bj for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 11:19:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6z2-0005nh-Us for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:48 -0500 Received: from [2a00:1450:4864:20::42e] (port=38415 helo=mail-wr1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6z1-0008F5-5y for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:48 -0500 Received: by mail-wr1-x42e.google.com with SMTP id c23so5576526wrb.5 for ; Thu, 27 Jan 2022 07:46:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1aqUKgcmvQE8aZsdzTIh/HJBOol3bJPDnt7wTDARukc=; b=Cn44QfOnJG+10CY0wnxF80pK+FJRySFh9/1bfa4BL5l2M+oH7ur0a+xftzVc7YNVjd u8uDJ64ZooHtrDZkWCJIGe7SmyjBHp4nIwiUpJKNuPlyWDeXJry1LUyAun4S8mN8A1+K ZwUxEcaZvI2P2NogO6KiRQWS+vzpdsIqphkuru6ZYE+tn1cOiRS/Yc+KOwcTJVnmhHZM 1UVmfDyN9yDt68K07b4L7NkGho+sZ3mMRIzx5/smGJktS/xG4d84dbBiJd/etTObsZSY NkcFFfr75gZQ62/DRguCgQ4d0a7zKLXBQaDW8DHp/vamIzTtE7CqWar/ZOJ5uDhHLPUs I3gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1aqUKgcmvQE8aZsdzTIh/HJBOol3bJPDnt7wTDARukc=; b=4PBD0gc+cZnN59RsLLmqB81HCI1bmDgOsHu1BI740Cp9/DVW2AYgIsXmhH1aNB9QVE ZGNvdpmseom4so/AN067cpKO2JRML0NMgAZdwN+bAcQbsGWi5IpA0hg1HSdW2M7zCumr VjrpcP8c+3KE0b3J8SzeCYcDpb7X+kSVZfRjetQinw+fbZ7bCAXdLyxf20B3XWGOGXNG iTT7TsZ3f8swTjPal01j5CzP72shHs3MtFZtz08KJunuLlQFpqaF4XjHA7PQN/242yQX jBHKhjMBj/UozJAqF5LuURNLSa8q0YGP1thbNvWA1G6VS8OsY9f04s0XDM3JlW42CSqJ YJ1Q== X-Gm-Message-State: AOAM533MOOaMpGpk98wJK/SbbwuCXpKvzsGevl3FIAJMluMPGcS3oHcM CXfZgu74WbxI8vGptS55rBan2g== X-Google-Smtp-Source: ABdhPJxzrJPJ6/lsmeC1NuTompfTb7puHVRrsVOltIrdK38AzUsm425C8PbOFc69wLOHr0O+0Wz3ew== X-Received: by 2002:adf:dfcf:: with SMTP id q15mr3516389wrn.276.1643298405897; Thu, 27 Jan 2022 07:46:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/16] cpu.c: Make start-powered-off settable after realize Date: Thu, 27 Jan 2022 15:46:25 +0000 Message-Id: <20220127154639.2090164-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The CPU object's start-powered-off property is currently only settable before the CPU object is realized. For arm machines this is awkward, because we would like to decide whether the CPU should be powered-off based on how we are booting the guest code, which is something done in the machine model code and in common code called by the machine model, which runs much later and in completely different parts of the codebase from the SoC object code that is responsible for creating and realizing the CPU objects. Allow start-powered-off to be set after realize. Since this isn't something that's supported by the DEFINE_PROP_* macros, we have to switch the property definition to use the object_class_property_add_bool() function. Note that it doesn't conceptually make sense to change the setting of the property after the machine has been completely initialized, beacuse this would mean that the behaviour of the machine when first started would differ from its behaviour when the system is subsequently reset. (It would also require the underlying state to be migrated, which we don't do.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- cpu.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/cpu.c b/cpu.c index 016bf06a1ae..3ea38aea707 100644 --- a/cpu.c +++ b/cpu.c @@ -196,13 +196,33 @@ static Property cpu_common_props[] = { DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, MemoryRegion *), #endif - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), DEFINE_PROP_END_OF_LIST(), }; +static bool cpu_get_start_powered_off(Object *obj, Error **errp) +{ + CPUState *cpu = CPU(obj); + return cpu->start_powered_off; +} + +static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) +{ + CPUState *cpu = CPU(obj); + cpu->start_powered_off = value; +} + void cpu_class_init_props(DeviceClass *dc) { + ObjectClass *oc = OBJECT_CLASS(dc); + device_class_set_props(dc, cpu_common_props); + /* + * We can't use DEFINE_PROP_BOOL in the Property array for this + * property, because we want this to be settable after realize. + */ + object_class_property_add_bool(oc, "start-powered-off", + cpu_get_start_powered_off, + cpu_set_start_powered_off); } void cpu_exec_initfn(CPUState *cpu) From patchwork Thu Jan 27 15:46:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585222 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=owOrx5Fc; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6600m4Gz9tk1 for ; Fri, 28 Jan 2022 03:50:32 +1100 (AEDT) Received: from localhost ([::1]:33710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD7yf-0002pX-Ol for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 11:50:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6z4-0005um-Nu for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:50 -0500 Received: from [2a00:1450:4864:20::430] (port=34541 helo=mail-wr1-x430.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6z2-0008FX-MC for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:50 -0500 Received: by mail-wr1-x430.google.com with SMTP id f17so5618857wrx.1 for ; Thu, 27 Jan 2022 07:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hqSSqW9mYLnln3gzM+pPhLBH+fYEcqnCz8mEiXgmBXs=; b=owOrx5FcfF+arn2fUABM8GImD2nGuHYE+8Whjp6gEmMTxtzfzUtL9REtCz7AG+PX0I 2QHJ95biicYSYnljURuWa0i7zpV9E59dA87NYUdh61Y6QaoaGn1/DMKSqQz0/HN1DyW0 4XBmEwsdl0SwF3tXaHCzRUEe9HYiiImb5T4nQ5YWt+PWtovbVWozy3o4jxO1jfV8SJ0+ B6EJULnXqDkTVpqULJDjbNg9oaTxT6QkS5wmWIxolqBM065eGpUe8buoPrdtp8/aiiCf jB/EtNkQmvCjCYsfqum7CZxdRrIgrerub9dYjqP9rPUQqFGZbO9tPmbbhASjCVQUJNel C7rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hqSSqW9mYLnln3gzM+pPhLBH+fYEcqnCz8mEiXgmBXs=; b=b1JLEa6PYSOS68Rery4epLdd7wquMBmZnOwTQjcBXgZ8Kwc1mbTuJIDjPpjy8rOFBG XQwnbaFYYQYv2L3vZc1eyoBz9Y/rzeIknJdkeguVQMhjDVoy5sN8waoxRgXt0TfK7Ibe LkkW7lEOT4jJPtg+Iys+GRY97vaf1uvsVDsQ8YMV2EKxANtkhI4fATzZaw/5+e220HLW KfkI+5bHItqe+grTm8wvqRN9zzE7oQA7M7l6LPkPgaxAesFjkyUK5SmlySjm9b+qLFUP TwctJjiJBM4iiY7AatATd1egzXNqQPdRB1O2Q+vkTpS+dacYxwDaLlf2fGsRctyZ3/s9 LSOg== X-Gm-Message-State: AOAM533ExxZQOnnY6G298VxXFTPk4PrHXwnz5kqG2vx20wViPog3mt9z comyPVeae6RpMqhDcRNhtFBBdQ== X-Google-Smtp-Source: ABdhPJxB2fCG4DsoJPBN2+ENoop6WWKnDluBXjbmj99puZ4B8NsE7j7NzdGcQrnfvX+NrXjJpVWKmg== X-Received: by 2002:a5d:47cf:: with SMTP id o15mr3463388wrc.577.1643298407303; Thu, 27 Jan 2022 07:46:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/16] hw/arm/boot: Support setting psci-conduit based on guest EL Date: Thu, 27 Jan 2022 15:46:26 +0000 Message-Id: <20220127154639.2090164-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::430 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Currently we expect board code to set the psci-conduit property on CPUs and ensure that secondary CPUs are created with the start-powered-off property set to false, if the board wishes to use QEMU's builtin PSCI emulation. This worked OK for the virt board where we first wanted to use it, because the virt board directly creates its CPUs and is in a reasonable position to set those properties. For other boards which model real hardware and use a separate SoC object, however, it is more awkward. Most PSCI-using boards just set the psci-conduit board unconditionally. This was never strictly speaking correct (because you would not be able to run EL3 guest firmware that itself provided the PSCI interface, as the QEMU implementation would overrule it), but mostly worked in practice because for non-PSCI SMC calls QEMU would emulate the SMC instruction as normal (by trapping to guest EL3). However, we would like to make our PSCI emulation follow the part of the SMCC specification that mandates that SMC calls with unknown function identifiers return a failure code, which means that all SMC calls will be handled by the PSCI code and the "emulate as normal" path will no longer be taken. We tried to implement that in commit 9fcd15b9193e81 ("arm: tcg: Adhere to SMCCC 1.3 section 5.2"), but this regressed attempts to run EL3 guest code on the affected boards: * mcimx6ul-evk, mcimx7d-sabre, orangepi, xlnx-zcu102 * for the case only of EL3 code loaded via -kernel (and not via -bios or -pflash), virt and xlnx-versal-virt so for the 7.0 release we reverted it (in commit 4825eaae4fdd56f). This commit provides a mechanism that boards can use to arrange that psci-conduit is set if running guest code at a low enough EL but not if it would be running at the same EL that the conduit implies that the QEMU PSCI implementation is using. (Later commits will convert individual board models to use this mechanism.) We do this by moving the setting of the psci-conduit and start-powered-off properties to arm_load_kernel(). Boards which want to potentially use emulated PSCI must set a psci_conduit field in the arm_boot_info struct to the type of conduit they want to use (SMC or HVC); arm_load_kernel() will then set the CPUs up accordingly if it is not going to start the guest code at the same or higher EL as the fake QEMU firmware would be at. Board/SoC code which uses this mechanism should no longer set the CPU psci-conduit property directly. It should only set the start-powered-off property for secondaries if EL3 guest firmware running bare metal expects that rather than the alternative "all CPUs start executing the firmware at once". Note that when calculating whether we are going to run guest code at EL3, we ignore the setting of arm_boot_info::secure_board_setup, which might cause us to run a stub bit of guest code at EL3 which does some board-specific setup before dropping to EL2 or EL1 to run the guest kernel. This is OK because only one board that enables PSCI sets secure_board_setup (the highbank board), and the stub code it writes will behave the same way whether the one SMC call it makes is handled by "emulate the SMC" or by "PSCI default returns an error code". So we can leave that stub code in place until after we've changed the PSCI default behaviour; at that point we will remove it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/boot.h | 10 +++++++++ hw/arm/boot.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index ce2b48b88bc..0bcb58babba 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -86,6 +86,16 @@ struct arm_boot_info { * the user it should implement this hook. */ void (*modify_dtb)(const struct arm_boot_info *info, void *fdt); + /* + * If a board wants to use the QEMU emulated-firmware PSCI support, + * it should set this to QEMU_PSCI_CONDUIT_HVC or QEMU_PSCI_CONDUIT_SMC + * as appropriate. arm_load_kernel() will set the psci-conduit and + * start-powered-off properties on the CPUs accordingly. + * Note that if the guest image is started at the same exception level + * as the conduit specifies calls should go to (eg guest firmware booted + * to EL3) then PSCI will not be enabled. + */ + int psci_conduit; /* Used internally by arm_boot.c */ int is_linux; hwaddr initrd_start; diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 399f8e837ce..327e449f831 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1299,6 +1299,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) { CPUState *cs; AddressSpace *as = arm_boot_address_space(cpu, info); + int boot_el; + CPUARMState *env = &cpu->env; /* * CPU objects (unlike devices) are not automatically reset on system @@ -1329,6 +1331,54 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) arm_setup_direct_kernel_boot(cpu, info); } + /* + * Disable the PSCI conduit if it is set up to target the same + * or a lower EL than the one we're going to start the guest code in. + * This logic needs to agree with the code in do_cpu_reset() which + * decides whether we're going to boot the guest in the highest + * supported exception level or in a lower one. + */ + + /* Boot into highest supported EL ... */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + boot_el = 3; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + boot_el = 2; + } else { + boot_el = 1; + } + /* ...except that if we're booting Linux we adjust the EL we boot into */ + if (info->is_linux && !info->secure_boot) { + boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1; + } + + if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) || + (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) { + info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; + } + + if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { + Object *cpuobj = OBJECT(cs); + + object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit, + &error_abort); + /* + * Secondary CPUs start in PSCI powered-down state. Like the + * code in do_cpu_reset(), we assume first_cpu is the primary + * CPU. + */ + if (cs != first_cpu) { + object_property_set_bool(cpuobj, "start-powered-off", true, + &error_abort); + } + } + } + + /* + * arm_load_dtb() may add a PSCI node so it must be called after we have + * decided whether to enable PSCI and set the psci-conduit CPU properties. + */ if (!info->skip_dtb_autoload && have_dtb(info)) { if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { exit(1); From patchwork Thu Jan 27 15:46:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585188 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=aO3YPA2F; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl5Vn4b0Jz9tB1 for ; Fri, 28 Jan 2022 03:23:28 +1100 (AEDT) Received: from localhost ([::1]:56102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD7YU-0003Fh-ME for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 11:23:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6z6-0005zu-2J for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:52 -0500 Received: from [2a00:1450:4864:20::32e] (port=37641 helo=mail-wm1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6z4-0008GY-7p for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:51 -0500 Received: by mail-wm1-x32e.google.com with SMTP id l12-20020a7bc34c000000b003467c58cbdfso6224470wmj.2 for ; Thu, 27 Jan 2022 07:46:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cob6w3lHJEyO4gfhiCk6AitKryZfSl3diXAcUqlKPB0=; b=aO3YPA2FVFGvD8nFLRYV5PLU2tra2CgjvvtuYX0lph2wEaQ0XqP53ebAyD4hDzgRg8 QBxM5/i+cOWfQ7G1Keik7Hufh6mbdvdUQ0krcF5zr694xSRmb4jeTFJGkG9jG4lPH75f VCiO1fLX4SlN60+KrXSdfmp1JbvIoZqdECWEzzODSMdSQD1/huykzkC7TjCsoDyGCSUx goE6hvOfOePaJLcGa2JJUbfzP6XLRoo8xryN/fyoAUBsQK8nUK8LPKPOZMucCtkOQ1Bh o9KMHBeg+sw59CHzLF5tDYCrr67c5VSPqMFsmqeOnEysXQhX/SyyX0e81h0a+FIkLFmV 6iLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cob6w3lHJEyO4gfhiCk6AitKryZfSl3diXAcUqlKPB0=; b=W10Qde6iA7LXE7Vge+vUIS/SnEwBManes/oJmrKOsvR4UQSM5MKUW5Dw9PPK0Z2Ysh og1G3zgLgZbh+IDqIUmcSdKx9ZgaV7FWsdtcxrwZg+uc0vKeZhXr5aF2PATr4Z0qwJ2g GR9W1KidpmmJBwG3DAcSUeuE9XApQoUFzVkqDlwja3AfN15iKWuGOEqx6DERnyuvagw9 vIvCQj4Ix15+6IJhJKPsTBJVPGbKGRNceazNxHPWmO9ZNZ17QhAAl23JNWEMQHesQsJu 9o7BI5RrC4NNCQnUtNhh4E1x3nEbZLP78hwYV2bp72BUXV502BHVTvDHuQyHxfT9iPw7 U0Ug== X-Gm-Message-State: AOAM532tB/qgSgw59fl0rPN3l1zaP6S9q5In1pSTvUtsCwuBbFfnyeV8 VmqtLu7Zjkvq3nO1eu4tNyoLXQ== X-Google-Smtp-Source: ABdhPJwwOUj3mBi3jqL5qRv5dq1/w/nIyepgKdqXs1AOzDjYW59kDE1OhRt/NLm1N/UoOatFaIUPBQ== X-Received: by 2002:a1c:f709:: with SMTP id v9mr3660276wmh.131.1643298408671; Thu, 27 Jan 2022 07:46:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/16] hw/arm: imx: Don't enable PSCI conduit when booting guest in EL3 Date: Thu, 27 Jan 2022 15:46:27 +0000 Message-Id: <20220127154639.2090164-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Change the iMX-SoC based boards to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit property on the CPU objects in the SoC code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with. This affects the mcimx6ul-evk and mcimx7d-sabre boards. Note that for the mcimx7d board, this means that when running guest code at EL3 there is currently no way to power on the secondary CPUs, because we do not currently have a model of the system reset controller module which should be used to do that for the imx7 SoC, only for the imx6 SoC. (Previously EL3 code which knew it was running on QEMU could use a PSCI call to do this.) This doesn't affect the imx6ul-evk board because it is uniprocessor. Signed-off-by: Peter Maydell Acked-by: Richard Henderson --- I don't have the i.mx7 manual to hand, so I'm partly making assumptions based on the i.mx6 behaviour. If somebody with the manual could double-check that it does indeed start up with the secondary CPUs powered down via the SRC that would be great. --- hw/arm/fsl-imx6ul.c | 2 -- hw/arm/fsl-imx7.c | 8 ++++---- hw/arm/mcimx6ul-evk.c | 1 + hw/arm/mcimx7d-sabre.c | 1 + 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 1d1a708dd97..f1897123294 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -166,8 +166,6 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) return; } - object_property_set_int(OBJECT(&s->cpu), "psci-conduit", - QEMU_PSCI_CONDUIT_SMC, &error_abort); qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); /* diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 149885f2b80..cc6fdb9373f 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -159,9 +159,6 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) for (i = 0; i < smp_cpus; i++) { o = OBJECT(&s->cpu[i]); - object_property_set_int(o, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, - &error_abort); - /* On uniprocessor, the CBAR is set to 0 */ if (smp_cpus > 1) { object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR, @@ -169,7 +166,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) } if (i) { - /* Secondary CPUs start in PSCI powered-down state */ + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ object_property_set_bool(o, "start-powered-off", true, &error_abort); } diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 28b4886f48b..8131518426a 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -35,6 +35,7 @@ static void mcimx6ul_evk_init(MachineState *machine) .board_id = -1, .ram_size = machine->ram_size, .nb_cpus = machine->smp.cpus, + .psci_conduit = QEMU_PSCI_CONDUIT_SMC, }; s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 50a5ecde31a..ba84fc21920 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -37,6 +37,7 @@ static void mcimx7d_sabre_init(MachineState *machine) .board_id = -1, .ram_size = machine->ram_size, .nb_cpus = machine->smp.cpus, + .psci_conduit = QEMU_PSCI_CONDUIT_SMC, }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/16] hw/arm: allwinner: Don't enable PSCI conduit when booting guest in EL3 Date: Thu, 27 Jan 2022 15:46:28 +0000 Message-Id: <20220127154639.2090164-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::331 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Change the allwinner-h3 based board to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit property on the CPU objects in the SoC code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with. This affects the orangepi-pc board. This commit leaves the secondary CPUs in the powered-down state if the guest is booting at EL3, which is the same behaviour as before this commit. The secondaries can no longer be started by that EL3 code making a PSCI call but can still be started via the CPU Configuration Module registers (which we model in hw/misc/allwinner-cpucfg.c). Signed-off-by: Peter Maydell Reviewed-by: Niek Linnenbank Tested-by: Niek Linnenbank --- If anybody knows for definite that the secondaries should be powered-down at startup for guest firmware, we can delete the TODO. The allwinner-cpucfg.c code makes the reset value for the REG_CPU*_RST_CTRL registers "CPUX_RESET_RELEASED", which might suggest otherwise, but that could easily just be a QEMU error. --- hw/arm/allwinner-h3.c | 9 ++++----- hw/arm/orangepi.c | 1 + 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f9b7ed18711..f54aff6d2d2 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -235,11 +235,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) /* CPUs */ for (i = 0; i < AW_H3_NUM_CPUS; i++) { - /* Provide Power State Coordination Interface */ - qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", - QEMU_PSCI_CONDUIT_SMC); - - /* Disable secondary CPUs */ + /* + * Disable secondary CPUs. TODO: check whether this is what + * guest EL3 firmware would really expect. + */ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", i > 0); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index e7963822367..68fe9182414 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -105,6 +105,7 @@ static void orangepi_init(MachineState *machine) } orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM]; orangepi_binfo.ram_size = machine->ram_size; + orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); } From patchwork Thu Jan 27 15:46:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bfEhqLLi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6gl28DMz9tB1 for ; Fri, 28 Jan 2022 04:16:19 +1100 (AEDT) Received: from localhost ([::1]:52186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD8Nc-0001ZB-CY for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 12:16:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48932) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6z8-00066v-Ek for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:54 -0500 Received: from [2a00:1450:4864:20::432] (port=44676 helo=mail-wr1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6z6-0008Im-ON for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:46:54 -0500 Received: by mail-wr1-x432.google.com with SMTP id k18so5505429wrg.11 for ; Thu, 27 Jan 2022 07:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sHJ9nThESHzWZK/5l0R4RVfaxxtdAwJGigaCcT5eBLk=; b=bfEhqLLicqGanBmEIeQu/xw3rEURaJgj5UxM2th6wKmp/gYIQJSvm26qG4OyA/UbOI pj/g8kakC1Ed9z4N6W0hAY6q7kbeoFSifw9OqD7sx7+LUGD5rUz0/h2qyTy4mWHgBFkG QZAOiDrT2fYuu2n2nMZLBFoza6RjL/sd4cXi5EHm2f3LuFQRLKLOic0mwNM4eRbel02X 4mQvYhHNZ/qtQP0f1EU6y0qbNXkuibtr2HqYYZlJUn5tLsG5A10bSh+fR2B0N1cKScxy LX8B1WFPxHo2eyakUxe1wJWoNdTbXNnwJrcgVYhzV/1ivDAfX20a25f/D/AVUbDXms2Q 1GKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sHJ9nThESHzWZK/5l0R4RVfaxxtdAwJGigaCcT5eBLk=; b=61jQgaHPcsGn5IlYhxWM4KImnoegOZyCPCkYI9GUhQ0t2oB5RB72ecIfImx8QEIc/R HZcbjleV6t228FSPmbecOKDse5jCj56VryaQzJQwYqOjK3Vbj/NnesVumR/rqTKrQjWW b/omfZyQIEIBiX7ENtJ8ZJaXHafaLHhBm3EG4czebyqWom8625O6wkTynudqEv1pr4pt SI46NfE8DKH2KJhT8xi1p1sG/O4HMwvlrWWfg6bFunywjXXIV7o65qOdSpcpd9i1QxJH CexKYuPA7t1TwPeJjJ2epNNjD2yMT4CxiR3hWZenycyptnreNoG/5xbKFDj1Dsz6IpMX 0ezw== X-Gm-Message-State: AOAM530CZc4C/4wcKCBg2lsXl9uakbo0Ny8349k+NREBUcLxcbiBL+kl JkngFcJPlc4wHMyn2/xiwyOufw== X-Google-Smtp-Source: ABdhPJzbWg/xGsyVhdiJdwxTMSICOJDcNbPCPGufNpVVHdO8z0tpenATHzVFdhgAblyd/i8GYrWo7A== X-Received: by 2002:adf:e602:: with SMTP id p2mr3578645wrm.126.1643298411408; Thu, 27 Jan 2022 07:46:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/16] hw/arm/xlnx-zcu102: Don't enable PSCI conduit when booting guest in EL3 Date: Thu, 27 Jan 2022 15:46:29 +0000 Message-Id: <20220127154639.2090164-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Change the Xilinx ZynqMP-based board xlnx-zcu102 to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit property on the CPU objects in the SoC code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with. Note that this means that EL3 guest code will have no way to power on secondary cores, because we don't model any kind of power controller that does that on this SoC. Signed-off-by: Peter Maydell Acked-by: Richard Henderson --- Again, if anybody knows the real-hardware EL3 behaviour for CPUs that would be great. --- hw/arm/xlnx-zcu102.c | 1 + hw/arm/xlnx-zynqmp.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 45eb19ab3b7..4c84bb932aa 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -236,6 +236,7 @@ static void xlnx_zcu102_init(MachineState *machine) s->binfo.ram_size = ram_size; s->binfo.loader_start = 0; s->binfo.modify_dtb = zcu102_modify_dtb; + s->binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); } diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 1c52a575aad..17305fe7b76 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -215,7 +215,10 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); if (strcmp(name, boot_cpu)) { - /* Secondary CPUs start in PSCI powered-down state */ + /* + * Secondary CPUs start in powered-down state. + * TODO: check this is what EL3 firmware expects. + */ object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "start-powered-off", true, &error_abort); } else { @@ -435,12 +438,12 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) for (i = 0; i < num_apus; i++) { const char *name; - object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit", - QEMU_PSCI_CONDUIT_SMC, &error_abort); - name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); if (strcmp(name, boot_cpu)) { - /* Secondary CPUs start in PSCI powered-down state */ + /* + * Secondary CPUs start in powered-down state. + * TODO: check this is what EL3 firmware expects. + */ object_property_set_bool(OBJECT(&s->apu_cpu[i]), "start-powered-off", true, &error_abort); } else { From patchwork Thu Jan 27 15:46:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:52 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/16] hw/arm/versal: Let boot.c handle PSCI enablement Date: Thu, 27 Jan 2022 15:46:30 +0000 Message-Id: <20220127154639.2090164-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of setting the CPU psci-conduit and start-powered-off properties in the xlnx-versal-virt board code, set the arm_boot_info psci_conduit field so that the boot.c code can do it. This will fix a corner case where we were incorrectly enabling PSCI emulation when booting guest code into EL3 because it was an ELF file passed to -kernel. (EL3 guest code started via -bios, -pflash, or the generic loader was already being run with PSCI emulation disabled.) Note that EL3 guest code has no way to turn on the secondary CPUs because there's no emulated power controller, but this was already true for EL3 guest code run via -bios, -pflash, or the generic loader. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/xlnx-versal.h | 1 - hw/arm/xlnx-versal-virt.c | 6 ++++-- hw/arm/xlnx-versal.c | 5 +---- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 895ba12c61e..2de487564e4 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -89,7 +89,6 @@ struct Versal { struct { MemoryRegion *mr_ddr; - uint32_t psci_conduit; } cfg; }; diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 0c5edc898e1..1b25342501b 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -626,6 +626,9 @@ static void versal_virt_init(MachineState *machine) * When loading an OS, we turn on QEMU's PSCI implementation with SMC * as the PSCI conduit. When there's no -kernel, we assume the user * provides EL3 firmware to handle PSCI. + * + * Even if the user provides a kernel filename, arm_load_kernel() + * may suppress PSCI if it's going to boot that guest code at EL3. */ if (machine->kernel_filename) { psci_conduit = QEMU_PSCI_CONDUIT_SMC; @@ -635,8 +638,6 @@ static void versal_virt_init(MachineState *machine) TYPE_XLNX_VERSAL); object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram), &error_abort); - object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit, - &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); fdt_create(s); @@ -677,6 +678,7 @@ static void versal_virt_init(MachineState *machine) s->binfo.loader_start = 0x0; s->binfo.get_dtb = versal_virt_get_dtb; s->binfo.modify_dtb = versal_virt_modify_dtb; + s->binfo.psci_conduit = psci_conduit; if (machine->kernel_filename) { arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); } else { diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index b2705b6925e..458ba33815f 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -35,10 +35,8 @@ static void versal_create_apu_cpus(Versal *s) object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i], XLNX_VERSAL_ACPU_TYPE); obj = OBJECT(&s->fpd.apu.cpu[i]); - object_property_set_int(obj, "psci-conduit", s->cfg.psci_conduit, - &error_abort); if (i) { - /* Secondary CPUs start in PSCI powered-down state */ + /* Secondary CPUs start in powered-down state */ object_property_set_bool(obj, "start-powered-off", true, &error_abort); } @@ -481,7 +479,6 @@ static void versal_init(Object *obj) static Property versal_properties[] = { DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0), DEFINE_PROP_END_OF_LIST() }; From patchwork Thu Jan 27 15:46:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585241 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=VJyYlQLk; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:46:53 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/16] hw/arm/virt: Let boot.c handle PSCI enablement Date: Thu, 27 Jan 2022 15:46:31 +0000 Message-Id: <20220127154639.2090164-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42b (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of setting the CPU psci-conduit and start-powered-off properties in the virt board code, set the arm_boot_info psci_conduit field so that the boot.c code can do it. This will fix a corner case where we were incorrectly enabling PSCI emulation when booting guest code into EL3 because it was an ELF file passed to -kernel or to the generic loader. (EL3 guest code started via -bios or -pflash was already being run with PSCI emulation disabled.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/virt.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 141350bf215..398145a7180 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2088,17 +2088,6 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "has_el2", false, NULL); } - if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { - object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit, - NULL); - - /* Secondary CPUs start in PSCI powered-down state */ - if (n > 0) { - object_property_set_bool(cpuobj, "start-powered-off", true, - NULL); - } - } - if (vmc->kvm_no_adjvtime && object_property_find(cpuobj, "kvm-no-adjvtime")) { object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); @@ -2246,6 +2235,7 @@ static void machvirt_init(MachineState *machine) vms->bootinfo.get_dtb = machvirt_dtb; vms->bootinfo.skip_dtb_autoload = true; vms->bootinfo.firmware_loaded = firmware_loaded; + vms->bootinfo.psci_conduit = vms->psci_conduit; arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); vms->machine_done.notify = virt_machine_done; From patchwork Thu Jan 27 15:46:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=U5Whb9jA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl5fv1YMyz9t6h for ; Fri, 28 Jan 2022 03:30:31 +1100 (AEDT) Received: from localhost ([::1]:37740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD7fI-0001Yo-Ou for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 11:30:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6zS-0006me-I3 for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:14 -0500 Received: from [2a00:1450:4864:20::32c] (port=46791 helo=mail-wm1-x32c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6zH-0008OC-OE for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:14 -0500 Received: by mail-wm1-x32c.google.com with SMTP id c190-20020a1c9ac7000000b0035081bc722dso2142622wme.5 for ; Thu, 27 Jan 2022 07:47:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D6RWfoE5VlE7/bSxhmZNiy91yop7RGn51a8FgJXH+HA=; b=U5Whb9jAbbzMGeoPE6Mc/6dKUyD4wFt6o+4N5inscDPj1V+AwELhc5hpwuGy0dnVGI J4HXkFUZW8aOqlHqHQjl1E7mK3sBEegxYVwAtFsjM6o/BZtZynV4b1EldG1HkmxeRdsX ZHQHliLIhVliIZkM4dEtJTzs27Qx+u5rN97/NbcyiNvlS+U5ZNY9Wo/VSOm3vz2qs2vo qAj9WKyrEf0d694f+bu9LD1RC2qg70juSvnPSlluQEj9RMdZfg4ejT4n/pmHa6PoSgTU skd9IclywmGluxkLwNQ/Yvs/1/EUp5JBfjhHU3PU2+SeNMp0yaf2LWUXWGX+8KyhtNcJ 1emA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D6RWfoE5VlE7/bSxhmZNiy91yop7RGn51a8FgJXH+HA=; b=KQ0qyMlgrGVLyigR/lHZc8SOaHVLfk/HY1j+G8GF8l6Y3zDbTeWoUqyu1LaDJ58TKY 5hrxvo2sJ312TACC4qBTFA4JO3aPcb/VI96zu1tuvPHHA8eK9F6T7CWRPyZpNNzn0Yy/ PnWDg4FY/cWJYcLLyE1ktjbsTZsruJiTeoOhF0+EVb0tr79Yk+D8aNBFsW80r1iGy/pQ vLLUNZfjCWqLmzfvAjRJe4JJm83kc43YJRBmO+TgqU+QO/4js+klxRyTDi/T7begETqg e4MngdaEkqeK/CDNT5CK5oq2LvhpPVuGR9fSL06SQ7HFRuAG8qAUKEjhNHu6RtOo5cZe vnag== X-Gm-Message-State: AOAM533ZQ6km6u/S3Q/Ew2n+bUtbywx1AxXq/xcVgwkPvSeZKBFUFGhV 14Kcfzkk49wYbi61GNaW1D6QXw== X-Google-Smtp-Source: ABdhPJxnH55UMhtpZ+RG1OpRccLW2+g/jlBNhXv85/JBpEPvgsBceKDF0IUYNY3JYWNUpHHmMwWn9g== X-Received: by 2002:a05:600c:3d06:: with SMTP id bh6mr12232366wmb.87.1643298421833; Thu, 27 Jan 2022 07:47:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:01 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/16] hw/arm: highbank: For EL3 guests, don't enable PSCI, start all cores Date: Thu, 27 Jan 2022 15:46:32 +0000 Message-Id: <20220127154639.2090164-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Change the highbank/midway boards to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit and start-powered-off properties on the CPU objects in the board code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with (in which case it will set these properties). This means that when running guest code at EL3, all the cores will start execution at once on poweron. This matches the real hardware behaviour. (A brief description of the hardware boot process is in the u-boot documentation for these boards: https://u-boot.readthedocs.io/en/latest/board/highbank/highbank.html#boot-process -- in theory one might run the 'a9boot'/'a15boot' secure monitor code in QEMU, though we probably don't emulate enough for that.) This affects the highbank and midway boards. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/highbank.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 4210894d814..048f8550cb9 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -271,12 +271,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, &error_abort); - if (n) { - /* Secondary CPUs start in PSCI powered-down state */ - object_property_set_bool(cpuobj, "start-powered-off", true, - &error_abort); - } - if (object_property_find(cpuobj, "reset-cbar")) { object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, &error_abort); @@ -397,6 +391,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; highbank_binfo.write_board_setup = hb_write_board_setup; highbank_binfo.secure_board_setup = true; + highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); } From patchwork Thu Jan 27 15:46:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585230 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=IkeAIzHi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6GZ0Hcvz9sCD for ; Fri, 28 Jan 2022 03:57:58 +1100 (AEDT) Received: from localhost ([::1]:53492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD85r-0007y6-Qo for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 11:57:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6zT-0006oN-3V for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:16 -0500 Received: from [2a00:1450:4864:20::434] (port=46896 helo=mail-wr1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6zN-0008OP-PB for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:14 -0500 Received: by mail-wr1-x434.google.com with SMTP id l25so5501243wrb.13 for ; Thu, 27 Jan 2022 07:47:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Uro/87OmdJ9VYj+C+oygu8t7WovRg4G1f/DHiBXFt7o=; b=IkeAIzHivng1HQ/nQ+S4sRI/FdGS4WUcsT3ZPfGKELg/79p2zACQpbTe93SjwI2Eui hYiqU8+GxrXnFstorrGt03sfHelkLjvmLVNzyh1a/jSi3cwZm42++tq/lAStK55WOtGQ /NvwfOlgGCX8p+wjhsD5yUo3DOhmrsG1JkZWRYp4epB9xZCWzyUQp8YzyXtVQ8y/xbzI Ks07KgN71UooYqLYY+5sKx/0/+lk9YlcoQefRJVT20JrYst4y3NIrfhThZ7mZu9n0fVF WUJjh2YRGbhShrKMYEBWJaAvDVJfIphS8dvhEEbwVVsurX/9XdiXeDSGS/79748gTzie Meew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Uro/87OmdJ9VYj+C+oygu8t7WovRg4G1f/DHiBXFt7o=; b=TVZhzyf9VKCI6MZ3N3h/MUdD2uByPWcaqEq6d99OYCmUQw3u7IBXTKeaRkuyVle+Uw +MWNfO6ceu51NQOM5oLR0A38b7qDRipQke7ZOnocJSwJpqWYSJrHtB3UQWN5+RAKlYf1 e+U2EkVnkcRbcR1SGI9w9uXiMrGUa26jUU7z9WzHYfxYOzRb16LjK9cqD5sVpniX5yiE xsS40bCPWBy7dfchW/6UNI3puc8fwIbi44fQOx1UG8jHQuLyqmHi0v8oVH05/25rOyVd NF4Q+q2Hm9Ls9kK09QkoUC+UmOBGBbTdJ/dIwzszEI7OGSPErQ6SktqFrjhVENPzfMvn AAbg== X-Gm-Message-State: AOAM532UYkjhFI2igBBvl+/nHIoduq4VV67rHc3ad2weDEq6KYMPhxaB 23tHkbbLoVk3BIMrORCKWaP2Zw== X-Google-Smtp-Source: ABdhPJyp6HkHmPzDWR8YSwaOmwxkbjTrFwLsJefClygZi5d1vrpNSyDxmNxCmyXMcqLeM8yog47vYA== X-Received: by 2002:adf:e54e:: with SMTP id z14mr3593821wrm.490.1643298423277; Thu, 27 Jan 2022 07:47:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:02 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/16] Revert "Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"" Date: Thu, 27 Jan 2022 15:46:33 +0000 Message-Id: <20220127154639.2090164-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::434 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that we have arranged for all the affected board models to not enable the PSCI emulation if they are running guest code at EL3, we can revert commit 4825eaae4fdd56fba0f, thus reinstating commit 9fcd15b9193e819b, without bringing back the regressions that caused us to revert it. For clarity, here is the original commit message of 9fcd15b9193e819b: The SMCCC 1.3 spec section 5.2 says The Unknown SMC Function Identifier is a sign-extended value of (-1) that is returned in the R0, W0 or X0 registers. An implementation must return this error code when it receives: * An SMC or HVC call with an unknown Function Identifier * An SMC or HVC call for a removed Function Identifier * An SMC64/HVC64 call from AArch32 state To comply with these statements, let's always return -1 when we encounter an unknown HVC or SMC call. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/psci.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/target/arm/psci.c b/target/arm/psci.c index 6709e280133..b279c0b9a45 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -27,15 +27,13 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { - /* Return true if the r0/x0 value indicates a PSCI call and - * the exception type matches the configured PSCI conduit. This is - * called before the SMC/HVC instruction is executed, to decide whether - * we should treat it as a PSCI call or with the architecturally + /* + * Return true if the exception type matches the configured PSCI conduit. + * This is called before the SMC/HVC instruction is executed, to decide + * whether we should treat it as a PSCI call or with the architecturally * defined behaviour for an SMC or HVC (which might be UNDEF or trap * to EL2 or to EL3). */ - CPUARMState *env = &cpu->env; - uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; switch (excp_type) { case EXCP_HVC: @@ -52,27 +50,7 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) return false; } - switch (param) { - case QEMU_PSCI_0_2_FN_PSCI_VERSION: - case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: - case QEMU_PSCI_0_2_FN_AFFINITY_INFO: - case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: - case QEMU_PSCI_0_2_FN_SYSTEM_RESET: - case QEMU_PSCI_0_2_FN_SYSTEM_OFF: - case QEMU_PSCI_0_1_FN_CPU_ON: - case QEMU_PSCI_0_2_FN_CPU_ON: - case QEMU_PSCI_0_2_FN64_CPU_ON: - case QEMU_PSCI_0_1_FN_CPU_OFF: - case QEMU_PSCI_0_2_FN_CPU_OFF: - case QEMU_PSCI_0_1_FN_CPU_SUSPEND: - case QEMU_PSCI_0_2_FN_CPU_SUSPEND: - case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: - case QEMU_PSCI_0_1_FN_MIGRATE: - case QEMU_PSCI_0_2_FN_MIGRATE: - return true; - default: - return false; - } + return true; } void arm_handle_psci_call(ARMCPU *cpu) @@ -194,10 +172,9 @@ void arm_handle_psci_call(ARMCPU *cpu) break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: + default: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; - default: - g_assert_not_reached(); } err: From patchwork Thu Jan 27 15:46:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=sJ77hw0u; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:04 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/16] hw/arm/highbank: Drop use of secure_board_setup Date: Thu, 27 Jan 2022 15:46:34 +0000 Message-Id: <20220127154639.2090164-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::334 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Guest code on highbank may make non-PSCI SMC calls in order to enable/disable the L2x0 cache controller (see the Linux kernel's arch/arm/mach-highbank/highbank.c highbank_l2c310_write_sec() function). The ABI for this is documented in kernel commit 8e56130dcb as being borrowed from the OMAP44xx ROM. The OMAP44xx TRM documents this function ID as having no return value and potentially trashing all guest registers except SP and PC. For QEMU's purposes (where our L2x0 model is a stub and enabling or disabling it doesn't affect the guest behaviour) a simple "do nothing" SMC is fine. We currently implement this NOP behaviour using a little bit of Secure code we run before jumping to the guest kernel, which is written by arm_write_secure_board_setup_dummy_smc(). The code sets up a set of Secure vectors where the SMC entry point returns without doing anything. Now that the PSCI SMC emulation handles all SMC calls (setting r0 to an error code if the input r0 function identifier is not recognized), we can use that default behaviour as sufficient for the highbank cache controller call. (Because the guest code assumes r0 has no interesting value on exit it doesn't matter that we set it to the error code). We can therefore delete the highbank board code that sets secure_board_setup to true and writes the secure-code bootstub. (Note that because the OMAP44xx ABI puts function-identifiers in r12 and PSCI uses r0, we only avoid a clash because Linux's code happens to put the function-identifier in both registers. But this is true also when the kernel is running on real firmware that implements both ABIs as far as I can see.) This change fixes in passing booting on the 'midway' board model, which has been completely broken since we added support for Hyp mode to the Cortex-A15 CPU. When we did that boot.c was made to start running the guest code in Hyp mode; this includes the board_setup hook, which instantly UNDEFs because the NSACR is not accessible from Hyp. (Put another way, we never made the secure_board_setup hook support cope with Hyp mode.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/highbank.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 048f8550cb9..a21afd178d1 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -48,12 +48,6 @@ /* Board init. */ -static void hb_write_board_setup(ARMCPU *cpu, - const struct arm_boot_info *info) -{ - arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); -} - static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { int n; @@ -389,8 +383,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) highbank_binfo.write_secondary_boot = hb_write_secondary; highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; - highbank_binfo.write_board_setup = hb_write_board_setup; - highbank_binfo.secure_board_setup = true; highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); From patchwork Thu Jan 27 15:46:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=R8Kd09Av; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6xx1X2Jz9tB1 for ; Fri, 28 Jan 2022 04:28:37 +1100 (AEDT) Received: from localhost ([::1]:51314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD8ZW-0004Ng-VB for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 12:28:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49282) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6zV-0006vF-Ta for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:17 -0500 Received: from [2a00:1450:4864:20::435] (port=37845 helo=mail-wr1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6zQ-0008On-Us for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:17 -0500 Received: by mail-wr1-x435.google.com with SMTP id w11so5581168wra.4 for ; Thu, 27 Jan 2022 07:47:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1EKftSqPbTE2cj73sSgFhaPxNMghmo4WdRClxKMHw6I=; b=R8Kd09Avc8C/f1GhlVyDLp/WK5GWmU076hO7f/3B6cOBvVZvhRrCneKAR6g2zYuGvS hlkr5kz/maqF5hKngaL+e+CRbPlZqwRXXTHp47YeEIJiIT1icbzp3g/fQ2YUu+D7LRxr rFlZ9bG2FO1mFBB5v+8SmG3pXbyb/TOwaPtCw7uZyC5/SqoPzKaPOINNvvdMyXJ/94OA FRVN3vDbWrEPZXm25dAzUFCe40vI/fEBAvbqOX1dmmDKfZOiO5ph3Q14Vu9bPqTlm7K8 xIUehGthUDR7eJkfwAeTG8Fc9gz9+Tww0FlhSCiUgq5ET957njMHZdGWY7DhXMm9lO9S Unjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1EKftSqPbTE2cj73sSgFhaPxNMghmo4WdRClxKMHw6I=; b=1egFb713iCy5OXQTDh4mQhaYIfrwMhH7s7WPcRhnm3RY3OLcNdj8XX0Orzn0Wh5PQB MZYT3vc2Lirvb4eNdyVd6xDVn5UY/0U85/0KKO28szQJcbGhlxMW7hlkExCenSisNyML pwNQzWfYW0pRuadRUUNfzrDidDGc/Tkmo/JnynLO3sSig2x/s2LuT9zCEoKjurSvl3Lc oXQnpq9UbNW756snFY/XwUiPhVvYoHdyuj1Kt8kt6IIySqEDE2UDuSFKh/9ILkyGtzmu b/enY6HxT0X2adeGogP6K7wa+tTL6q8GqoM2pbnFgo4NPeCcPu3QubNzrr36nnk3jshi cUtQ== X-Gm-Message-State: AOAM530PPuIpKWWYwC3gb+sBd4c2Obc6JQ26AjMHSbqfpkrVLVFmeO1S 9+9GBMaeae7Pzt0bdN6n/9OvMg== X-Google-Smtp-Source: ABdhPJyJ0vDMQpM7k1jCNlNJSXlIBKZe/bE12lz7XpfvaQAA8V6L4dJPtZl1C/1L/CHCgTGmMHZTgQ== X-Received: by 2002:adf:f08b:: with SMTP id n11mr3525373wro.7.1643298426087; Thu, 27 Jan 2022 07:47:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:05 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/16] hw/arm/boot: Prevent setting both psci_conduit and secure_board_setup Date: Thu, 27 Jan 2022 15:46:35 +0000 Message-Id: <20220127154639.2090164-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::435 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that we have dealt with the one special case (highbank) that needed to set both psci_conduit and secure_board_setup, we don't need to allow that combination any more. It doesn't make sense in general, so use an assertion to ensure we don't add new boards that do it by accident without thinking through the consequences. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/boot.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 327e449f831..0424c178305 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1339,6 +1339,16 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) * supported exception level or in a lower one. */ + /* + * If PSCI is enabled, then SMC calls all go to the PSCI handler and + * are never emulated to trap into guest code. It therefore does not + * make sense for the board to have a setup code fragment that runs + * in Secure, because this will probably need to itself issue an SMC of some + * kind as part of its operation. + */ + assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED || + !info->secure_board_setup); + /* Boot into highest supported EL ... */ if (arm_feature(env, ARM_FEATURE_EL3)) { boot_el = 3; From patchwork Thu Jan 27 15:46:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=bPeg/HCv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6s20Fhzz9tB1 for ; Fri, 28 Jan 2022 04:24:22 +1100 (AEDT) Received: from localhost ([::1]:41508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD8VP-0005v4-0O for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 12:24:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6zU-0006qe-Jz for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:16 -0500 Received: from [2a00:1450:4864:20::32a] (port=43804 helo=mail-wm1-x32a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6zQ-0008Ov-Ud for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:16 -0500 Received: by mail-wm1-x32a.google.com with SMTP id r2-20020a1c2b02000000b0034f7b261169so2154806wmr.2 for ; Thu, 27 Jan 2022 07:47:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UTmaOnPlnPo5RWfu20ZKGcE5TEJnVANPMo+LxFYK5oU=; b=bPeg/HCvcVPeMYp3+ZtqeGiOCSj01rEpUK8y7awyBEwtEfPASPKIl32MOEt2dxmQvF xIAa0vWQVM5Wgf4Hy+TG5iLX0EIpWuKhPmiFRCD7iMQ4q9ipqqHq6PN1zgJEF9hJUiYq 4wAxR5QfEvyGkzhUIMtOqhwPzdbFRK3jBfuzGyiKvRVwxvnL0NkPHySp9NmO+AGrSd7q LTybbe87zroAnxFPRIunrbpqkJ28uX3QGfMcOvawT8/7fxUxfvfTXXMSDrIi7P8yQs/L Gt/SctidcegoqnvkcqNwpptOyH+QTlaP9J2d+Bpat6GDIlJwLqerVxyvTjSsZw1I59Gv 34AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UTmaOnPlnPo5RWfu20ZKGcE5TEJnVANPMo+LxFYK5oU=; b=l9cp9i5fbT2A+eVvB9ZFmA9pJg2rGimnB0ZEWBYWbhheh+PApoujBQIjt38Y1B3IsC 1q6cKVGR539ibE7p4dDv7mpv3AHbl3KPGxklaei2jNRpTdHI45+9kDnjI3yQoxnNwmBD sA7na6dZFPB8bXBZfkFqrss8OSxapgQWwkEf0p/lNW0tdV6kO3vIo/xwbuk+jaMk3iiw f88BPd/DWQWXukq5TFpp7lcXVad8JoDKxdcswHDLzi0ef9RMZjvlobXibGJBslQgQP8K omkXy3jYuf76qL30gGM19sh0dS3Xx6fBsC4ZgGbzS73svYHw2+oETmuCjWCkQmIdkYop rtFg== X-Gm-Message-State: AOAM532nhWMgFA1NMPrCDUAjcc63agy5wzODUdvNLVXXs8BrID9lD3ox qEHyNkRmul7Zp1R+Qn6/Hix6RA== X-Google-Smtp-Source: ABdhPJxVjdHo9Va+qcugwXbTiDtwd5eQ+TO6Mjec1qCFahpXnG/5+Jh7FViiGQVphS8y4qzBuEa0jQ== X-Received: by 2002:a1c:440a:: with SMTP id r10mr3830021wma.142.1643298427499; Thu, 27 Jan 2022 07:47:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:07 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/16] hw/arm/boot: Don't write secondary boot stub if using PSCI Date: Thu, 27 Jan 2022 15:46:36 +0000 Message-Id: <20220127154639.2090164-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If we're using PSCI emulation to start secondary CPUs, there is no point in writing the "secondary boot" stub code, because it will never be used -- secondary CPUs start powered-off, and when powered on are set to begin execution at the address specified by the guest's power-on PSCI call, not at the stub. Move the call to the hook that writes the secondary boot stub code so that we can do it only if we're starting a Linux kernel and not using PSCI. (None of the users of the hook care about the ordering of its call relative to anything else: they only use it to write a rom blob to guest memory.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/boot.h | 3 +++ hw/arm/boot.c | 35 ++++++++++++++++++++++++----------- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index 0bcb58babba..0cfc1c95c4e 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -70,6 +70,9 @@ struct arm_boot_info { * boot loader/boot ROM code, and secondary_cpu_reset_hook() should * perform any necessary CPU reset handling and set the PC for the * secondary CPUs to point at this boot blob. + * + * These hooks won't be called if secondary CPUs are booting via + * emulated PSCI (see psci_conduit below). */ void (*write_secondary_boot)(ARMCPU *cpu, const struct arm_boot_info *info); diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0424c178305..184628ce564 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -804,7 +804,7 @@ static void do_cpu_reset(void *opaque) set_kernel_args(info, as); } } - } else { + } else if (info->secondary_cpu_reset_hook) { info->secondary_cpu_reset_hook(cpu, info); } } @@ -1030,13 +1030,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, elf_machine = EM_ARM; } - if (!info->secondary_cpu_reset_hook) { - info->secondary_cpu_reset_hook = default_reset_secondary; - } - if (!info->write_secondary_boot) { - info->write_secondary_boot = default_write_secondary; - } - if (info->nb_cpus == 0) info->nb_cpus = 1; @@ -1216,9 +1209,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, write_bootloader("bootloader", info->loader_start, primary_loader, fixupcontext, as); - if (info->nb_cpus > 1) { - info->write_secondary_boot(cpu, info); - } if (info->write_board_setup) { info->write_board_setup(cpu, info); } @@ -1385,6 +1375,29 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) } } + if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && + info->is_linux && info->nb_cpus > 1) { + /* + * We're booting Linux but not using PSCI, so for SMP we need + * to write a custom secondary CPU boot loader stub, and arrange + * for the secondary CPU reset to make the accompanying initialization. + */ + if (!info->secondary_cpu_reset_hook) { + info->secondary_cpu_reset_hook = default_reset_secondary; + } + if (!info->write_secondary_boot) { + info->write_secondary_boot = default_write_secondary; + } + info->write_secondary_boot(cpu, info); + } else { + /* + * No secondary boot stub; don't use the reset hook that would + * have set the CPU up to call it + */ + info->write_secondary_boot = NULL; + info->secondary_cpu_reset_hook = NULL; + } + /* * arm_load_dtb() may add a PSCI node so it must be called after we have * decided whether to enable PSCI and set the psci-conduit CPU properties. From patchwork Thu Jan 27 15:46:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=EY26MJId; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jl6SQ0Jzdz9sCD for ; Fri, 28 Jan 2022 04:06:30 +1100 (AEDT) Received: from localhost ([::1]:35066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nD8E7-0006Vw-Rc for incoming@patchwork.ozlabs.org; Thu, 27 Jan 2022 12:06:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nD6zV-0006sy-Ch for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:17 -0500 Received: from [2a00:1450:4864:20::42c] (port=33605 helo=mail-wr1-x42c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nD6zQ-0008P5-Uh for qemu-devel@nongnu.org; Thu, 27 Jan 2022 10:47:16 -0500 Received: by mail-wr1-x42c.google.com with SMTP id e8so5674638wrc.0 for ; Thu, 27 Jan 2022 07:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DfIhd8MoTLGoeHrJIwdVILwXtofxSeMFrV8DeNXbnjE=; b=EY26MJIdltYrrTH7zWb5KlQlfxK1uEGig84kew7gyMawNfiVI4HqXNvTOcX/zK2uqh 6UAPpu9Klq/GwvJHfnTu8uwSFRFY5/o1yWTj1jfQXLmwvRtAs6ZYFBHOc8ox34xqbi1O E4YCp9fKIId4o7t4m7FwP/UyR4KHj73/+Ru/5UJH1yTfcWNktd1bSPEziaYBAOKi8m+W 1wYjUgG8SYM1jjK0qrC48c3+cm6X8lg8W/4Ts3q5t/WOwAzaYNpLSvQMdqqJG9V5lWUh +dQgFsqMSEbOU1vIq17u9J8fj2h2hgUqrPhIucEldRf3VAZLK28cEAo8/dMbYNdDmfdb +0uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DfIhd8MoTLGoeHrJIwdVILwXtofxSeMFrV8DeNXbnjE=; b=KIPrOBPmt0sKF+t5VSLCjFbza/2RZESCyyRXNZijjvMfplgF4opfhJzyaqQK1ZKj1L /ctA7D0sQmE+s/dC3NL+IUUQQaHkF5ky/L29sUDAi9pWnTv4BNkyk2TZ9/NUL9xhGeFI HoI0w6EZ1xlsVzUhzclkw3ix4yI3rF9xsTwLD9actQyXWozNDQaxKRuZa8OESH587ZU4 LU87HX1qNmKR6Omkjv7pJFTNuo/hHpOpwN0SoK02d7Nt8+aOBV3et+I5DHoyJnO2M9Al 5k5ClIP8gBRfu7UFKfgO16wT2UMTYBZ/2esgKTwWx+pkwFgt75lF/H9CU8VeNTGVvvL6 eZVA== X-Gm-Message-State: AOAM532FLB7a/uXcoaoS7KvosD7gx+iXBr7uSupzr/GbrmwIG6bF9Wfb hz5an40DNS3Yx3Avr0mncI66zQ== X-Google-Smtp-Source: ABdhPJwgiNxBOBZIaHiwgkB0Icec2fEHMF8VSDamoPFXdjlxlCGpWtWXTaoGnmUgvyspUdKbwNrwsA== X-Received: by 2002:adf:b610:: with SMTP id f16mr3530437wre.266.1643298428943; Thu, 27 Jan 2022 07:47:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:08 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/16] hw/arm/highbank: Drop unused secondary boot stub code Date: Thu, 27 Jan 2022 15:46:37 +0000 Message-Id: <20220127154639.2090164-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The highbank and midway board code includes boot-stub code for handling secondary CPU boot which keeps the secondaries in a pen until the primary writes to a known location with the address they should jump to. This code is never used, because the boards enable QEMU's PSCI emulation, so secondary CPUs are kept powered off until the PSCI call which turns them on, and then start execution from the address given by the guest in that PSCI call. Delete the unreachable code. (The code was wrong for midway in any case -- on the Cortex-A15 the GIC CPU interface registers are at a different offset from PERIPHBASE compared to the Cortex-A9, and the code baked-in the offsets for highbank's A9.) Note that this commit implicitly depends on the preceding "Don't write secondary boot stub if using PSCI" commit -- the default secondary-boot stub code overlaps with one of the highbank-specific bootcode rom blobs, so we must suppress the secondary-boot stub code entirely, not merely replace the highbank-specific version with the default. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/highbank.c | 56 ----------------------------------------------- 1 file changed, 56 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index a21afd178d1..da681b15708 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -48,60 +48,6 @@ /* Board init. */ -static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) -{ - int n; - uint32_t smpboot[] = { - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ - 0xe210000f, /* ands r0, r0, #0x0f */ - 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ - 0xe0830200, /* add r0, r3, r0, lsl #4 */ - 0xe59f2024, /* ldr r2, privbase */ - 0xe3a01001, /* mov r1, #1 */ - 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ - 0xe3a010ff, /* mov r1, #0xff */ - 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ - 0xf57ff04f, /* dsb */ - 0xe320f003, /* wfi */ - 0xe5901000, /* ldr r1, [r0] */ - 0xe1110001, /* tst r1, r1 */ - 0x0afffffb, /* beq */ - 0xe12fff11, /* bx r1 */ - MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ - }; - for (n = 0; n < ARRAY_SIZE(smpboot); n++) { - smpboot[n] = tswap32(smpboot[n]); - } - rom_add_blob_fixed_as("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR, - arm_boot_address_space(cpu, info)); -} - -static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) -{ - CPUARMState *env = &cpu->env; - - switch (info->nb_cpus) { - case 4: - address_space_stl_notdirty(&address_space_memory, - SMP_BOOT_REG + 0x30, 0, - MEMTXATTRS_UNSPECIFIED, NULL); - /* fallthrough */ - case 3: - address_space_stl_notdirty(&address_space_memory, - SMP_BOOT_REG + 0x20, 0, - MEMTXATTRS_UNSPECIFIED, NULL); - /* fallthrough */ - case 2: - address_space_stl_notdirty(&address_space_memory, - SMP_BOOT_REG + 0x10, 0, - MEMTXATTRS_UNSPECIFIED, NULL); - env->regs[15] = SMP_BOOT_ADDR; - break; - default: - break; - } -} - #define NUM_REGS 0x200 static void hb_regs_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) @@ -380,8 +326,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) highbank_binfo.board_id = -1; highbank_binfo.nb_cpus = smp_cpus; highbank_binfo.loader_start = 0; - highbank_binfo.write_secondary_boot = hb_write_secondary; - highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; From patchwork Thu Jan 27 15:46:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 1585243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=xe/aiDz9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:10 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/16] hw/arm/boot: Drop nb_cpus field from arm_boot_info Date: Thu, 27 Jan 2022 15:46:38 +0000 Message-Id: <20220127154639.2090164-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::429 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We use the arm_boot_info::nb_cpus field in only one place, and that place can easily get the number of CPUs locally rather than relying on the board code to have set the field correctly. (At least one board, xlnx-versal-virt, does not set the field despite having more than one CPU.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/arm/boot.h | 1 - hw/arm/aspeed.c | 1 - hw/arm/boot.c | 7 +++---- hw/arm/exynos4_boards.c | 1 - hw/arm/highbank.c | 1 - hw/arm/imx25_pdk.c | 3 +-- hw/arm/kzm.c | 1 - hw/arm/mcimx6ul-evk.c | 1 - hw/arm/mcimx7d-sabre.c | 1 - hw/arm/npcm7xx.c | 3 --- hw/arm/orangepi.c | 4 +--- hw/arm/raspi.c | 1 - hw/arm/realview.c | 1 - hw/arm/sabrelite.c | 1 - hw/arm/sbsa-ref.c | 1 - hw/arm/vexpress.c | 1 - hw/arm/virt.c | 1 - hw/arm/xilinx_zynq.c | 1 - 18 files changed, 5 insertions(+), 26 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index 0cfc1c95c4e..c7ebae156ec 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -56,7 +56,6 @@ struct arm_boot_info { hwaddr smp_loader_start; hwaddr smp_bootreg_addr; hwaddr gic_cpu_if_addr; - int nb_cpus; int board_id; /* ARM machines that support the ARM Security Extensions use this field to * control whether Linux is booted as secure(true) or non-secure(false). diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cf20ae0db5e..d911dc904fb 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -431,7 +431,6 @@ static void aspeed_machine_init(MachineState *machine) aspeed_board_binfo.ram_size = machine->ram_size; aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; - aspeed_board_binfo.nb_cpus = sc->num_cpus; if (amc->i2c_init) { amc->i2c_init(bmc); diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 184628ce564..b46f1fe889e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1030,9 +1030,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, elf_machine = EM_ARM; } - if (info->nb_cpus == 0) - info->nb_cpus = 1; - /* Assume that raw images are linux kernels, and ELF images are not. */ kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr, &image_high_addr, elf_machine, as); @@ -1291,6 +1288,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) AddressSpace *as = arm_boot_address_space(cpu, info); int boot_el; CPUARMState *env = &cpu->env; + int nb_cpus = 0; /* * CPU objects (unlike devices) are not automatically reset on system @@ -1300,6 +1298,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) */ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); + nb_cpus++; } /* @@ -1376,7 +1375,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info) } if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED && - info->is_linux && info->nb_cpus > 1) { + info->is_linux && nb_cpus > 1) { /* * We're booting Linux but not using PSCI, so for SMP we need * to write a custom secondary CPU boot loader stub, and arrange diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 35dd9875da1..ef5bcbc212c 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -67,7 +67,6 @@ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = { static struct arm_boot_info exynos4_board_binfo = { .loader_start = EXYNOS4210_BASE_BOOT_ADDR, .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR, - .nb_cpus = EXYNOS4210_NCPUS, .write_secondary_boot = exynos4210_write_secondary, }; diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index da681b15708..f12aacea6b8 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -324,7 +324,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) * clear that the value is meaningless. */ highbank_binfo.board_id = -1; - highbank_binfo.nb_cpus = smp_cpus; highbank_binfo.loader_start = 0; highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 6dff0001633..b4f7f4e8a7f 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -114,8 +114,7 @@ static void imx25_pdk_init(MachineState *machine) imx25_pdk_binfo.ram_size = machine->ram_size; imx25_pdk_binfo.loader_start = FSL_IMX25_SDRAM0_ADDR; - imx25_pdk_binfo.board_id = 1771, - imx25_pdk_binfo.nb_cpus = 1; + imx25_pdk_binfo.board_id = 1771; for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) { BusState *bus; diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 39559c44c29..b1b281c9acb 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -124,7 +124,6 @@ static void kzm_init(MachineState *machine) } kzm_binfo.ram_size = machine->ram_size; - kzm_binfo.nb_cpus = 1; if (!qtest_enabled()) { arm_load_kernel(&s->soc.cpu, machine, &kzm_binfo); diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 8131518426a..d83c3c380e8 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -34,7 +34,6 @@ static void mcimx6ul_evk_init(MachineState *machine) .loader_start = FSL_IMX6UL_MMDC_ADDR, .board_id = -1, .ram_size = machine->ram_size, - .nb_cpus = machine->smp.cpus, .psci_conduit = QEMU_PSCI_CONDUIT_SMC, }; diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index ba84fc21920..6182b15f190 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -36,7 +36,6 @@ static void mcimx7d_sabre_init(MachineState *machine) .loader_start = FSL_IMX7_MMDC_ADDR, .board_id = -1, .ram_size = machine->ram_size, - .nb_cpus = machine->smp.cpus, .psci_conduit = QEMU_PSCI_CONDUIT_SMC, }; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 878c2208e07..d85cc027651 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -355,10 +355,7 @@ static struct arm_boot_info npcm7xx_binfo = { void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) { - NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); - npcm7xx_binfo.ram_size = machine->ram_size; - npcm7xx_binfo.nb_cpus = sc->num_cpus; arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 68fe9182414..3ace4748704 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -25,9 +25,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" -static struct arm_boot_info orangepi_binfo = { - .nb_cpus = AW_H3_NUM_CPUS, -}; +static struct arm_boot_info orangepi_binfo; static void orangepi_init(MachineState *machine) { diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index b4dd6c1e99a..92d068d1f9d 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -204,7 +204,6 @@ static void setup_boot(MachineState *machine, RaspiProcessorId processor_id, s->binfo.board_id = MACH_TYPE_BCM2708; s->binfo.ram_size = ram_size; - s->binfo.nb_cpus = machine->smp.cpus; if (processor_id <= PROCESSOR_ID_BCM2836) { /* diff --git a/hw/arm/realview.c b/hw/arm/realview.c index ddc70b54a56..7b424e94a5f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -363,7 +363,6 @@ static void realview_init(MachineState *machine, memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); realview_binfo.ram_size = ram_size; - realview_binfo.nb_cpus = smp_cpus; realview_binfo.board_id = realview_board_id[board_type]; realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index cce49aa25cf..41191245b81 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -93,7 +93,6 @@ static void sabrelite_init(MachineState *machine) } sabrelite_binfo.ram_size = machine->ram_size; - sabrelite_binfo.nb_cpus = machine->smp.cpus; sabrelite_binfo.secure_boot = true; sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary; sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index dd944553f78..23874019639 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -776,7 +776,6 @@ static void sbsa_ref_init(MachineState *machine) create_secure_ec(secure_sysmem); sms->bootinfo.ram_size = machine->ram_size; - sms->bootinfo.nb_cpus = smp_cpus; sms->bootinfo.board_id = -1; sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; sms->bootinfo.get_dtb = sbsa_ref_dtb; diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 3e99b7918ab..e1d1983ae65 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -708,7 +708,6 @@ static void vexpress_common_init(MachineState *machine) } daughterboard->bootinfo.ram_size = machine->ram_size; - daughterboard->bootinfo.nb_cpus = machine->smp.cpus; daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID; daughterboard->bootinfo.loader_start = daughterboard->loader_start; daughterboard->bootinfo.smp_loader_start = map[VE_SRAM]; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 398145a7180..46bf7ceddf3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2229,7 +2229,6 @@ static void machvirt_init(MachineState *machine) } vms->bootinfo.ram_size = machine->ram_size; - vms->bootinfo.nb_cpus = smp_cpus; vms->bootinfo.board_id = -1; vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; vms->bootinfo.get_dtb = machvirt_dtb; diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 50e7268396c..3190cc0b8db 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -343,7 +343,6 @@ static void zynq_init(MachineState *machine) sysbus_mmio_map(busdev, 0, 0xF8007000); zynq_binfo.ram_size = machine->ram_size; - zynq_binfo.nb_cpus = 1; zynq_binfo.board_id = 0xd32; zynq_binfo.loader_start = 0; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id w9sm6687667wmc.36.2022.01.27.07.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jan 2022 07:47:11 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/16] hw/arm/boot: Drop existing dtb /psci node rather than retaining it Date: Thu, 27 Jan 2022 15:46:39 +0000 Message-Id: <20220127154639.2090164-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127154639.2090164-1-peter.maydell@linaro.org> References: <20220127154639.2090164-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Beniamino Galvani , Alistair Francis , Rob Herring , Andrew Jeffery , Andre Przywara , Tyrone Ting , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Yanan Wang , Igor Mitsyanko , Niek Linnenbank , Alexander Graf , =?utf-8?q?C=C3=A9dric_Le_Goater?= , "Edgar E. Iglesias" , Havard Skinnemoen , Andrey Smirnov , Joel Stanley Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" If we're using PSCI emulation, we add a /psci node to the device tree we pass to the guest. At the moment, if the dtb already has a /psci node in it, we retain it, rather than replacing it. (This behaviour was added in commit c39770cd637765 in 2018.) This is a problem if the existing node doesn't match our PSCI emulation. In particular, it might specify the wrong method (HVC vs SMC), or wrong function IDs for cpu_suspend/cpu_off/etc, in which case the guest will not get the behaviour it wants when it makes PSCI calls. An example of this is trying to boot the highbank or midway board models using the device tree supplied in the kernel sources: this device tree includes a /psci node that specifies function IDs that don't match the (PSCI 0.2 compliant) IDs that QEMU uses. The dtb cpu_suspend function ID happens to match the PSCI 0.2 cpu_off ID, so the guest hangs after booting when the kernel tries to idle the CPU and instead it gets turned off. Instead of retaining an existing /psci node, delete it entirely and replace it with a node whose properties match QEMU's PSCI emulation behaviour. This matches the way we handle /memory nodes, where we also delete any existing nodes and write in ones that match the way QEMU is going to behave. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I'm not confident about the FDT API to use to remove an existing node -- I used qemu_fdt_nop_node() as that matches the code in boot.c that's removing the memory nodes. There is also an fdt_del_node(), though... --- hw/arm/boot.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b46f1fe889e..b1e95978f26 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -478,12 +478,13 @@ static void fdt_add_psci_node(void *fdt) } /* - * If /psci node is present in provided DTB, assume that no fixup - * is necessary and all PSCI configuration should be taken as-is + * A pre-existing /psci node might specify function ID values + * that don't match QEMU's PSCI implementation. Delete the whole + * node and put our own in instead. */ rc = fdt_path_offset(fdt, "/psci"); if (rc >= 0) { - return; + qemu_fdt_nop_node(fdt, "/psci"); } qemu_fdt_add_subnode(fdt, "/psci");