From patchwork Tue Feb 13 03:34:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 872558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-473134-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="nn/oM+Ui"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zgSpK2Xckz9sNw for ; Tue, 13 Feb 2018 14:34:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=TJ0ZY7Cv/k25TFV8 DtKow08arTG2Kr8P5I5WlQCwdkJur+jy3ZCWHX18sVrOsrihrYsagmz2JSPiseqv FKp1v8cfnaoLTjxabBtogzVpZQ62p/ObgSZFTlRe+dOmRHrSrEgH+nIHDQqZvy6i WASmo7t08j1alkbiayfySwB3qaw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type :content-transfer-encoding; s=default; bh=smv228FAtg6awQNiTrn0gR 4y80c=; b=nn/oM+Ui0RRgiCCuBR+kzByC99xO5kk//3VEKAufWvXYjUHnvnpfh3 gRjPgt1gYTprssTJwX0oNTIQ6pmou6OnCFdVujPGCiAwmcUR4XZD9hq8hAFPWHCr cOBisUhj1BpIMImThNdIVEi7QqSS8p7V921fRvlsoN2XsT9dLElDQ= Received: (qmail 18841 invoked by alias); 13 Feb 2018 03:34:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17806 invoked by uid 89); 13 Feb 2018 03:34:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.6 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=H*F:U*peter, H*MI:4b62, Hx-languages-length:4201, H*M:4b62 X-HELO: gateway32.websitewelcome.com Received: from gateway32.websitewelcome.com (HELO gateway32.websitewelcome.com) (192.185.145.113) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Feb 2018 03:34:35 +0000 Received: from cm16.websitewelcome.com (cm16.websitewelcome.com [100.42.49.19]) by gateway32.websitewelcome.com (Postfix) with ESMTP id 85FA935C35 for ; Mon, 12 Feb 2018 21:34:33 -0600 (CST) Received: from gator3106.hostgator.com ([50.87.144.141]) by cmsmtp with SMTP id lRMXeRtCpODN4lRMXeL2sq; Mon, 12 Feb 2018 21:34:33 -0600 Received: from 64-83-233-176.static.stcd.mn.charter.com ([64.83.233.176]:52411 helo=otta.local) by gator3106.hostgator.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.89_1) (envelope-from ) id 1elRMW-0003oF-Bk; Mon, 12 Feb 2018 21:34:32 -0600 To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt , Jakub Jelinek From: Peter Bergner Subject: [PATCH, rs6000] Fix PR84279, powerpc64le ICE on cvc4 Message-ID: <31e557e6-4b62-eeca-a1a3-173397c205e7@bergner.org> Date: Mon, 12 Feb 2018 21:34:30 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 X-BWhitelist: no X-Source-L: No X-Exim-ID: 1elRMW-0003oF-Bk X-Source-Sender: 64-83-233-176.static.stcd.mn.charter.com (otta.local) [64.83.233.176]:52411 X-Source-Auth: peter@bergner.org X-Email-Count: 1 X-Source-Cap: YmVyZ25lcjtiZXJnbmVyO2dhdG9yMzEwNi5ob3N0Z2F0b3IuY29t X-Local-Domain: yes PR84279 is a similar problem to PR83399, in that we generate an altivec load/store through an explicit call to the altivec_{l,st}vx_v4si_2op pattern and then due to spilling, we end up calling recog() and we match an earlier pattern, in this case vsx_movv4si_64bit. That is ok, since this pattern can generate the lvx/stvx insns the altivec patterm can. However, due to a constraint bug, we end up using the wrong alternative. The problematic code after spilling looks like: (insn 92 131 126 2 (parallel [ (set (reg:V4SI 140) (unspec:V4SI [ (reg:SI 143 [ g ]) (reg:SI 150 [ ar.v ]) (subreg:SI (reg:DI 146) 0) (subreg:SI (reg:DI 149) 0) ] UNSPEC_VSX_VEC_INIT)) (clobber (scratch:DI)) (clobber (scratch:DI)) ]) "bug.i":25 1237 {vsx_init_v4si}) (insn 126 92 95 2 (set (mem/c:V4SI (and:DI (plus:DI (reg/f:DI 111 sfp) (reg:DI 156)) (const_int -16 [0xfffffffffffffff0])) [3 MEM[(struct A *)&am]+0 S16 A128]) (reg:V4SI 140)) "bug.i":25 1792 {altivec_stvx_v4si_2op}) The vsx_init_v4si pattern forces pseudo 140 to be assigned a GPR, which should force a reload in insn 126, because the altivec store requires an altivec register for its src operand. However, after recog(), we end up using the vsx_movv4si_64bit pattern which looks like: (define_insn "*vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, , , r, we, ?wQ, ?&r, ??r, ??Y, ??r, wo, v, ?, *r, v, ??r, wZ, v") (match_operand:VSX_M 1 "input_operand" ", ZwO, , we, r, r, wQ, Y, r, r, wE, jwM, ?jwM, jwM, W, W, v, wZ"))] Now we _should_ match using the second to last alternative, but we end up matching the 8th alternative ("??Y" and "r"). The 8th alternative is used for storing a GPR, which we have, but the mem we're trying to store to does not have a valid address for a GPR store. The "bug" is that the "Y" constraint code, which is implemented by mem_operand_gpr() allows our altivec address when it should not. The following patch which fixes the ICE adds code to mem_operand_gpr() which disallows such addresses. This patch passed bootstrap and retesting on powerpc64le-linux with no regressions. Ok for mainline? Peter gcc/ PR target/84279 * config/rs6000/rs6000.c (mem_operand_gpr): Disallow altivec addresses. gcc/testsuite/ PR target/84279 * g++.dg/pr84279.C: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 257606) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -8220,6 +8220,12 @@ mem_operand_gpr (rtx op, machine_mode mo int extra; rtx addr = XEXP (op, 0); + /* Don't allow altivec type addresses like (mem (and (plus ...))). + See PR target/84279. */ + + if (GET_CODE (addr) == AND) + return false; + op = address_offset (addr); if (op == NULL_RTX) return true; Index: gcc/testsuite/g++.dg/pr84279.C =================================================================== --- gcc/testsuite/g++.dg/pr84279.C (nonexistent) +++ gcc/testsuite/g++.dg/pr84279.C (working copy) @@ -0,0 +1,35 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O3 -mcpu=power8 -g -fPIC -fvisibility=hidden -fstack-protector-strong" } */ + +template struct E { T e; }; +struct J { + unsigned k, l; + J (unsigned x, unsigned y) : k(x), l(y) {} +}; +typedef struct A { + J n, p; + A (); + A (J x, J y) : n(x), p(y) {} +} *S; +S t; +struct B { + struct C { + S q, r; + int u, v; + bool m1 (S, A &); + J m2 () const; + J m3 () const; + A m4 () const; + }; + typedef E D; + void m5 (D *); + void m6 (unsigned, A); +}; +bool B::C::m1 (S, A &x) { bool o; x = m4 (); return o; } +J B::C::m2 () const { unsigned g (u == 0); unsigned h (v); return J (g, h); } +J B::C::m3 () const { unsigned g (q != t); unsigned h (r != t); return J (g, h); } +A B::C::m4 () const { return A (m2 (), m3 ()); } +void B::m5 (D *c) { unsigned x; C ar; A am; if (ar.m1 (c->e, am)) m6 (x, am); }