From patchwork Mon Feb 12 03:40:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="AwsoQNv3"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs4y5VK5z9t2l for ; Mon, 12 Feb 2018 14:45:22 +1100 (AEDT) Received: from localhost ([::1]:34098 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el53Q-00025a-Mt for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:45:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zL-0007hK-JE for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zH-000679-Rz for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:07 -0500 Received: from ozlabs.org ([103.22.144.67]:60567) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zG-00063v-VI; Sun, 11 Feb 2018 22:41:03 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzs52Qvz9t3F; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406857; bh=dURwxk/PMU6k39+qxU9fvQeT9ihZsa+BJOaA0jOA2Qc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AwsoQNv3FOkXf/3p0Vql5fTONngd2FxmV1vcrRIbkZoIM4F9FNEmTa/7UxbkmV7+x MCXCMuMNLKwvIPthAa8cLRt8wS4hzZCXgJLt7WnKA2rX0XAQ8ENKmtQYe4hRemQIM8 pJAKd99wsAsEaJEB2B3ze5c9pc0GK22bd1yNECB4= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:43 +1100 Message-Id: <20180212034054.23441-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 01/12] spapr: add missing break in h_get_cpu_characteristics() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz Detected by Coverity (CID 1385702). This fixes the recently added hypercall to let guests properly apply Spectre and Meltdown workarounds. Fixes: c59704b25473 "target/ppc/spapr: Add H-Call H_GET_CPU_CHARACTERISTICS" Reported-by: Paolo Bonzini Signed-off-by: Greg Kurz Reviewed-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- hw/ppc/spapr_hcall.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 4d0e6eb0cf..596f58378a 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1697,6 +1697,7 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu, switch (safe_indirect_branch) { case SPAPR_CAP_FIXED: characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED; + break; default: /* broken */ assert(safe_indirect_branch == SPAPR_CAP_BROKEN); break; From patchwork Mon Feb 12 03:40:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871864 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="W2uYP1yj"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs170PMwz9s8J for ; Mon, 12 Feb 2018 14:42:02 +1100 (AEDT) Received: from localhost ([::1]:34081 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el50B-0007i8-Lj for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:41:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zJ-0007gw-C6 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zH-00067Q-UE for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:05 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:52435) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zG-00063p-Uz; Sun, 11 Feb 2018 22:41:03 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzs3zzmz9s8J; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406857; bh=PkWy+Y2NamZ7LZaiL4NL3nahDWyn0TEGHkJcASQXIT8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W2uYP1yjt1K0g+WJiLcsYNldKWjqQnEMoGPKNRBtkRgk/yUEB4xKxxMTYq2oFK2qm Gwr4XgRQCOFUBHz78hnuDxlnjb85MciTWvOVncFk4DxN3nw/eyS9McWVpSIqaSNeBS D7NfRKr8a/am3Ylfd7oxPaLHy/6pa2UYKnm0Mx0w= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:44 +1100 Message-Id: <20180212034054.23441-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 02/12] hw/ppc: rename functions in comments X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Daniel Henrique Barboza , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Daniel Henrique Barboza Commit bcb5ce08cf ("spapr: Rename machine init functions for clarity") renamed ppc_spapr_reset to spapr_machine_reset and ppc_spapr_init to spapr_machine_init. Let's also rename the references in comments. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/ppc/spapr.c | 3 ++- hw/ppc/spapr_hcall.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 659be6b746..96515036e6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -464,7 +464,8 @@ static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) } } if (!mem_start) { - /* ppc_spapr_init() checks for rma_size <= node0_size already */ + /* spapr_machine_init() checks for rma_size <= node0_size + * already */ spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); mem_start += spapr->rma_size; node_size -= spapr->rma_size; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 596f58378a..76422cfac1 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1635,7 +1635,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu, spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, OV1_PPC_3_00); if (!spapr->cas_reboot) { - /* If ppc_spapr_reset() did not set up a HPT but one is necessary + /* If spapr_machine_reset() did not set up a HPT but one is necessary * (because the guest isn't going to use radix) then set it up here. */ if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { /* legacy hash or new hash: */ From patchwork Mon Feb 12 03:40:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="ZI9vK4wo"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs980c37z9t2l for ; Mon, 12 Feb 2018 14:49:00 +1100 (AEDT) Received: from localhost ([::1]:34117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el56w-0004v0-34 for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:48:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zN-0007iK-DZ for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006BD-19 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:09 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:41937) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-000685-I3; Sun, 11 Feb 2018 22:41:06 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt0ZFMz9t3l; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=HEWydNp3dJtPD/0Hwbpgzj6D2qW6OMHF+rdOpjvuCvQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZI9vK4woeDgHvy8FZM81IUyAnUlmvlVpGtzwXf7gEcAkLv2+8AVucjsCDW+KsCQZi jy7vh47npprBuuMoXxTpGJeboEVaSOXGwRN52ZWso7332uu3L1dbJwmo/LaBYKwr/E vVEd51fAAtiI6l1EW3Pd4kcRmExTeulsEGj7u8HQ= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:45 +1100 Message-Id: <20180212034054.23441-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 03/12] cuda: do not use old_mmio accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 40 ++++++++-------------------------------- 1 file changed, 8 insertions(+), 32 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 008d8bd4d5..6631017ca2 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -275,7 +275,7 @@ static void cuda_delay_set_sr_int(CUDAState *s) timer_mod(s->sr_delay_timer, expire); } -static uint32_t cuda_readb(void *opaque, hwaddr addr) +static uint64_t cuda_read(void *opaque, hwaddr addr, unsigned size) { CUDAState *s = opaque; uint32_t val; @@ -350,7 +350,7 @@ static uint32_t cuda_readb(void *opaque, hwaddr addr) return val; } -static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val) +static void cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { CUDAState *s = opaque; @@ -780,38 +780,14 @@ static void cuda_receive_packet_from_host(CUDAState *s, } } -static void cuda_writew (void *opaque, hwaddr addr, uint32_t value) -{ -} - -static void cuda_writel (void *opaque, hwaddr addr, uint32_t value) -{ -} - -static uint32_t cuda_readw (void *opaque, hwaddr addr) -{ - return 0; -} - -static uint32_t cuda_readl (void *opaque, hwaddr addr) -{ - return 0; -} - static const MemoryRegionOps cuda_ops = { - .old_mmio = { - .write = { - cuda_writeb, - cuda_writew, - cuda_writel, - }, - .read = { - cuda_readb, - cuda_readw, - cuda_readl, - }, + .read = cuda_read, + .write = cuda_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 1, }, - .endianness = DEVICE_NATIVE_ENDIAN, }; static bool cuda_timer_exist(void *opaque, int version_id) From patchwork Mon Feb 12 03:40:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="oTsVIy1B"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs1D6sBsz9s8J for ; Mon, 12 Feb 2018 14:42:08 +1100 (AEDT) Received: from localhost ([::1]:34084 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el50I-0007lJ-Rr for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:42:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zL-0007hL-JA for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zH-00067I-SR for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:07 -0500 Received: from ozlabs.org ([103.22.144.67]:42757) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zG-00063u-V4; Sun, 11 Feb 2018 22:41:03 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzs605rz9t3C; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406857; bh=ut5JMd2CysqpPJYl7Led4uytJLVnDPKPgTdHOAmFw6Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oTsVIy1BC4FrWzw9nJ6dltiemrD9UA1MG+CvtXC9GsOXVndpgrnVkFWHf7EpSUitY Yjuk9lPbbOdxYHuJ76G/BTG+nfPfSFVpW4voFAcNVLdG4XUw0k7GWZ+wPCbz1ddv56 2vWw79IO4/oZkM0JrbA5fn2YuX0Qp1nhZ8ni327A= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:46 +1100 Message-Id: <20180212034054.23441-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 04/12] cuda: don't allow writes to port output pins X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Use the direction registers as a mask to ensure that only input pins are updated upon write. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 6631017ca2..eaa8924f49 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -359,11 +359,11 @@ static void cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) switch(addr) { case CUDA_REG_B: - s->b = val; + s->b = (s->b & ~s->dirb) | (val & s->dirb); cuda_update(s); break; case CUDA_REG_A: - s->a = val; + s->a = (s->a & ~s->dira) | (val & s->dira); break; case CUDA_REG_DIRB: s->dirb = val; From patchwork Mon Feb 12 03:40:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871865 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="B4KbczF/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs194S8mz9s8J for ; Mon, 12 Feb 2018 14:42:05 +1100 (AEDT) Received: from localhost ([::1]:34083 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el50F-0007ik-G9 for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:42:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44887) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zJ-0007gp-5J for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zH-00067b-UU for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:05 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:41785) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zG-00063q-V3; Sun, 11 Feb 2018 22:41:03 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzs6yTVz9t3Z; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406857; bh=xc3cWte9SdlObzWKx2hMSTesiRm1+zTKt39c3cya5ZQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4KbczF/+7R4BHYyvkj1GOf3s9jbSZ22JIncpyOT/t5mvZLDYWjU+F4S4WH/u8ZL5 NHMEX0SGQgQSuZ0SBJuErlLAIuhc5JThkMQA35F6ifoKVquBiZeDh+U55pzodbgMLD Q9iU869vUldmJYE2aaCiuA3iJB5ffKSRG2T0BO84= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:47 +1100 Message-Id: <20180212034054.23441-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 05/12] spapr: set vsmt to MAX(8, smp_threads) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Laurent Vivier We ignore silently the value of smp_threads when we set the default VSMT value, and if smp_threads is greater than VSMT kernel is going into trouble later. Fixes: 8904e5a750 ("spapr: Adjust default VSMT value for better migration compatibility") Signed-off-by: Laurent Vivier Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/ppc/spapr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 96515036e6..9f29434819 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2310,7 +2310,7 @@ static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) * the value that we'd get with KVM on POWER8, the * overwhelmingly common case in production systems. */ - spapr->vsmt = 8; + spapr->vsmt = MAX(8, smp_threads); } /* KVM: If necessary, set the SMT mode: */ From patchwork Mon Feb 12 03:40:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="C0nUK7+K"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfsDg03rPz9t2l for ; Mon, 12 Feb 2018 14:52:03 +1100 (AEDT) Received: from localhost ([::1]:34369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el59t-0007r5-3k for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:52:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45001) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zN-0007ib-J6 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006Bp-ED for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:09 -0500 Received: from ozlabs.org ([103.22.144.67]:51027) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-00068J-O7; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt4bqGz9t3n; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=vqJ2YK7yEhUYagvuiWrtEFfhwm8qn+GOMLmmxxLgeTo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C0nUK7+K5XS2Gdoc9Pvc6H8pKmObIhXTobEWsUvenMLCllrH8WqvXRQXx89A2Pqb1 L7wn/qIX+Cccdf2DqJhhEetrk7kdgXK2OSKAmisHbOpWsgAt62wN+XookALpEOxQ1K Z19n6CKkdey2a641w8KNtjDeAszENex8gXAmvZfE= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:48 +1100 Message-Id: <20180212034054.23441-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 06/12] cuda: introduce CUDAState parameter to get_counter() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This will be required shortly and also happens to match nicely with the corresponding signature for set_counter(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index eaa8924f49..fa10b6d0c1 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -150,7 +150,7 @@ static uint64_t get_tb(uint64_t time, uint64_t freq) return muldiv64(time, freq, NANOSECONDS_PER_SECOND); } -static unsigned int get_counter(CUDATimer *ti) +static unsigned int get_counter(CUDAState *s, CUDATimer *ti) { int64_t d; unsigned int counter; @@ -295,12 +295,12 @@ static uint64_t cuda_read(void *opaque, hwaddr addr, unsigned size) val = s->dira; break; case CUDA_REG_T1CL: - val = get_counter(&s->timers[0]) & 0xff; + val = get_counter(s, &s->timers[0]) & 0xff; s->ifr &= ~T1_INT; cuda_update_irq(s); break; case CUDA_REG_T1CH: - val = get_counter(&s->timers[0]) >> 8; + val = get_counter(s, &s->timers[0]) >> 8; cuda_update_irq(s); break; case CUDA_REG_T1LL: @@ -311,12 +311,12 @@ static uint64_t cuda_read(void *opaque, hwaddr addr, unsigned size) val = (s->timers[0].latch >> 8) & 0xff; break; case CUDA_REG_T2CL: - val = get_counter(&s->timers[1]) & 0xff; + val = get_counter(s, &s->timers[1]) & 0xff; s->ifr &= ~T2_INT; cuda_update_irq(s); break; case CUDA_REG_T2CH: - val = get_counter(&s->timers[1]) >> 8; + val = get_counter(s, &s->timers[1]) >> 8; break; case CUDA_REG_SR: val = s->sr; From patchwork Mon Feb 12 03:40:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="Fenrrzlz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs4y1vX7z9s8J for ; Mon, 12 Feb 2018 14:45:22 +1100 (AEDT) Received: from localhost ([::1]:34096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el53Q-000241-At for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:45:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zO-0007jp-Jj for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006Bv-Hf for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:10 -0500 Received: from ozlabs.org ([103.22.144.67]:42897) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-00068E-Pa; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt2xrZz9t3w; Mon, 12 Feb 2018 14:40:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=hArf4DEH8bsyuJ8rC6jmdCtxnoSwHhGOBsz+eHDY2gg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fenrrzlz+BRw7AuY6wBOqwJrWTkX22Sum3zN6IOKxu1ndnKrA37lq2VBxVNT5vm3u R4eSkyccG9p6O3bGy8f+bO4uEexIekuFgLdT6NVKJ2TBMmHenh8b3kkJxjKZdAHB0E JxcWBVur967fj4lm3Dlf3wyYd9WnMuU7G3u8RypQ= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:49 +1100 Message-Id: <20180212034054.23441-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 07/12] cuda: rename frequency property to tb_frequency X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland This allows us to more easily differentiate between the timebase frequency used to calibrate the MacOS timers and the actual frequency of the hardware clock as indicated by CUDA_TIMER_FREQ. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé [dwg: Revert some extraneous changes which break compile] Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 6 +++--- hw/misc/macio/macio.c | 2 +- hw/ppc/mac.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index fa10b6d0c1..d4a52fbddb 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -179,7 +179,7 @@ static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) { CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti->index, val); ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->frequency); + s->tb_frequency); ti->counter_value = val; cuda_timer_update(s, ti, ti->load_time); } @@ -879,7 +879,7 @@ static void cuda_realizefn(DeviceState *dev, Error **errp) struct tm tm; s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s); - s->timers[0].frequency = s->frequency; + s->timers[0].frequency = s->tb_frequency; s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s); s->timers[1].frequency = (SCALE_US * 6000) / 4700; @@ -910,7 +910,7 @@ static void cuda_initfn(Object *obj) } static Property cuda_properties[] = { - DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0), + DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), DEFINE_PROP_END_OF_LIST() }; diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 44f91d1e7f..a639b09e00 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -451,7 +451,7 @@ void macio_init(PCIDevice *d, macio_state->escc_mem = escc_mem; /* Note: this code is strongly inspirated from the corresponding code in PearPC */ - qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "frequency", + qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency", macio_state->frequency); qdev_init_nofail(DEVICE(d)); diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index b501af1653..fa78115c95 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -99,7 +99,7 @@ typedef struct CUDAState { CUDATimer timers[2]; uint32_t tick_offset; - uint64_t frequency; + uint64_t tb_frequency; uint8_t last_b; uint8_t last_acr; From patchwork Mon Feb 12 03:40:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="XsZC9M4S"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs5R5sLHz9s8J for ; Mon, 12 Feb 2018 14:45:47 +1100 (AEDT) Received: from localhost ([::1]:34103 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el53p-0002SG-RE for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:45:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zO-0007jW-A4 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006Be-C8 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:10 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:49155) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-00068D-Pi; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt5gt9z9t3m; Mon, 12 Feb 2018 14:40:58 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=+JybuRhAidvl5vpjurSmS63KCg9ZTzG6HT6IEyK0rhk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XsZC9M4Swmp7b+KjIaVZH+bpGd9h2n8N1++jeb3oLCp+tcwVLA1m/Rqf2HFWtUoHL hIdbnY8QjVD19V0n4Nv6W/TdQn+y9HPct7AhiK2fNY64cFK535O/uQn5bWf9vNAAKc XdlAhFnQ12rn5JwQYkCcCyBgCcgmjGtdeYVnL8ko= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:50 +1100 Message-Id: <20180212034054.23441-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 08/12] cuda: minor cosmetic tidy-ups to get_next_irq_time() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index d4a52fbddb..729905236c 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -184,36 +184,37 @@ static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) cuda_timer_update(s, ti, ti->load_time); } -static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time) +static int64_t get_next_irq_time(CUDATimer *ti, int64_t current_time) { int64_t d, next_time; unsigned int counter; /* current counter value */ - d = muldiv64(current_time - s->load_time, + d = muldiv64(current_time - ti->load_time, CUDA_TIMER_FREQ, NANOSECONDS_PER_SECOND); /* the timer goes down from latch to -1 (period of latch + 2) */ - if (d <= (s->counter_value + 1)) { - counter = (s->counter_value - d) & 0xffff; + if (d <= (ti->counter_value + 1)) { + counter = (ti->counter_value - d) & 0xffff; } else { - counter = (d - (s->counter_value + 1)) % (s->latch + 2); - counter = (s->latch - counter) & 0xffff; + counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter = (ti->latch - counter) & 0xffff; } /* Note: we consider the irq is raised on 0 */ if (counter == 0xffff) { - next_time = d + s->latch + 1; + next_time = d + ti->latch + 1; } else if (counter == 0) { - next_time = d + s->latch + 2; + next_time = d + ti->latch + 2; } else { next_time = d + counter; } CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", - s->latch, d, next_time - d); + ti->latch, d, next_time - d); next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, CUDA_TIMER_FREQ) + - s->load_time; - if (next_time <= current_time) + ti->load_time; + if (next_time <= current_time) { next_time = current_time + 1; + } return next_time; } From patchwork Mon Feb 12 03:40:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871868 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="iBo7Cs+2"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs4w1y0nz9s8J for ; Mon, 12 Feb 2018 14:45:20 +1100 (AEDT) Received: from localhost ([::1]:34097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el53O-000248-5G for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:45:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zN-0007iP-FZ for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006C2-Hd for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:09 -0500 Received: from ozlabs.org ([103.22.144.67]:60017) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-000687-VN; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt1h93z9t3R; Mon, 12 Feb 2018 14:40:58 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=omwDmee7esdjW/Sjgxw2oEtPMnZeej2L9zRQZufxneA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iBo7Cs+20tGMqrxJgJjw487FcmCKHcoNbOtlGDRGdo0JFn3Zy0beIs9FR40GEgDJN LqQ49jmnzy50gIbS/WPdZVwHNTSkDS0dGZ6u9pRqXJu6EKhsAUqzrW5ymw6fGTbgEc PxhpGajxa/BrTZj72udbzBt/TBP/RpITuUXBCveE= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:51 +1100 Message-Id: <20180212034054.23441-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 09/12] cuda: don't call cuda_update() when writing to ACR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland The wire protocol for reading data to/from the VIA is triggered by changing inputs on port B rather than changing the timer configuration via the ACR. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 729905236c..355a2f2262 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -407,7 +407,6 @@ static void cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) case CUDA_REG_ACR: s->acr = val; cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); - cuda_update(s); break; case CUDA_REG_PCR: s->pcr = val; From patchwork Mon Feb 12 03:40:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="cWGzXG43"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs980trjz9t3C for ; Mon, 12 Feb 2018 14:49:00 +1100 (AEDT) Received: from localhost ([::1]:34118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el56w-0004wY-6j for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:48:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zP-0007kp-HN for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006CM-O4 for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:11 -0500 Received: from ozlabs.org ([103.22.144.67]:58467) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zL-00068R-2z; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzv10qKz9t41; Mon, 12 Feb 2018 14:40:58 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406859; bh=SceavMWEC+3N7UxLNDESEMDWak+8MXmEz5uPM/VxMKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cWGzXG43A4c0EGlo102pq8W8crOFO8/rk9f8E7cX8Btvd/GFgufVEhrihy3/co9hi dkNmpTWDa+AbmOp8n8wtFtyLG/9AVC/6+yNA4VSs0eI+LcocVhNrUIzi4Ho95oQp1Q pzNVhyNqQx/mYNYXQsSZlq4ibO6ydVjgTGAuE13A= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:52 +1100 Message-Id: <20180212034054.23441-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 10/12] cuda: set timer 1 frequency property to CUDA_TIMER_FREQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Now that we have successfully decoupled the timebase frequency and the hardware timer frequency, set the timer 1 frequency property to CUDA_TIMER_FREQ and alter get_next_irq_time() to use it rather than the hard-coded constant. In addition to this we must now switch the tb_diff calculation over to use the timebase frequency now that the hardware clock frequency and the timebase frequency are different. Signed-off-by: Mark Cave-Ayland [dwg: Correct a conflict due to a bug in an earlier patch] Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 355a2f2262..e00df4a21a 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -158,8 +158,8 @@ static unsigned int get_counter(CUDAState *s, CUDATimer *ti) uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */ - tb_diff = get_tb(current_time, ti->frequency) - ti->load_time; - d = (tb_diff * 0xBF401675E5DULL) / (ti->frequency << 24); + tb_diff = get_tb(current_time, s->tb_frequency) - ti->load_time; + d = (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); if (ti->index == 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -191,7 +191,7 @@ static int64_t get_next_irq_time(CUDATimer *ti, int64_t current_time) /* current counter value */ d = muldiv64(current_time - ti->load_time, - CUDA_TIMER_FREQ, NANOSECONDS_PER_SECOND); + ti->frequency, NANOSECONDS_PER_SECOND); /* the timer goes down from latch to -1 (period of latch + 2) */ if (d <= (ti->counter_value + 1)) { counter = (ti->counter_value - d) & 0xffff; @@ -210,7 +210,7 @@ static int64_t get_next_irq_time(CUDATimer *ti, int64_t current_time) } CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", ti->latch, d, next_time - d); - next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, CUDA_TIMER_FREQ) + + next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + ti->load_time; if (next_time <= current_time) { next_time = current_time + 1; @@ -879,7 +879,7 @@ static void cuda_realizefn(DeviceState *dev, Error **errp) struct tm tm; s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s); - s->timers[0].frequency = s->tb_frequency; + s->timers[0].frequency = CUDA_TIMER_FREQ; s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer2, s); s->timers[1].frequency = (SCALE_US * 6000) / 4700; From patchwork Mon Feb 12 03:40:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="KbaE/F+I"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfs9707pRz9t2l for ; Mon, 12 Feb 2018 14:48:59 +1100 (AEDT) Received: from localhost ([::1]:34116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el56v-0004t6-49 for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:48:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zP-0007kZ-9H for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zL-0006CT-Nz for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:11 -0500 Received: from ozlabs.org ([103.22.144.67]:58399) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zL-00068P-6R; Sun, 11 Feb 2018 22:41:07 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzv0HlRz9t4t; Mon, 12 Feb 2018 14:40:58 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406859; bh=JoPc6tyRR+MwUkjvf+vit5Avh/VIzmYD7QmvciLJDWU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KbaE/F+IPQK9BDKx4JLTgW5WtsONSrzn/NlGaR20c7uxdYYfo50i8sKFA4PZpE3cj wuzeLpKQbxPWtBkYFjhypRM7WJ3IpGnDGolTysX3oWPD1ktVjlQaG8L8j47oquor4M 9yx4ThrbeR6fyF/c8u6ETQ59pm3M9X3kitYW73yg= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:53 +1100 Message-Id: <20180212034054.23441-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 11/12] cuda: factor out timebase-derived counter value and load time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland Commit b981289c49 "PPC: Cuda: Use cuda timer to expose tbfreq to guest" altered the timer calculations from those based upon the hardware CUDA clock frequency to those based upon the CPU timebase frequency. In fact we can isolate the differences to 2 simple changes: one to the counter read value and another to the counter load time. Move these changes into separate functions so the implementation can be swapped later. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index e00df4a21a..a185252144 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -145,21 +145,29 @@ static void cuda_update_irq(CUDAState *s) } } -static uint64_t get_tb(uint64_t time, uint64_t freq) +static uint64_t get_counter_value(CUDAState *s, CUDATimer *ti) { - return muldiv64(time, freq, NANOSECONDS_PER_SECOND); + /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup */ + uint64_t tb_diff = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + s->tb_frequency, NANOSECONDS_PER_SECOND) - + ti->load_time; + + return (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); +} + +static uint64_t get_counter_load_time(CUDAState *s, CUDATimer *ti) +{ + uint64_t load_time = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + s->tb_frequency, NANOSECONDS_PER_SECOND); + return load_time; } static unsigned int get_counter(CUDAState *s, CUDATimer *ti) { int64_t d; unsigned int counter; - uint64_t tb_diff; - uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */ - tb_diff = get_tb(current_time, s->tb_frequency) - ti->load_time; - d = (tb_diff * 0xBF401675E5DULL) / (s->tb_frequency << 24); + d = get_counter_value(s, ti); if (ti->index == 0) { /* the timer goes down from latch to -1 (period of latch + 2) */ @@ -178,8 +186,7 @@ static unsigned int get_counter(CUDAState *s, CUDATimer *ti) static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) { CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti->index, val); - ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - s->tb_frequency); + ti->load_time = get_counter_load_time(s, ti); ti->counter_value = val; cuda_timer_update(s, ti, ti->load_time); } From patchwork Mon Feb 12 03:40:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 871876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="nZyToi8G"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zfsHk3HfHz9t3C for ; Mon, 12 Feb 2018 14:54:42 +1100 (AEDT) Received: from localhost ([::1]:34968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el5CS-0002Id-Hn for incoming@patchwork.ozlabs.org; Sun, 11 Feb 2018 22:54:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1el4zW-0007tL-Jd for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1el4zM-0006D3-AU for qemu-devel@nongnu.org; Sun, 11 Feb 2018 22:41:18 -0500 Received: from ozlabs.org ([103.22.144.67]:41237) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1el4zK-00068N-T0; Sun, 11 Feb 2018 22:41:08 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zfrzt6gJ2z9t3v; Mon, 12 Feb 2018 14:40:58 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518406858; bh=n/AEtYtaKo0YGYQ5Eon3bAKjGsvplGCvkyRRyExaYSs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nZyToi8GJzNAc8/j9Yq/Yafas5QKUKzPfxU4+VK73P/3xbgsLQaVlWrXPXosp4o+B vj7hjKXAL3hqe/6+NhgmKBIeiwr8eIkfQfK9lyqmFm3gBjViEq2vxNNBLpBqhrQYBv IyQmgG9l3ibmT84JGI7xGsWcFeJtYiGuyacS67/A= From: David Gibson To: peter.maydell@linaro.org Date: Mon, 12 Feb 2018 14:40:54 +1100 Message-Id: <20180212034054.23441-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180212034054.23441-1-david@gibson.dropbear.id.au> References: <20180212034054.23441-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 103.22.144.67 Subject: [Qemu-devel] [PULL 12/12] misc: introduce new mos6522 VIA device and enable it for ppc builds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, mark.cave-ayland@ilande.co.uk, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Mark Cave-Ayland The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations. This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and including a conversion to trace-events. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- default-configs/ppc-softmmu.mak | 1 + hw/misc/Makefile.objs | 3 + hw/misc/mos6522.c | 505 ++++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 7 + include/hw/misc/mos6522.h | 152 ++++++++++++ 5 files changed, 668 insertions(+) create mode 100644 hw/misc/mos6522.c create mode 100644 include/hw/misc/mos6522.h diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak index 65680d85bc..76e29cfa14 100644 --- a/default-configs/ppc-softmmu.mak +++ b/default-configs/ppc-softmmu.mak @@ -30,6 +30,7 @@ CONFIG_MAC=y CONFIG_ESCC=y CONFIG_MACIO=y CONFIG_SUNGEM=y +CONFIG_MOS6522=y CONFIG_CUDA=y CONFIG_ADB=y CONFIG_MAC_NVRAM=y diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index fce426eb75..f33b37a8e5 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -17,6 +17,9 @@ common-obj-$(CONFIG_INTEGRATOR_DEBUG) += arm_integrator_debug.o common-obj-$(CONFIG_A9SCU) += a9scu.o common-obj-$(CONFIG_ARM11SCU) += arm11scu.o +# Mac devices +common-obj-$(CONFIG_MOS6522) += mos6522.o + # PKUnity SoC devices common-obj-$(CONFIG_PUV3) += puv3_pm.o diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c new file mode 100644 index 0000000000..8ad9fc831e --- /dev/null +++ b/hw/misc/mos6522.c @@ -0,0 +1,505 @@ +/* + * QEMU MOS6522 VIA emulation + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "hw/input/adb.h" +#include "hw/misc/mos6522.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "qemu/cutils.h" +#include "qemu/log.h" +#include "trace.h" + +/* XXX: implement all timer modes */ + +static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time); + +static void mos6522_update_irq(MOS6522State *s) +{ + if (s->ifr & s->ier & (SR_INT | T1_INT | T2_INT)) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti) +{ + MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); + + if (ti->index == 0) { + return mdc->get_timer1_counter_value(s, ti); + } else { + return mdc->get_timer2_counter_value(s, ti); + } +} + +static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti) +{ + MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); + + if (ti->index == 0) { + return mdc->get_timer1_load_time(s, ti); + } else { + return mdc->get_timer2_load_time(s, ti); + } +} + +static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti) +{ + int64_t d; + unsigned int counter; + + d = get_counter_value(s, ti); + + if (ti->index == 0) { + /* the timer goes down from latch to -1 (period of latch + 2) */ + if (d <= (ti->counter_value + 1)) { + counter = (ti->counter_value - d) & 0xffff; + } else { + counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter = (ti->latch - counter) & 0xffff; + } + } else { + counter = (ti->counter_value - d) & 0xffff; + } + return counter; +} + +static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val) +{ + trace_mos6522_set_counter(1 + ti->index, val); + ti->load_time = get_load_time(s, ti); + ti->counter_value = val; + mos6522_timer_update(s, ti, ti->load_time); +} + +static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time) +{ + int64_t d, next_time; + unsigned int counter; + + /* current counter value */ + d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + ti->frequency, NANOSECONDS_PER_SECOND); + + /* the timer goes down from latch to -1 (period of latch + 2) */ + if (d <= (ti->counter_value + 1)) { + counter = (ti->counter_value - d) & 0xffff; + } else { + counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); + counter = (ti->latch - counter) & 0xffff; + } + + /* Note: we consider the irq is raised on 0 */ + if (counter == 0xffff) { + next_time = d + ti->latch + 1; + } else if (counter == 0) { + next_time = d + ti->latch + 2; + } else { + next_time = d + counter; + } + trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d); + next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) + + ti->load_time; + if (next_time <= current_time) { + next_time = current_time + 1; + } + return next_time; +} + +static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti, + int64_t current_time) +{ + if (!ti->timer) { + return; + } + if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) { + timer_del(ti->timer); + } else { + ti->next_irq_time = get_next_irq_time(s, ti, current_time); + timer_mod(ti->timer, ti->next_irq_time); + } +} + +static void mos6522_timer1(void *opaque) +{ + MOS6522State *s = opaque; + MOS6522Timer *ti = &s->timers[0]; + + mos6522_timer_update(s, ti, ti->next_irq_time); + s->ifr |= T1_INT; + mos6522_update_irq(s); +} + +static void mos6522_timer2(void *opaque) +{ + MOS6522State *s = opaque; + MOS6522Timer *ti = &s->timers[1]; + + mos6522_timer_update(s, ti, ti->next_irq_time); + s->ifr |= T2_INT; + mos6522_update_irq(s); +} + +static void mos6522_set_sr_int(MOS6522State *s) +{ + trace_mos6522_set_sr_int(); + s->ifr |= SR_INT; + mos6522_update_irq(s); +} + +static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti) +{ + uint64_t d; + + d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time, + ti->frequency, NANOSECONDS_PER_SECOND); + + return d; +} + +static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti) +{ + uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + return load_time; +} + +static void mos6522_portA_write(MOS6522State *s) +{ + qemu_log_mask(LOG_UNIMP, "portA_write unimplemented"); +} + +static void mos6522_portB_write(MOS6522State *s) +{ + qemu_log_mask(LOG_UNIMP, "portB_write unimplemented"); +} + +uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) +{ + MOS6522State *s = opaque; + uint32_t val; + + switch (addr) { + case VIA_REG_B: + val = s->b; + break; + case VIA_REG_A: + val = s->a; + break; + case VIA_REG_DIRB: + val = s->dirb; + break; + case VIA_REG_DIRA: + val = s->dira; + break; + case VIA_REG_T1CL: + val = get_counter(s, &s->timers[0]) & 0xff; + s->ifr &= ~T1_INT; + mos6522_update_irq(s); + break; + case VIA_REG_T1CH: + val = get_counter(s, &s->timers[0]) >> 8; + mos6522_update_irq(s); + break; + case VIA_REG_T1LL: + val = s->timers[0].latch & 0xff; + break; + case VIA_REG_T1LH: + /* XXX: check this */ + val = (s->timers[0].latch >> 8) & 0xff; + break; + case VIA_REG_T2CL: + val = get_counter(s, &s->timers[1]) & 0xff; + s->ifr &= ~T2_INT; + mos6522_update_irq(s); + break; + case VIA_REG_T2CH: + val = get_counter(s, &s->timers[1]) >> 8; + break; + case VIA_REG_SR: + val = s->sr; + s->ifr &= ~(SR_INT | CB1_INT | CB2_INT); + mos6522_update_irq(s); + break; + case VIA_REG_ACR: + val = s->acr; + break; + case VIA_REG_PCR: + val = s->pcr; + break; + case VIA_REG_IFR: + val = s->ifr; + if (s->ifr & s->ier) { + val |= 0x80; + } + break; + case VIA_REG_IER: + val = s->ier | 0x80; + break; + default: + case VIA_REG_ANH: + val = s->anh; + break; + } + + if (addr != VIA_REG_IFR || val != 0) { + trace_mos6522_read(addr, val); + } + + return val; +} + +void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + MOS6522State *s = opaque; + MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s); + + trace_mos6522_write(addr, val); + + switch (addr) { + case VIA_REG_B: + s->b = (s->b & ~s->dirb) | (val & s->dirb); + mdc->portB_write(s); + break; + case VIA_REG_A: + s->a = (s->a & ~s->dira) | (val & s->dira); + mdc->portA_write(s); + break; + case VIA_REG_DIRB: + s->dirb = val; + break; + case VIA_REG_DIRA: + s->dira = val; + break; + case VIA_REG_T1CL: + s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T1CH: + s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); + s->ifr &= ~T1_INT; + set_counter(s, &s->timers[0], s->timers[0].latch); + break; + case VIA_REG_T1LL: + s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T1LH: + s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); + s->ifr &= ~T1_INT; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_T2CL: + s->timers[1].latch = (s->timers[1].latch & 0xff00) | val; + break; + case VIA_REG_T2CH: + /* To ensure T2 generates an interrupt on zero crossing with the + common timer code, write the value directly from the latch to + the counter */ + s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8); + s->ifr &= ~T2_INT; + set_counter(s, &s->timers[1], s->timers[1].latch); + break; + case VIA_REG_SR: + s->sr = val; + break; + case VIA_REG_ACR: + s->acr = val; + mos6522_timer_update(s, &s->timers[0], + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + break; + case VIA_REG_PCR: + s->pcr = val; + break; + case VIA_REG_IFR: + /* reset bits */ + s->ifr &= ~val; + mos6522_update_irq(s); + break; + case VIA_REG_IER: + if (val & IER_SET) { + /* set bits */ + s->ier |= val & 0x7f; + } else { + /* reset bits */ + s->ier &= ~val; + } + mos6522_update_irq(s); + break; + default: + case VIA_REG_ANH: + s->anh = val; + break; + } +} + +static const MemoryRegionOps mos6522_ops = { + .read = mos6522_read, + .write = mos6522_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static bool mos6522_timer_exist(void *opaque, int version_id) +{ + MOS6522Timer *s = opaque; + + return s->timer != NULL; +} + +static const VMStateDescription vmstate_mos6522_timer = { + .name = "mos6522_timer", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT16(latch, MOS6522Timer), + VMSTATE_UINT16(counter_value, MOS6522Timer), + VMSTATE_INT64(load_time, MOS6522Timer), + VMSTATE_INT64(next_irq_time, MOS6522Timer), + VMSTATE_TIMER_PTR_TEST(timer, MOS6522Timer, mos6522_timer_exist), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_mos6522 = { + .name = "mos6522", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8(a, MOS6522State), + VMSTATE_UINT8(b, MOS6522State), + VMSTATE_UINT8(dira, MOS6522State), + VMSTATE_UINT8(dirb, MOS6522State), + VMSTATE_UINT8(sr, MOS6522State), + VMSTATE_UINT8(acr, MOS6522State), + VMSTATE_UINT8(pcr, MOS6522State), + VMSTATE_UINT8(ifr, MOS6522State), + VMSTATE_UINT8(ier, MOS6522State), + VMSTATE_UINT8(anh, MOS6522State), + VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 1, + vmstate_mos6522_timer, MOS6522Timer), + VMSTATE_END_OF_LIST() + } +}; + +static void mos6522_reset(DeviceState *dev) +{ + MOS6522State *s = MOS6522(dev); + + s->b = 0; + s->a = 0; + s->dirb = 0xff; + s->dira = 0; + s->sr = 0; + s->acr = 0; + s->pcr = 0; + s->ifr = 0; + s->ier = 0; + /* s->ier = T1_INT | SR_INT; */ + s->anh = 0; + + s->timers[0].latch = 0xffff; + set_counter(s, &s->timers[0], 0xffff); + + s->timers[1].latch = 0xffff; +} + +static void mos6522_realize(DeviceState *dev, Error **errp) +{ + MOS6522State *s = MOS6522(dev); + + s->timers[0].frequency = s->frequency; + s->timers[1].frequency = s->frequency; +} + +static void mos6522_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + MOS6522State *s = MOS6522(obj); + int i; + + memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10); + sysbus_init_mmio(sbd, &s->mem); + sysbus_init_irq(sbd, &s->irq); + + for (i = 0; i < ARRAY_SIZE(s->timers); i++) { + s->timers[i].index = i; + } + + s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s); + s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s); +} + +static Property mos6522_properties[] = { + DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void mos6522_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); + + dc->realize = mos6522_realize; + dc->reset = mos6522_reset; + dc->vmsd = &vmstate_mos6522; + dc->props = mos6522_properties; + mdc->parent_realize = dc->realize; + mdc->set_sr_int = mos6522_set_sr_int; + mdc->portB_write = mos6522_portB_write; + mdc->portA_write = mos6522_portA_write; + mdc->get_timer1_counter_value = mos6522_get_counter_value; + mdc->get_timer2_counter_value = mos6522_get_counter_value; + mdc->get_timer1_load_time = mos6522_get_load_time; + mdc->get_timer2_load_time = mos6522_get_load_time; +} + +static const TypeInfo mos6522_type_info = { + .name = TYPE_MOS6522, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MOS6522State), + .instance_init = mos6522_init, + .abstract = true, + .class_size = sizeof(MOS6522DeviceClass), + .class_init = mos6522_class_init, +}; + +static void mos6522_register_types(void) +{ + type_register_static(&mos6522_type_info); +} + +type_init(mos6522_register_types) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index e6070f280d..b340d4e81c 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -70,3 +70,10 @@ msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status regist #hw/misc/imx7_gpr.c imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx + +# hw/misc/mos6522.c +mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" +mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64 +mos6522_set_sr_int(void) "set sr_int" +mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 +mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h new file mode 100644 index 0000000000..a53c161b00 --- /dev/null +++ b/include/hw/misc/mos6522.h @@ -0,0 +1,152 @@ +/* + * QEMU MOS6522 VIA emulation + * + * Copyright (c) 2004-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MOS6522_H +#define MOS6522_H + +#include "exec/memory.h" +#include "hw/sysbus.h" +#include "hw/ide/internal.h" +#include "hw/input/adb.h" + +/* Bits in ACR */ +#define SR_CTRL 0x1c /* Shift register control bits */ +#define SR_EXT 0x0c /* Shift on external clock */ +#define SR_OUT 0x10 /* Shift out if 1 */ + +/* Bits in IFR and IER */ +#define IER_SET 0x80 /* set bits in IER */ +#define IER_CLR 0 /* clear bits in IER */ + +#define CA2_INT 0x01 +#define CA1_INT 0x02 +#define SR_INT 0x04 /* Shift register full/empty */ +#define CB2_INT 0x08 +#define CB1_INT 0x10 +#define T2_INT 0x20 /* Timer 2 interrupt */ +#define T1_INT 0x40 /* Timer 1 interrupt */ + +/* Bits in ACR */ +#define T1MODE 0xc0 /* Timer 1 mode */ +#define T1MODE_CONT 0x40 /* continuous interrupts */ + +/* VIA registers */ +#define VIA_REG_B 0x00 +#define VIA_REG_A 0x01 +#define VIA_REG_DIRB 0x02 +#define VIA_REG_DIRA 0x03 +#define VIA_REG_T1CL 0x04 +#define VIA_REG_T1CH 0x05 +#define VIA_REG_T1LL 0x06 +#define VIA_REG_T1LH 0x07 +#define VIA_REG_T2CL 0x08 +#define VIA_REG_T2CH 0x09 +#define VIA_REG_SR 0x0a +#define VIA_REG_ACR 0x0b +#define VIA_REG_PCR 0x0c +#define VIA_REG_IFR 0x0d +#define VIA_REG_IER 0x0e +#define VIA_REG_ANH 0x0f + +/** + * MOS6522Timer: + * @counter_value: counter value at load time + */ +typedef struct MOS6522Timer { + int index; + uint16_t latch; + uint16_t counter_value; + int64_t load_time; + int64_t next_irq_time; + uint64_t frequency; + QEMUTimer *timer; +} MOS6522Timer; + +/** + * MOS6522State: + * @b: B-side data + * @a: A-side data + * @dirb: B-side direction (1=output) + * @dira: A-side direction (1=output) + * @sr: Shift register + * @acr: Auxiliary control register + * @pcr: Peripheral control register + * @ifr: Interrupt flag register + * @ier: Interrupt enable register + * @anh: A-side data, no handshake + * @last_b: last value of B register + * @last_acr: last value of ACR register + */ +typedef struct MOS6522State { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion mem; + /* VIA registers */ + uint8_t b; + uint8_t a; + uint8_t dirb; + uint8_t dira; + uint8_t sr; + uint8_t acr; + uint8_t pcr; + uint8_t ifr; + uint8_t ier; + uint8_t anh; + + MOS6522Timer timers[2]; + uint64_t frequency; + + qemu_irq irq; +} MOS6522State; + +#define TYPE_MOS6522 "mos6522" +#define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522) + +typedef struct MOS6522DeviceClass { + DeviceClass parent_class; + + DeviceRealize parent_realize; + void (*set_sr_int)(MOS6522State *dev); + void (*portB_write)(MOS6522State *dev); + void (*portA_write)(MOS6522State *dev); + /* These are used to influence the CUDA MacOS timebase calibration */ + uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti); + uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti); + uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti); + uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti); +} MOS6522DeviceClass; + +#define MOS6522_DEVICE_CLASS(cls) \ + OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522) +#define MOS6522_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522) + +uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size); +void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size); + +#endif /* MOS6522_H */