From patchwork Sat Feb 10 01:38:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZWP3bPSz9s7f for ; Sat, 10 Feb 2018 12:45:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752167AbeBJBnt (ORCPT ); Fri, 9 Feb 2018 20:43:49 -0500 Received: from mout.perfora.net ([74.208.4.197]:53511 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751087AbeBJBnq (ORCPT ); Fri, 9 Feb 2018 20:43:46 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0MFaXj-1eWLUw3PnB-00Ebkq; Sat, 10 Feb 2018 02:38:16 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/6] arm: tegra: apalis-tk1: set critical trips Date: Sat, 10 Feb 2018 02:38:01 +0100 Message-Id: <20180210013806.28496-2-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:SqSLnO3YejxxAFcuVAbb4AmAGp5i0tWs+awj+4DXEFqke2dAEcU RE+H7xixerBRmB3M4ApNJYfvYOynRmZ/6l9AutOIVPuiHexqE5H7SxFqSKlpgP9wLxdmK04 h1XB1NPvn5ihz0pkK80zDIS2luqr3avPiyG6tXG91J3hS07DR8UEPSn2oz8QFfK/26bA18T t8NDvULsd89hEkTMx90bg== X-UI-Out-Filterresults: notjunk:1; V01:K0:F3uqRVSdY+U=:1CzV+1f8CTmuFQxOX1roIC P1WBB4gg3flUWnye6dCvCPpYxknV7WBdXoJzzCgzj6/nSaSfpC5PRkh2BHczTL7g27cmTYNQF Y118it/K/TXGUQ1q8AFYmausnLIghkQi0TxW0jTtWawiHyFYhmIHN+Sj84veNqTvDfEzT8M2u YwYCyMZhrRupuCIw6Keu/SRl6KsrlRDZ+yeBKN1DeAF3Qh//wpDvkg+ujw9bhB/tNkafqIDyC rIeJXF5v+qDMZvgaFEM4uYg1j21GbV9lOOgycFL/d1lW/wURCLuqMn95Kri5zd/pWyXLa18cS RH4oxG24d2WL5pmUgl77oS8lBOn3rJyyFMGkudAvAhduRYPF009s3fJgyc7C3jNuG08K6j8ce HcJ8a/O2ZLQe/dLbc6/5qHVKFHTwj7Y6ZbzdkBy2X42zZG/m4D4KrQq1D5ygeNvToD7etH+Qb Y1rOHLe832YZB+7c6V6MvFiPUL2at0DxerJJ6AiV0Q38ex6N+x5o1DHNjZEsEO5wBByuxJsRU d9ZvfqtJZaLfxqD9dO8TRkRPhot0x9ApmXC05sJI7y5yAHUhFAMR/bXRme1+GFMJarY8/ia12 k+Bpvw7SIeK8q5VlOBHiaaus69qefbo4oSuXbEkm3sERUgYKR6/EG/abz9UFbqUgyvivAkkPi lrZgp/3jNTdJRssYpbQb8R8w2xS6Rqt7DrdQXKmZXnXKttyX8WwumZVXu0wMxh9nB7QwumPL0 LuCpf4AME0qaAvVAi5TY4sb9fAzeCmJ1p0JRXA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler Set "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones. These trips can trigger shut down or reset. Similar to commit 40823f8e267f ("arm: tegra: set critical trips for Tegra124"). Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis.dtsi | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 7aef8928e115..be45b6753916 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2041,53 +2041,32 @@ thermal-zones { cpu { trips { - trip@0 { + cpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; mem { trips { - trip@0 { + mem-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; gpu { trips { - trip@0 { + gpu-shutdown-trip { temperature = <101000>; hysteresis = <0>; type = "critical"; }; }; - - cooling-maps { - /* - * There are currently no cooling maps because - * there are no cooling devices - */ - }; }; }; }; From patchwork Sat Feb 10 01:38:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZVq1KTKz9sDB for ; Sat, 10 Feb 2018 12:44:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752086AbeBJBnu (ORCPT ); Fri, 9 Feb 2018 20:43:50 -0500 Received: from mout.perfora.net ([74.208.4.197]:50701 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751053AbeBJBnq (ORCPT ); Fri, 9 Feb 2018 20:43:46 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0LwYI5-1elG3J00Kd-018N6M; Sat, 10 Feb 2018 02:38:18 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/6] ARM: dts: tegra: apalis-tk1: activate pwm pin muxing for pwm3 Date: Sat, 10 Feb 2018 02:38:02 +0100 Message-Id: <20180210013806.28496-3-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:xdLOrEuIzP2AmnCHfynM9E/x2E80LwZaQybJ1rHqjzNTQKOKRDY pwXEdxGdQTlGya2bjbRg980o4bLJ///ixuTY9tUjJZr5OSNLzuwfKth+/nFvCIGLwn76gd4 f91jGLN+Ghx6N961IxKJscZviioqvpxzffKKq+Huis/TMFCMGDnPETEm3Nmtv67aSCUpDWf IitW7kuFYqu7mb8ngP8+Q== X-UI-Out-Filterresults: notjunk:1; V01:K0:z2RndCEv/1s=:7l04btBKAwH55x/cY9KWvB kCp2SJl0TcwDS9SiaasxnTw+0cBTM0KbdqPX1uhSIDgZUvAIalNQqKZ3ZlZ+5KOB5kfg8e5VC torFwbtcNHhZ0yxdnl5trP7iJENVmbOoRirYiGfDtMXaggnAARMAGRjx91JJL80pz2Ij14H8P cPz3eA35t5u9Fm8tJYi10MWGVni81nEMLxqKZDcjLhDoRO8zgEoKN+V6+DxY0Iy41ljOYTC7L LLoyCO6JGcIo1I2iTQSzYEM7tNtpt66TfPkgLrz5tIrSTWs4bqXfMZK0A2b5ziohLMNmz+UTC OhcaPOFqR1QA6m7fiH5TImkR4un0Hh8gHg6YDP6k/yGQ70GnvcLyW76ZUh///RebGcHvTwLri QSUfpJSg/89VKHIA9dcezua7T3aXIDEfdkEZQfm938+ISgIkxFhsgSvpg850IfkAtNTtnzZKG KcoalJ5hV5iHXzYVMLu0ePIH/MqW1d9LTh8l8h0/9qoKXk7D1ipA4yx3if+0RLA0zy5tqBrnG hWLa3bFoB9eqW9JIrLqdaZmJql9bIfWL0moj0vKjVtalmjw1XyylswMBuVXXOTgs9bM4qQ71m HS+h6Ta1RadHuFmoOLSgCKqyeFyihhd4+E6mY9CX53T+cYUFrqMY9+9+6Y7VvtS+sV5bRkoEc ALzvSm7pmoAH/JpTxmkYjaUqHElI8CQ1GKoEG4/hDIi7k82bh9Ugdg78bc8jG8Gv3OYPgB+xE wi3avXem1TpJm1b2MelcTmA3hiELcXocTOid/g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler Activate PWM pin muxing for Apalis PWM3. Note that the same PWM3 is already active on pu6 being Apalis BKL1_PWM as well. Therefore exporting that one for raw sysfs access will fail and one has to revert to using the pwm backlight. Downstream commit 668ddb921800 ("apalis-tk1: activate pwm pin muxing for pwm3"). Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index be45b6753916..7fbaaf221029 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -453,12 +453,12 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - /* PWM3 active on pu6 being Apalis BKL1_PWM */ + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ ph3 { nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; nvidia,enable-input = ; }; From patchwork Sat Feb 10 01:38:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871619 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZTY6n04z9rxj for ; Sat, 10 Feb 2018 12:43:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751031AbeBJBnp (ORCPT ); Fri, 9 Feb 2018 20:43:45 -0500 Received: from mout.perfora.net ([74.208.4.196]:50729 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751003AbeBJBno (ORCPT ); Fri, 9 Feb 2018 20:43:44 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0LZxCl-1f7r6X11Rd-00llm0; Sat, 10 Feb 2018 02:38:20 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/6] ARM: dts: tegra: apalis-tk1: add missing as3722 gpio0 configuration Date: Sat, 10 Feb 2018 02:38:03 +0100 Message-Id: <20180210013806.28496-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:FQCRpJ63UOZD+pIhM5iivJMBISPsYCSlvsCAUg6w3LJ0QIJ5MI4 DvPkps0wdZSfYb++bFFW1+VraQ7A/yXO4flr0x2UP9DNVZz7GgDfHAROFHGx7pEJIF5UkFi tPGyIVruzF3fcDX4bwtFfw7Z3+0cjH0DhAPE89QFoSA/1/LH9tr9AXZdpffyXDHKLyZlRHZ hiHnpBGBHvd7hgc+Fh3Ig== X-UI-Out-Filterresults: notjunk:1; V01:K0:HV/fQQ2UpjE=:p9qluWJruJhCSlBy5XRLED FayxGtJIvgpes4SgiDdyQyzEL3KMbdBfT7dI7U1GRAg2AQrCiIj2+0B6fVOojJXVyW4GQRyBb AF1bPPiwQ1EU2cqXt+BzGhhzpJ6D7IA/TmgEQimRVlOdzj2CZdHgHXBQmppdrYnpS829a+OjG qNahu6fj9Fq8Uacl3ggIIKRLsk6sjb8vKLqjOSXxoNX1pRtTLlxfv377/2e2qgrvEZco/8gSb yn1Xy/UZMVE8cPN0UhIUgW/fUozgKPjYHkxyDpv0FpiJ6Ik1fe+DASwgH762S61O8iQ12tk1v QK44KVh740WsEeETs1wcNOlYMAoHzKX6RhrsSyKeiByYJkua5HNeeP3C8u/oD+oNVrDmqBysb FA3MkIF0+jcd/i8MY/P2+UaLpk/UUnZUOeVnQouMScFDig/4bchkW4DKHDtWi0TxNugjTPUQA clfibgEdgwtuXW4RDDZ5XXd15L/1G34yhccaAbU+gnKYHz1NITuG0tIfzTceLfiFZETFxEQq3 5vdx0l2IaZbW5J1TQKmBh6f70AProjaOm9ewwEi6IzO0WuGlTj3Bl0O+yn0OAjX5+7kI7Roaa c6W47n6KVE6GyJ2mmItJF1BYvvV0pon66OaZPPIXJE/2xhcJvNmkumsz4PIn6gICNvDxBqV0n 22KRrFVIA3iSlCpG/lb4gCt5Xwi/14xYq8kUn/+CduhiPOzFTdCvD8yM2zLhNJNqbR3gGsLV+ o1ir4/eVMjqBro6AniywrsQfEZRDNClxvgtCzQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 7fbaaf221029..44c31176ce90 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1620,9 +1620,9 @@ bias-pull-up; }; - gpio1_3_4_5_6 { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6"; + gpio0_1_3_4_5_6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; bias-high-impedance; }; }; From patchwork Sat Feb 10 01:38:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZVN3cYYz9rxj for ; Sat, 10 Feb 2018 12:44:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752528AbeBJBoF (ORCPT ); Fri, 9 Feb 2018 20:44:05 -0500 Received: from mout.perfora.net ([74.208.4.197]:37797 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752172AbeBJBoD (ORCPT ); Fri, 9 Feb 2018 20:44:03 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0MCrG1-1ebHi9250V-009gKo; Sat, 10 Feb 2018 02:38:23 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: tegra: apalis-tk1: hog group for ethernet, pcie, reset gpios Date: Sat, 10 Feb 2018 02:38:04 +0100 Message-Id: <20180210013806.28496-5-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:M3fmOvleO9n6WsFexiZLkA2W5ROjyWQlO+xNbgadPe6J7NQNF6C ngsQ7WXlMjlHjpM55ZQGY0xVlSxDFltb5ZaSYt43h8EsfwOIuPnsPyI+/7ypBaOTFkT5tb/ R7HBJIEmN+3EoH4lPwaTWOeH71X6AIFQAklqK1osOu0VqVJdI6rn7dAGpDayiugHksVJ1wH /vAph89vAtXPaed337Q5g== X-UI-Out-Filterresults: notjunk:1; V01:K0:1vWfnneh4Lg=:j0CLIPZtbBrrURrtBi4lEM ePXWQlRp3Rw3d8S8IxZrno68B4zRelg/GojWL/tk/L+7ENoMBjv7cXp+BjKl934ei5jvEldfv qWbN91CcdndZ/jZNTC2g4AiU+151o8Qjx9IGBaRUR6ufR7VFepBicLAp67/nNSWkQE8hORMB/ S3Lw5qRKqkDB2Lyzgg8kAAPr+BFzU7b/UbWegkoiWuYqVaWL2rvz46S7Ikrq6lKEx9oeGatYP yJVrBo6YhSUeKzvdIP5rP8oNH9ooHs4xXs5ZvR2RCCkU5LyryuR2PjzjT4r3jKS403BN2WtRr /GzPFpZLXXwhIDrICtfQbgbP5X5fnSFmFmTY5MWMIVHKLTdiW0/NE/0i4McsYQPciIcViXdlw KkHo5CVzD8HkJjiN9MvAhCL6jgylPESuqZgI+Tm4DDsCdpvcv3TR+aayO1fmVHeDWfA3MS5ft U0qvlFc6kz8bJONe58v7JGn7UWaMjfb+8/Mo6QnHs0fWlQcACURkAh8jY/CwYC0EwxPkxN0pJ K8vhDI0NtEN0N7GvSsnnINEeslC94HUkMdca6oPGXbLkeS9XNI8T3e6FRxE8ZcpjzTNrMo/xO 0cJhMKR+I7ab6aH20wIRQL3JG1c4WLK4DZmZ7AUOwz5leTOhJwyfq/iELGpC0+8egpQd+5DDf /QG87ACKzOhoevBI0pgT4Zbva+G+pfzFv/s6iYhhcvTM/TjbfUWJdjUqOr/uFn/Hbx7mCvED6 S7yY0xg/iYhhSf+N7WE5vifJHn9KVMMw7iQ1IA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler The Apalis TK1 module uses some dedicated GPIOs as I210 gigabit Ethernet controller reset and to control RESET_MOCI aka reset module output carrier input on MXM3 pin 26. The Apalis Evaluation Board furthermore uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 10 ++++++++++ arch/arm/boot/dts/tegra124-apalis.dtsi | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index af6c566e8ac4..f1010cefb993 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -275,3 +275,13 @@ vin-supply = <®_5v0>; }; }; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex_perst_n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index 44c31176ce90..b7648ce4565d 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -2070,3 +2070,21 @@ }; }; }; + +&gpio { + /* I210 Gigabit Ethernet Controller Reset */ + lan_reset_n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset_moci_ctrl { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; +}; From patchwork Sat Feb 10 01:38:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871620 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZVC6CHLz9rxj for ; Sat, 10 Feb 2018 12:44:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752227AbeBJBoG (ORCPT ); Fri, 9 Feb 2018 20:44:06 -0500 Received: from mout.perfora.net ([74.208.4.194]:48063 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751371AbeBJBoC (ORCPT ); Fri, 9 Feb 2018 20:44:02 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0LmMC4-1fJ6yQ32yA-00ZuSx; Sat, 10 Feb 2018 02:38:25 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/6] ARM: dts: tegra: apalis-tk1: copyright period, spurious newlines Date: Sat, 10 Feb 2018 02:38:05 +0100 Message-Id: <20180210013806.28496-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:R3OSbxibVpFqYTawGU60tTb2Oud7LLVhLLRQdFmUmdWWyZe6GKN tW5aj1jzAZwiOd1aci5BSZX0fOoWFB90flelGVHDocwXARKh/Z8P8NZNMQVLWRCrofmHrOM /BW8tU17r+rhRtmt5h8IMQxgvpXF7cg4cNoDesWq+VDtktGp34HHU7kURkOmFVBEMDVLgpp SvTbXyeszfEqoPVq8Jv6Q== X-UI-Out-Filterresults: notjunk:1; V01:K0:oGv7YX/3SIM=:o+Osqv2N5SJjUQeMyTW/x8 eyus1Uynewfu+d+/amPDX2/GrjDhm+HYcZsrQc/dNXNh2NRHCqn6vtnRe6vu/2IfPKXlJmK4E 7/5uv/tXJyhXY1ioxWLgFpEuGCcdQxVaQ53NBdbNdpG55MOkPlECiuC4p+RvPEx2p/4yDYxx1 z8EKYEhUjket6RefQAXVHQfYdlNahZw9gtPhUGW+cp2TNBhDVrU8uzpc+7TLmdM5goVwT3chq hqnTgyZN/U7qNUfFhQ2JmOKjpUveDq6+uwxyxJnqJW52wdEVdp2mgo+SUc1vJpHlWmjkIf6kl s2O6zuHHXAZ+wQoMs2dTszxZWO44ir9pAAgldMrIFMF8SBprNq64ZDjggxwKcX2Rp30OmbDYM dGDNrDwAWSk14tZA5RiQDI9+OrG0stKvHgh47BOy/KFHgbbLzXH9c3Am40lO12/eQmkf/POtu /Ibd/Yd1T4CeaMzgUK7lxZh5iuxn4CGcW/v6bPy0D4iToCiK5L9f9P+S70aKgRSVt4jyBwIFt mCmXxXJi9s8Ruma62BQUAXRfvyolCG4d5UbYGtXGB9K5bf4XcokYR4/ueddajOpAbYFd9z+J5 /oGHIgJxf+RQqnGamCOoxVW6VXSX5IUaOqju+Qowc/eJQ2FSD0DILsDeHJZxzqoagohIE/nHm VpMPf3SZ/oNbu7ZyoHt+yea5/hO0Js5HA/JGbGkLf9ZM3jOT7KCozbpIBLQRZy+0QiTXoXzbb j0QaFIdXiOnT+r+FvhcorxV3o/HwGK0kKYwE0w== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler Update the copyright period and get rid of some spurious newlines. Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/tegra124-apalis-eval.dts | 6 ++---- arch/arm/boot/dts/tegra124-apalis.dtsi | 11 +---------- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index f1010cefb993..a6ad759dddb4 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2018 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -225,9 +225,7 @@ backlight: backlight { compatible = "pwm-backlight"; - - /* BKL1_PWM */ - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ brightness-levels = <255 231 223 207 191 159 127 0>; default-brightness-level = <6>; /* BKL1_ON */ diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index b7648ce4565d..65a2161b9b8e 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -1,5 +1,5 @@ /* - * Copyright 2016 Toradex AG + * Copyright 2016-2018 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -56,7 +56,6 @@ pcie@1003000 { status = "okay"; - avddio-pex-supply = <&vdd_1v05>; avdd-pex-pll-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; @@ -85,7 +84,6 @@ hdmi@54280000 { pll-supply = <®_1v05_avdd_hdmi_pll>; vdd-supply = <®_3v3_avdd_hdmi>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; @@ -1600,15 +1598,11 @@ compatible = "ams,as3722"; reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - ams,system-power-controller; - #interrupt-cells = <2>; interrupt-controller; - gpio-controller; #gpio-cells = <2>; - pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; @@ -1783,7 +1777,6 @@ reg = <0x4c>; interrupt-parent = <&gpio>; interrupts = ; - #thermal-sensor-cells = <1>; }; }; @@ -1816,7 +1809,6 @@ sata@70020000 { phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; phy-names = "sata-0"; - avdd-supply = <&vdd_1v05>; hvdd-supply = <®_3v3>; vddio-supply = <&vdd_1v05>; @@ -1830,7 +1822,6 @@ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; - avddio-pex-supply = <&vdd_1v05>; avdd-pll-erefe-supply = <&avdd_1v05>; avdd-pll-utmip-supply = <&vddio_1v8>; From patchwork Sat Feb 10 01:38:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 871625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdZWK2dmrz9sQm for ; Sat, 10 Feb 2018 12:45:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751550AbeBJBpA (ORCPT ); Fri, 9 Feb 2018 20:45:00 -0500 Received: from mout.perfora.net ([74.208.4.196]:55383 "EHLO mout.perfora.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751128AbeBJBoz (ORCPT ); Fri, 9 Feb 2018 20:44:55 -0500 Received: from localhost.localdomain.ziswiler.net ([178.38.65.171]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPA (Nemesis) id 0MejGQ-1eM46N06Tw-00OHR3; Sat, 10 Feb 2018 02:38:27 +0100 From: Marcel Ziswiler To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Cc: Marcel Ziswiler , Thierry Reding , Jonathan Hunter , linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH 6/6] ARM: dts: tegra: apalis-tk1: support v1.2 hardware revision Date: Sat, 10 Feb 2018 02:38:06 +0100 Message-Id: <20180210013806.28496-7-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180210013806.28496-1-marcel@ziswiler.com> References: <20180210013806.28496-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:aVZ7gUQhuuB1PVdSTGc2OVfBdOH8i64mPFYZa2jDNf0QM9tjt69 qn+8y74XiINSJFa9j7FK90Hu2NIx8GwTYdBi7tlaPpxhmxDALvLEJ96/nRNXdNYMmRWb+/q wxL4hMt639aDYNy7h8virCLWxz4qcUSjmA5TlqRgpmvnINxkt4Lhy1R94eIza1clOtg+apD sS3d62CCIBbD/32Twc/sQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:g2QtvJVYOZg=:YbSBCo+lgKP65OBOW4usWy IgbhnVGZLWAKxp+ikzzSm0+HRxCVHms9oDrRHcD/1DYWwWcTmA8Q6BRyksSUjLwMi9Iw8cHlm UmseeIn0mcG5DAkl19IcWmYKtEb9j6ZnaDuBt8GF94pI3CM09KtRX4P8KOgBV2VFKOQw2r4q1 acOwFCIRiZ+4g3Gcp9m8Dd0a6D5K0vZZlBQ4pJxeRGLdwSCQPM8mpPGLn6iEPrniXaN5BEkDk nMqzvC8Mqn5jnU06QTUBqa3Clgo9clRmrH94fa6NMFOJ6HWyUuB8Q29xawZDfc/+It78vLrkU vUYQi2pUyDHT7jQ3lXsrqFukK2mKB6LvY1qs0H8bTuhCqW7Zeb03Px0A2Hxf+08QHu/BuTJl7 1COL8Xms/OhcJLIh438JJyAsPq/ilWooLXtic1pbTy0taS7BvCWvqYoQw+eMGAriJRqwd8XWv gY4fRpzJYlreuk3KWJa4Dc9l6jMcxU8z0Fet0+XGK0D4zY2/EZUu/7bqlL4scmu3QAfDX+VLn N9VxG6mrWh7jJCWbHecZy1867snpmYaka4NPRqaRElZGOEenMPpNZqmC2pNBOSkRPIFAMRqx5 v6hla7SS2nHOZqlSrYxJubYXe1Q4OrHcyZv82FM2N5iCdm0UDlrlGgYlGE4h3raTxRt0YRIun jIHdrtJyH6hA+yx/NKzjRo3nlN2MeJV36gxHh7gQyXabzvj553ux09IctybWUWq/D/Jfk4dwh TfNK+R4kF0OEPBlsPq4OtStdW90dhiHGcySQdw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Marcel Ziswiler Support the V1.2 hardware revision with the following pin muxing changes: Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 are now used as DDC pins. Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are now used as USB power enable signals. Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power enable signals are now used as GPIO3 and GPIO4. Signed-off-by: Marcel Ziswiler --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 250 +++ arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2052 +++++++++++++++++++++++ 3 files changed, 2303 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ade7a38543dc..9d882741f0da 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1022,6 +1022,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-tn7.dtb dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-apalis-eval.dtb \ + tegra124-apalis-v1.2-eval.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-nyan-blaze.dtb \ diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts new file mode 100644 index 000000000000..8a8d5fa0ecd1 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016-2018 Toradex AG + */ + +/dts-v1/; + +#include +#include "tegra124-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis TK1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", + "toradex,apalis-tk1", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@7000c000/rtc@68"; + rtc1 = "/i2c@7000d000/pmic@40"; + rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pcie@1003000 { + pci@1,0 { + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + }; + }; + + /* Apalis UART1 */ + serial@70006000 { + status = "okay"; + }; + + /* Apalis UART2 */ + serial@70006040 { + status = "okay"; + }; + + /* Apalis UART3 */ + serial@70006200 { + status = "okay"; + }; + + /* Apalis UART4 */ + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + /* + * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier + * board) + */ + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + pcie-switch@58 { + compatible = "plx,pex8605"; + reg = <0x58>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + }; + + /* GEN2_I2C: unused */ + + /* + * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor + * on carrier board) + */ + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + /* + * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 + * (e.g. display EDID) + */ + hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + + /* SPI1: Apalis SPI1 */ + spi@7000d400 { + status = "okay"; + spi-max-frequency = <50000000>; + + spidev0: spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /* SPI4: Apalis SPI2 */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <50000000>; + + spidev1: spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + /* Apalis Serial ATA */ + sata@70020000 { + status = "okay"; + }; + + hda@70030000 { + status = "okay"; + }; + + usb@70090000 { + status = "okay"; + }; + + /* Apalis MMC1 */ + sdhci@700b0000 { + status = "okay"; + /* MMC1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc1>; + }; + + /* Apalis SD1 */ + sdhci@700b0400 { + status = "okay"; + /* SD1_CD# */ + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + bus-width = <4>; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <®_usbo1_vbus>; + }; + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <®_usbh_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 3 5000000>; /* BKL1_PWM */ + brightness-levels = <255 231 223 207 191 159 127 0>; + default-brightness-level = <6>; + /* BKL1_ON */ + enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup { + label = "WAKE1_MICO"; + gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* USBO1_EN */ + reg_usbo1_vbus: regulator-usbo1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBO1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; + + /* USBH_EN */ + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_5v0>; + }; +}; + +&gpio { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex_perst_n { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; +}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi new file mode 100644 index 000000000000..bb67edb016c5 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -0,0 +1,2052 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016-2018 Toradex AG + */ + +#include "tegra124.dtsi" +#include "tegra124-apalis-emc.dtsi" + +/* + * Toradex Apalis TK1 Module Device Tree + * Compatible for Revisions 2GB: V1.2A + */ +/ { + model = "Toradex Apalis TK1"; + compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", + "nvidia,tegra124"; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pcie@1003000 { + status = "okay"; + avddio-pex-supply = <&vdd_1v05>; + avdd-pex-pll-supply = <&vdd_1v05>; + avdd-pll-erefe-supply = <&avdd_1v05>; + dvddio-pex-supply = <&vdd_1v05>; + hvdd-pex-pll-e-supply = <®_3v3>; + hvdd-pex-supply = <®_3v3>; + vddio-pex-ctl-supply = <®_3v3>; + + /* Apalis PCIe (additional lane Apalis type specific) */ + pci@1,0 { + /* PCIE1_RX/TX and TS_DIFF1/2 */ + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; + phy-names = "pcie-0", "pcie-1"; + }; + + /* I210 Gigabit Ethernet Controller (On-module) */ + pci@2,0 { + phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; + status = "okay"; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + pll-supply = <®_1v05_avdd_hdmi_pll>; + vdd-supply = <®_3v3_avdd_hdmi>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + + pinmux: pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* Analogue Audio (On-module) */ + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_ON */ + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis BKL1_PWM */ + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis CAM1_MCLK */ + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis Digital Audio */ + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "hda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb3 { /* DAP1_RESET */ + nvidia,pins = "pbb3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis GPIO */ + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis HDMI1_CEC */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis HDMI1_HPD */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis I2C1 */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C3 (CAM) */ + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis I2C4 (DDC) */ + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + + /* Apalis MMC1 */ + sdmmc1_cd_n_pv3 { /* CD# GPIO */ + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { /* D5 GPIO */ + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { /* D4 GPIO */ + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { /* D7 GPIO */ + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis PWM */ + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SATA1_ACT# */ + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SD1 */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { /* CD# GPIO */ + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPDIF */ + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI1 */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis SPI2 */ + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART1 */ + pb1 { /* DCD GPIO */ + nvidia,pins = "pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { /* RI GPIO */ + nvidia,pins = "pk7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_txd_pu0 { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_rxd_pu1 { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_cts_n_pu2 { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart1_rts_n_pu3 { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { /* DSR GPIO */ + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { /* DTR GPIO */ + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART2 */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART3 */ + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis UART4 */ + uart4_rxd_pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart4_txd_pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBH_EN */ + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBH_OC# */ + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis USBO1_EN */ + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* Apalis USBO1_OC# */ + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Apalis WAKE1_MICO */ + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE_PWR_REQ */ + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CPU_PWR_REQ */ + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* DVFS */ + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* eMMC */ + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* JTAG_RTCK */ + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_DEV_OFF# */ + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_RESET# */ + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LAN_WAKE# */ + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT1# */ + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT2# */ + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT3# */ + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_INT4# */ + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU_RESET */ + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MCU SPI */ + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { /* MCU_CS */ + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w2_aud_pw2 { /* MCU_CSEZP */ + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CLK_32K */ + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PMIC_CPU_OC_INT */ + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWR_I2C */ + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* PWR_INT_N */ + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_MOCI_CTRL */ + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* RESET_OUT_N */ + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_IN */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Configure level-shifter as output for HDA */ + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_DIR_OUT */ + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SHIFT_CTRL_OE */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* TOUCH_INT */ + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pc7 { /* NC */ + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { /* NC */ + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { /* NC */ + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { /* NC */ + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { /* NC */ + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { /* NC */ + nvidia,pins = "pg4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { /* NC */ + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { /* NC */ + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { /* NC */ + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { /* NC */ + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { /* NC */ + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { /* NC */ + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { /* NC */ + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { /* NC */ + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { /* NC */ + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { /* NC */ + nvidia,pins = "pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { /* NC */ + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { /* NC */ + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { /* NC */ + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { /* NC */ + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { /* NC */ + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { /* NC */ + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { /* NC */ + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { /* NC */ + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { /* NC */ + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { /* NC */ + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { /* NC */ + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { /* NC */ + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { /* NC */ + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { /* NC */ + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { /* NC */ + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { /* NC */ + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { /* NC */ + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { /* NC */ + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { /* NC */ + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { /* NC */ + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { /* NC */ + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { /* NC */ + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { /* NC */ + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { /* NC */ + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { /* NC */ + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { /* NC */ + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { /* NC */ + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { /* NC */ + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { /* NC */ + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { /* NC */ + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { /* NC */ + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * PCB Version Indication: V1.2 and later have GPIO_PV0 + * wired to GND, was NC before + */ + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { /* NC */ + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { /* NC */ + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { /* NC */ + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { /* NC */ + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { /* NC */ + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { /* NC */ + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { /* NC */ + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { /* NC */ + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + /* + * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output + * driver enabled aka not tristated and input driver + * enabled as well as it features some magic properties + * even though the external loopback is disabled and the + * internal loopback used as per + * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 + * bits being set to 0xfffd according to the TRM! + */ + sdmmc3_clk_lb_out_pee4 { /* NC */ + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + serial@70006040 { + compatible = "nvidia,tegra124-hsuart"; + }; + + serial@70006200 { + compatible = "nvidia,tegra124-hsuart"; + }; + + serial@70006300 { + compatible = "nvidia,tegra124-hsuart"; + }; + + hdmi_ddc: i2c@7000c700 { + clock-frequency = <10000>; + }; + + /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* SGTL5000 audio codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <&vddio_1v8>; + clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; + }; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + ams,system-power-controller; + #interrupt-cells = <2>; + interrupt-controller; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio2_7 { + pins = "gpio2", /* PWR_EN_+V3.3 */ + "gpio7"; /* +V1.6_LPO */ + function = "gpio"; + bias-pull-up; + }; + + gpio0_1_3_4_5_6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + + regulators { + vsup-sd2-supply = <®_3v3>; + vsup-sd3-supply = <®_3v3>; + vsup-sd4-supply = <®_3v3>; + vsup-sd5-supply = <®_3v3>; + vin-ldo0-supply = <&vddio_ddr_1v35>; + vin-ldo1-6-supply = <®_3v3>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <®_3v3>; + vin-ldo9-10-supply = <®_3v3>; + vin-ldo11-supply = <®_3v3>; + + vdd_cpu: sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vddio_ddr_1v35: sd2 { + regulator-name = + "+V1.35_VDDIO_DDR(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = + "+V1.35_VDDIO_DDR(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05: sd4 { + regulator-name = "+V1.05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_gpu: sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + avdd_1v05: ldo0 { + regulator-name = "+V1.05_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + vddio_sdmmc1: ldo1 { + regulator-name = "VDDIO_SDMMC1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "+V1.2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+V1.05_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + /* 1.8V for LVDS, 3.3V for eDP */ + ldo4 { + regulator-name = "AVDD_LVDS0_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* LDO5 not used */ + + vddio_sdmmc3: ldo6 { + regulator-name = "VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + /* LDO7 not used */ + + ldo9 { + regulator-name = "+V3.3_ETH(ldo9)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo10 { + regulator-name = "+V3.3_ETH(ldo10)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo11 { + regulator-name = "+V1.8_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + /* + * TMP451 temperature sensor + * Note: THERM_N directly connected to AS3722 PMIC THERM + */ + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + #thermal-sensor-cells = <1>; + }; + }; + + /* SPI2: MCU SPI */ + spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + /* Set power_off bit in ResetControl register of AS3722 PMIC */ + i2c-thermtrip { + nvidia,i2c-controller-id = <4>; + nvidia,bus-addr = <0x40>; + nvidia,reg-addr = <0x36>; + nvidia,reg-data = <0x2>; + }; + }; + + sata@70020000 { + phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; + phy-names = "sata-0"; + avdd-supply = <&vdd_1v05>; + hvdd-supply = <®_3v3>; + vddio-supply = <&vdd_1v05>; + }; + + usb@70090000 { + /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, + <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; + phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; + avddio-pex-supply = <&vdd_1v05>; + avdd-pll-erefe-supply = <&avdd_1v05>; + avdd-pll-utmip-supply = <&vddio_1v8>; + avdd-usb-ss-pll-supply = <&vdd_1v05>; + avdd-usb-supply = <®_3v3>; + dvddio-pex-supply = <&vdd_1v05>; + hvdd-usb-ss-pll-e-supply = <®_3v3>; + hvdd-usb-ss-supply = <®_3v3>; + }; + + padctl@7009f000 { + pads { + usb2 { + status = "okay"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + pcie { + status = "okay"; + + lanes { + pcie-0 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-1 { + nvidia,function = "usb3-ss"; + status = "okay"; + }; + + pcie-2 { + nvidia,function = "pcie"; + status = "okay"; + }; + + pcie-3 { + nvidia,function = "pcie"; + status = "okay"; + }; + + pcie-4 { + nvidia,function = "pcie"; + status = "okay"; + }; + }; + }; + + sata { + status = "okay"; + + lanes { + sata-0 { + nvidia,function = "sata"; + status = "okay"; + }; + }; + }; + }; + + ports { + /* USBO1 */ + usb2-0 { + status = "okay"; + mode = "otg"; + + vbus-supply = <®_usbo1_vbus>; + }; + + /* USBH2 */ + usb2-1 { + status = "okay"; + mode = "host"; + + vbus-supply = <®_usbh_vbus>; + }; + + /* USBH4 */ + usb2-2 { + status = "okay"; + mode = "host"; + + vbus-supply = <®_usbh_vbus>; + }; + + usb3-0 { + nvidia,usb2-companion = <2>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + }; + }; + + /* eMMC */ + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + /* CPU DFLL clock */ + clock@70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + + ahub@70300000 { + i2s@70301200 { + status = "okay"; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + cpus { + cpu@0 { + vdd-cpu-supply = <&vdd_cpu>; + }; + }; + + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { + compatible = "regulator-fixed"; + regulator-name = "+V1.05_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05>; + }; + + reg_3v3_mxm: regulator-3v3-mxm { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_MXM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + /* PWR_EN_+V3.3 */ + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3_mxm>; + }; + + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_HDMI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_1v05>; + }; + + sound { + compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", + "nvidia,tegra-audio-sgtl5000"; + nvidia,model = "Toradex Apalis TK1"; + nvidia,audio-routing = + "Headphone Jack", "HP_OUT", + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack"; + nvidia,i2s-controller = <&tegra_i2s2>; + nvidia,audio-codec = <&sgtl5000>; + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + cpu { + trips { + cpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem { + trips { + mem-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu { + trips { + gpu-shutdown-trip { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&gpio { + /* I210 Gigabit Ethernet Controller Reset */ + lan_reset_n { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset_moci_ctrl { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; +};