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(localhost [IPv6:::1]) by gnu-tgl-3.localdomain (Postfix) with ESMTP id E986FC068A; Fri, 24 Dec 2021 13:22:42 -0800 (PST) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2] i386: Check AX input in any_mul_highpart peepholes Date: Fri, 24 Dec 2021 13:22:42 -0800 Message-Id: <20211224212242.27161-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Spam-Status: No, score=-3029.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: Roger Sayle Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" When applying peephole optimization to transform mov imm, %reg0 mov %reg1, %AX_REG imul %reg0 to mov imm, %AX_REG imul %reg1 disable peephole optimization if reg1 == AX_REG as in (set (reg:SI 1 dx [92]) (const_int 714200473 [0x2a91d599])) (set (reg:SI 0 ax [105]) (reg:SI 0 ax [orig:89 k ] [89])) (parallel [ (set (reg:SI 1 dx [91]) (smul_highpart:SI (reg:SI 0 ax [105]) (reg:SI 1 dx [92]))) (clobber (reg:SI 0 ax [105])) (clobber (reg:CC 17 flags)) ]) PR bootstrap/103785 * config/i386/i386.md: Swap operand order in comments and check AX input in any_mul_highpart peepholes. --- gcc/config/i386/i386.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 58b10643fcb..72e6486a92f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8552,7 +8552,7 @@ (set_attr "mode" "SI")]) ;; Highpart multiplication peephole2s to tweak register allocation. -;; mov %rdx,imm; mov %rax,%rdi; imulq %rdx -> mov %rax,imm; imulq %rdi +;; mov imm,%rdx; mov %rdi,%rax; imulq %rdx -> mov imm,%rax; imulq %rdi (define_peephole2 [(set (match_operand:SWI48 0 "general_reg_operand") (match_operand:SWI48 1 "immediate_operand")) @@ -8562,7 +8562,8 @@ (any_mul_highpart:SWI48 (match_dup 2) (match_dup 0))) (clobber (match_dup 2)) (clobber (reg:CC FLAGS_REG))])] - "REGNO (operands[0]) != REGNO (operands[2]) + "REGNO (operands[3]) != AX_REG + && REGNO (operands[0]) != REGNO (operands[2]) && REGNO (operands[0]) != REGNO (operands[3]) && (REGNO (operands[0]) == REGNO (operands[4]) || peep2_reg_dead_p (3, operands[0]))" @@ -8582,7 +8583,9 @@ (any_mul_highpart:SI (match_dup 2) (match_dup 0)))) (clobber (match_dup 2)) (clobber (reg:CC FLAGS_REG))])] - "REGNO (operands[0]) != REGNO (operands[2]) + "REGNO (operands[3]) != AX_REG + && REGNO (operands[0]) != REGNO (operands[2]) + && REGNO (operands[2]) != REGNO (operands[3]) && REGNO (operands[0]) != REGNO (operands[3]) && (REGNO (operands[0]) == REGNO (operands[4]) || peep2_reg_dead_p (3, operands[0]))"