From patchwork Fri Feb 9 16:57:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 871477 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="goaqqwRM"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="GwVPKTMb"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zdLpn2rDgz9s7g for ; Sat, 10 Feb 2018 03:57:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752274AbeBIQ5t (ORCPT ); Fri, 9 Feb 2018 11:57:49 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34434 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752230AbeBIQ5r (ORCPT ); Fri, 9 Feb 2018 11:57:47 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A8AA460A06; Fri, 9 Feb 2018 16:57:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518195466; bh=6qg26uLj5NziFLniHpDBIcYJleg2+WhTdkgjp33oLU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=goaqqwRMn7rQPKH0CyvwhVUayOXr5Jb6KODNljbRAniB3AM035x3k24WoWL7JOQbr rtnTN44gKdREed1KwsacPvItR84hbrlt10Y8WUgP8sKEHzWT+3/SIqSHT8gaHfQoV7 +dWgEzCjv+WjVlLvNTgjJDq6I+/ZgUO/wRyJ/B1U= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 07F6F60A4E; Fri, 9 Feb 2018 16:57:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518195465; bh=6qg26uLj5NziFLniHpDBIcYJleg2+WhTdkgjp33oLU0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GwVPKTMbEpEOrbA64YbQetdD5V3lyS0bAaT12Jw6PV6sFz+tNRCTh5LQHrEDPeTek Wg8fQSVMw3F75tO+TqrrY9e5Fu1+GdnhFCSXbhP/VrPr+HTZoJ2GGO471vJ+lJpOqZ KTHlIDFKCzCMfjX4FJwmKQDX0igQAClATnzB0tiE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 07F6F60A4E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH v6 2/2] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Date: Fri, 9 Feb 2018 09:57:35 -0700 Message-Id: <20180209165735.19151-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180209165735.19151-1-ilina@codeaurora.org> References: <20180209165735.19151-1-ilina@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Archana Sathyakumar Add device binding documentation for the PDC Interrupt controller on QCOM SoC's like the SDM845. The interrupt-controller can be used to sense edge low interrupts and wakeup interrupts when the GIC is non-operational. Cc: devicetree@vger.kernel.org Signed-off-by: Archana Sathyakumar Signed-off-by: Lina Iyer Reviewed-by: Rob Herring --- .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt new file mode 100644 index 000000000000..0b2c97ddb520 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -0,0 +1,78 @@ +PDC interrupt controller + +Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a +Power Domain Controller (PDC) that is on always-on domain. In addition to +providing power control for the power domains, the hardware also has an +interrupt controller that can be used to help detect edge low interrupts as +well detect interrupts when the GIC is non-operational. + +GIC is parent interrupt controller at the highest level. Platform interrupt +controller PDC is next in hierarchy, followed by others. Drivers requiring +wakeup capabilities of their device interrupts routed through the PDC, must +specify PDC as their interrupt controller and request the PDC port associated +with the GIC interrupt. See example below. + +Properties: + +- compatible: + Usage: required + Value type: + Definition: Should contain "qcom,-pdc" + - "qcom,sdm845-pdc": For SDM845 + +- reg: + Usage: required + Value type: + Definition: Specifies the base physical address for PDC hardware. + +- interrupt-cells: + Usage: required + Value type: + Definition: Specifies the number of cells needed to encode an interrupt + source. + Must be 2. + The first element of the tuple is the PDC pin for the + interrupt. + The second element is the trigger type. + +- interrupt-parent: + Usage: required + Value type: + Definition: Specifies the interrupt parent necessary for hierarchical + domain to operate. + +- interrupt-controller: + Usage: required + Value type: + Definition: Identifies the node as an interrupt controller. + +- qcom,pdc-ranges: + Usage: required + Value type: + Definition: Specifies the PDC pin offset and the number of PDC ports. + The tuples indicates the valid mapping of valid PDC ports + and their hwirq mapping. + The first element of the tuple is the starting PDC port. + The second element is the GIC hwirq number for the PDC port. + The third element is the number of interrupts in sequence. + +Example: + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + +DT binding of a device that wants to use the GIC SPI 514 as a wakeup +interrupt, must do - + + wake-device { + interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; + }; + +In this case interrupt 514 would be mapped to port 2 on the PDC as defined by +the qcom,pdc-ranges property.