From patchwork Fri Feb 9 09:48:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 871289 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="h/3DLLfU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zd9HM71Sbz9s1h for ; Fri, 9 Feb 2018 20:48:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750993AbeBIJsa (ORCPT ); Fri, 9 Feb 2018 04:48:30 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:39150 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750924AbeBIJs2 (ORCPT ); Fri, 9 Feb 2018 04:48:28 -0500 Received: by mail-pg0-f68.google.com with SMTP id w17so3278309pgv.6; Fri, 09 Feb 2018 01:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=7nu2rrbnJSxPyPy0j9WEjXVGZ3C2tsgJNpI07BgAWoU=; b=h/3DLLfUsaJ/ZOGf9Iq4cctVOqsxOfb0c/3xVNf4P2hx+N8Ao6fqkQc90qdi751K6W QBZ/35egnPyRzx52gV3XUwkuKR1PNuBGV4TW7SZRo9KN3IR1X+o8tQRAqcpiL2KTfxQb C1TSqzvo6hoQm6xmL91g0pejyA8I0uALdLNvfnozU9V08DZGafIy+hSmPFjjgaobLiFH AchOjwhpUenLsItcQB7muGr8LZ/HUdPBPWPlIUN+0nEUxuwEjJByLGPQeSO2i1c1bj8V 8WL0qKL8ItzWejp32sVGu+Owt4C3WtNHLT+3xINGMOgobez9KjomI+quKMX5ov49scKn 3mxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=7nu2rrbnJSxPyPy0j9WEjXVGZ3C2tsgJNpI07BgAWoU=; b=hjlO9ZfW5MvfvgnX/3yIOC85epkqEhJbi9K4nXbyOCp2+jIX1f4Kb9Hp2kuTvBvjrv CKzQnRjKultKchpYEEGy7jY6J6PQ7i4aDqi27VyKh7zOF4na33z4ZsnHKXpH/f4Otnxj SaMGJLAIiQ9WYVmwDXz3J7FlV5eTZyrZ87UsUqCnkhfsOzU8UEMj7AmIQSOy0W4jPSoQ MPF89K9svnRVvFgAqwCWaGj3zehzjnY4bkduWwRspx/QzQxjnRKS7iejzPcQ0iwByl6F X9hYf2aZF/aScAmiQWV4oml3Cqfo7sjO8iZ7cN3p0e4sBdwUL21dyrj4mLQCfsRTMIGL wuRg== X-Gm-Message-State: APf1xPCPZkDXtN06N83MWJZy27J4BRiW8nEGqx5ZdAnwDn19pu8RbM9B xko1R4Js0zOe1Ey4eh0pwU20/w== X-Google-Smtp-Source: AH8x226vc2Ol6fre152NrCS5h9xCfJ0WgQ/z3/LzHZ3T5Mx8bZIx1kjUjwHbfgtLlp4RD4vrevIIjA== X-Received: by 10.98.32.157 with SMTP id m29mr2263109pfj.182.1518169708221; Fri, 09 Feb 2018 01:48:28 -0800 (PST) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id b8sm5745205pfl.129.2018.02.09.01.48.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 01:48:27 -0800 (PST) From: Chunyan Zhang To: Stephen Boyd , Rob Herring Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [PATCH 1/2] dt-bindings: clocks: add APB RTC gate for SC9860 Date: Fri, 9 Feb 2018 17:48:10 +0800 Message-Id: <1518169691-14870-1-git-send-email-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Chunyan Zhang Added index of RTC gate clocks which are used by some devices on aon area of SC9860, for example the Watchdog timer. Signed-off-by: Chunyan Zhang Reviewed-by: Rob Herring --- include/dt-bindings/clock/sprd,sc9860-clk.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h index 4cb202f..f2ab463 100644 --- a/include/dt-bindings/clock/sprd,sc9860-clk.h +++ b/include/dt-bindings/clock/sprd,sc9860-clk.h @@ -229,7 +229,26 @@ #define CLK_SDIO1_2X_EN 65 #define CLK_SDIO2_2X_EN 66 #define CLK_EMMC_2X_EN 67 -#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1) +#define CLK_ARCH_RTC_EB 68 +#define CLK_KPB_RTC_EB 69 +#define CLK_AON_SYST_RTC_EB 70 +#define CLK_AP_SYST_RTC_EB 71 +#define CLK_AON_TMR_RTC_EB 72 +#define CLK_AP_TMR0_RTC_EB 73 +#define CLK_EIC_RTC_EB 74 +#define CLK_EIC_RTCDV5_EB 75 +#define CLK_AP_WDG_RTC_EB 76 +#define CLK_AP_TMR1_RTC_EB 77 +#define CLK_AP_TMR2_RTC_EB 78 +#define CLK_DCXO_TMR_RTC_EB 79 +#define CLK_BB_CAL_RTC_EB 80 +#define CLK_AVS_BIG_RTC_EB 81 +#define CLK_AVS_LIT_RTC_EB 82 +#define CLK_AVS_GPU0_RTC_EB 83 +#define CLK_AVS_GPU1_RTC_EB 84 +#define CLK_GPU_TS_EB 85 +#define CLK_RTCDV10_EB 86 +#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) #define CLK_LIT_MCU 0 #define CLK_BIG_MCU 1