From patchwork Thu Feb 8 16:20:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870925 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zck6r58s0z9s72 for ; Fri, 9 Feb 2018 03:24:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5DE57C21EE5; Thu, 8 Feb 2018 16:21:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3F71C21E74; Thu, 8 Feb 2018 16:21:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3015CC21DFA; Thu, 8 Feb 2018 16:21:33 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id BD05FC21DFA for ; Thu, 8 Feb 2018 16:21:32 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GJ6oB018490; Thu, 8 Feb 2018 17:21:31 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fw4uj3drd-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:31 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0C9F438; Thu, 8 Feb 2018 16:21:31 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E8CF4A6F7; Thu, 8 Feb 2018 16:21:30 +0000 (GMT) Received: from localhost (10.75.127.51) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:30 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:45 +0100 Message-ID: <1518106851-18106-2-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG6NODE1.st.com (10.75.127.16) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 1/7] clk: clk_stm32f: Fix stm32_clk_get_rate() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Wrong parameter was passed to stm32_clk_pll48clk_rate(). sysclk (PLL_p output value) was passed instead of VCO value. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index f1f02995d9c0..41d8b5e5c88a 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -230,7 +230,7 @@ static int configure_clocks(struct udevice *dev) } static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, - u32 sysclk) + u32 vco) { struct stm32_rcc_regs *regs = priv->base; u16 pllq, pllm, pllsain, pllsaip; @@ -254,7 +254,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } /* PLL48CLK is selected from PLLQ */ - return sysclk / pllq; + return vco / pllq; } static bool stm32_get_timpre(struct stm32_clk *priv) @@ -337,6 +337,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_clk *priv = dev_get_priv(clk->dev); struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; + u32 vco; u16 pllm, plln, pllp; if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == @@ -346,7 +347,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); - sysclk = ((priv->hse_rate / pllm) * plln) / pllp; + vco = (priv->hse_rate / pllm) * plln; + sysclk = vco / pllp; } else { return -EINVAL; } @@ -388,14 +390,14 @@ static ulong stm32_clk_get_rate(struct clk *clk) /* System clock is selected as SDMMC1 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break; case STM32F7_APB2_CLOCK(SDMMC2): if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) /* System clock is selected as SDMMC2 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break; /* For timer clock, an additionnal prescaler is used*/ From patchwork Thu Feb 8 16:20:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870926 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zck6s4Knrz9s75 for ; Fri, 9 Feb 2018 03:24:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 562CCC21EB4; Thu, 8 Feb 2018 16:22:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 141B6C21EC2; Thu, 8 Feb 2018 16:21:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 86E92C21E2C; Thu, 8 Feb 2018 16:21:34 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 3EDE6C21CB1 for ; Thu, 8 Feb 2018 16:21:34 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GJJmn004965; Thu, 8 Feb 2018 17:21:32 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fw3qx399b-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:32 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B114931; Thu, 8 Feb 2018 16:21:31 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9DAD9A6F7; Thu, 8 Feb 2018 16:21:31 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:31 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:46 +0100 Message-ID: <1518106851-18106-3-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 2/7] clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 41d8b5e5c88a..7d89906379af 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -55,8 +55,8 @@ #define RCC_CFGR_PPRE1_SHIFT 10 #define RCC_CFGR_PPRE2_SHIFT 13 -#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) -#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) +#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) @@ -247,9 +247,9 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, if (pllsai) { /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) + pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); - pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) + pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } From patchwork Thu Feb 8 16:20:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870924 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zck6D5X9Lz9s72 for ; Fri, 9 Feb 2018 03:24:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6FD42C21ECE; Thu, 8 Feb 2018 16:22:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4600FC21E70; Thu, 8 Feb 2018 16:21:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 96A3EC21CB1; Thu, 8 Feb 2018 16:21:34 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 40FF6C21DFA for ; Thu, 8 Feb 2018 16:21:34 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GKAkI007557; Thu, 8 Feb 2018 17:21:33 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fya26cuf7-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7FEE834; Thu, 8 Feb 2018 16:21:32 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 69A7FA6F7; Thu, 8 Feb 2018 16:21:32 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:32 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:47 +0100 Message-ID: <1518106851-18106-4-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG7NODE1.st.com (10.75.127.19) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 3/7] clk: clk_stm32f: No more need of 48Mhz from PLL_SAI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Initially, 48Mhz for SDIO clock was generated from SAI pll for STM32F469 and STM32F746 SoCs, but this solution was not suitable for STM32F429 SoCs. A generic solution is to used the PLL_Q output as 48Mhz clock for all STM32F SOCs family. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 29 ++++++++--------------------- 1 file changed, 8 insertions(+), 21 deletions(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 7d89906379af..e8f6b47acc17 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -128,7 +128,6 @@ static int configure_clocks(struct udevice *dev) struct stm32_rcc_regs *regs = priv->base; struct stm32_pwr_regs *pwr = priv->pwr_regs; struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; - u32 pllsaicfgr = 0; /* Reset RCC configuration */ setbits_le32(®s->cr, RCC_CR_HSION); @@ -160,20 +159,10 @@ static int configure_clocks(struct udevice *dev) clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); - /* Configure the SAI PLL to get a 48 MHz source */ - pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | - RCC_PLLSAICFGR_PLLSAIP_4; - pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; - writel(pllsaicfgr, ®s->pllsaicfgr); - - /* Enable the main PLL */ - setbits_le32(®s->cr, RCC_CR_PLLON); - while (!(readl(®s->cr) & RCC_CR_PLLRDY)) - ; - + /* configure SDMMC clock */ if (priv->info.v2) { /*stm32f7 case */ - /* select PLLSAI as 48MHz clock source */ - setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); + /* select PLLQ as 48MHz clock source */ + clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); /* select 48MHz as SDMMC1 clock source */ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); @@ -181,16 +170,16 @@ static int configure_clocks(struct udevice *dev) /* select 48MHz as SDMMC2 clock source */ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); } else { /* stm32f4 case */ - /* select PLLSAI as 48MHz clock source */ - setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); + /* select PLLQ as 48MHz clock source */ + clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); /* select 48MHz as SDMMC1 clock source */ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); } - /* Enable the SAI PLL */ - setbits_le32(®s->cr, RCC_CR_PLLSAION); - while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) + /* Enable the main PLL */ + setbits_le32(®s->cr, RCC_CR_PLLON); + while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); @@ -218,8 +207,6 @@ static int configure_clocks(struct udevice *dev) while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) ; - /* gate the SAI clock, needed for MMC 1&2 clocks */ - setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); #ifdef CONFIG_ETH_DESIGNWARE /* gate the SYSCFG clock, needed to set RMII ethernet interface */ From patchwork Thu Feb 8 16:20:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870934 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zck9R6QWPz9s72 for ; Fri, 9 Feb 2018 03:26:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 9C217C21E30; Thu, 8 Feb 2018 16:22:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5F2F0C21EB1; Thu, 8 Feb 2018 16:21:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 78641C21ED9; Thu, 8 Feb 2018 16:21:37 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id ED3D6C21E30 for ; Thu, 8 Feb 2018 16:21:34 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GKBVa007564; Thu, 8 Feb 2018 17:21:33 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fya26cuf9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 54B5031; Thu, 8 Feb 2018 16:21:33 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2D5FBA6F7; Thu, 8 Feb 2018 16:21:33 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:32 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:48 +0100 Message-ID: <1518106851-18106-5-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 4/7] clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Rework the way SDMMC clock get rate is done in a more generic way : _ Add stm32_clk_get_pllsai_rate() which give the PLLSAI indicated output rate. _ Add stm32_clk_get_pllsai_vco_rate() which give the VCO internal rate. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 105 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 74 insertions(+), 31 deletions(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index e8f6b47acc17..a687e2acd406 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -57,8 +57,12 @@ #define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6) #define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16) +#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24) +#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 +#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24 +#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) @@ -87,6 +91,12 @@ #define RCC_APB2ENR_SYSCFGEN BIT(14) #define RCC_APB2ENR_SAI1EN BIT(22) +enum pllsai_div { + PLLSAIP, + PLLSAIQ, + PLLSAIR, +}; + static const struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { @@ -216,32 +226,57 @@ static int configure_clocks(struct udevice *dev) return 0; } -static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, - u32 vco) +static bool stm32_clk_get_ck48msel(struct stm32_clk *priv) { struct stm32_rcc_regs *regs = priv->base; - u16 pllq, pllm, pllsain, pllsaip; - bool pllsai; - - pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) - >> RCC_PLLCFGR_PLLQ_SHIFT; if (priv->info.v2) /*stm32f7 case */ - pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; + return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; else - pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; - if (pllsai) { - /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ - pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); - pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) - >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); - pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIP_MASK) - >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); - return ((priv->hse_rate / pllm) * pllsain) / pllsaip; + return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; +} + +static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv) +{ + struct stm32_rcc_regs *regs = priv->base; + u16 pllm, pllsain; + + pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK) + >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); + + return ((priv->hse_rate / pllm) * pllsain); +} + +static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv, + enum pllsai_div output) +{ + struct stm32_rcc_regs *regs = priv->base; + u16 pll_div_output; + + switch (output) { + case PLLSAIP: + pll_div_output = ((((readl(®s->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIP_MASK) + >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); + break; + case PLLSAIQ: + pll_div_output = (readl(®s->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIQ_MASK) + >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT; + break; + case PLLSAIR: + pll_div_output = (readl(®s->pllsaicfgr) + & RCC_PLLSAICFGR_PLLSAIR_MASK) + >> RCC_PLLSAICFGR_PLLSAIR_SHIFT; + break; + default: + pr_err("incorrect PLLSAI output %d\n", output); + return -EINVAL; } - /* PLL48CLK is selected from PLLQ */ - return vco / pllq; + + return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output); } static bool stm32_get_timpre(struct stm32_clk *priv) @@ -325,7 +360,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; u32 vco; - u16 pllm, plln, pllp; + u32 sdmmcxsel_bit; + u16 pllm, plln, pllp, pllq; if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) { @@ -334,6 +370,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); + pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) + >> RCC_PLLCFGR_PLLQ_SHIFT); vco = (priv->hse_rate / pllm) * plln; sysclk = vco / pllp; } else { @@ -366,25 +404,30 @@ static ulong stm32_clk_get_rate(struct clk *clk) /* APB2 CLOCK */ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + switch (clk->id) { /* * particular case for SDMMC1 and SDMMC2 : * 48Mhz source clock can be from main PLL or from - * SAI PLL + * PLLSAIP */ - switch (clk->id) { case STM32F7_APB2_CLOCK(SDMMC1): - if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) - /* System clock is selected as SDMMC1 clock */ - return sysclk; - else - return stm32_clk_pll48clk_rate(priv, vco); - break; case STM32F7_APB2_CLOCK(SDMMC2): - if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) - /* System clock is selected as SDMMC2 clock */ + if (clk->id == STM32F7_APB2_CLOCK(SDMMC1)) + sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL; + else + sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL; + + if (readl(®s->dckcfgr2) & sdmmcxsel_bit) + /* System clock is selected as SDMMC1 clock */ return sysclk; + /* + * 48 MHz can be generated by either PLLSAIP + * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR + */ + if (stm32_clk_get_ck48msel(priv)) + return stm32_clk_get_pllsai_rate(priv, PLLSAIP); else - return stm32_clk_pll48clk_rate(priv, vco); + return (vco / pllq); break; /* For timer clock, an additionnal prescaler is used*/ From patchwork Thu Feb 8 16:20:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870937 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zckBs59YVz9s72 for ; Fri, 9 Feb 2018 03:28:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 68BF3C21ECE; Thu, 8 Feb 2018 16:23:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1FE70C21EF1; Thu, 8 Feb 2018 16:21:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1E7ACC21E5D; Thu, 8 Feb 2018 16:21:39 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 820ADC21E5B for ; Thu, 8 Feb 2018 16:21:35 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GKBVb007564; Thu, 8 Feb 2018 17:21:34 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2fya26cufd-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:34 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F3DE838; Thu, 8 Feb 2018 16:21:33 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E1EF2A6F7; Thu, 8 Feb 2018 16:21:33 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:33 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:49 +0100 Message-ID: <1518106851-18106-6-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 5/7] clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Configure SAI PLL configuration to generate LTDC pixel clock on the PLLSAIR output. PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a687e2acd406..a11d6dc242ba 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -65,13 +65,17 @@ #define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) -#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) +#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28) #define RCC_DCKCFGRX_TIMPRE BIT(24) #define RCC_DCKCFGRX_CK48MSEL BIT(27) #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) +#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16 +#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16) +#define RCC_DCKCFGR_PLLSAIDIVR_2 0 + /* * RCC AHB1ENR specific definitions */ @@ -132,6 +136,8 @@ struct stm32_clk { unsigned long hse_rate; }; +static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 }; + static int configure_clocks(struct udevice *dev) { struct stm32_clk *priv = dev_get_priv(dev); @@ -187,11 +193,29 @@ static int configure_clocks(struct udevice *dev) clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); } +#ifdef CONFIG_VIDEO_STM32 + /* + * Configure the SAI PLL to generate LTDC pixel clock + */ + clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, + RCC_PLLSAICFGR_PLLSAIR_3); + clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK, + 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT); + + clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, + RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); +#endif /* Enable the main PLL */ setbits_le32(®s->cr, RCC_CR_PLLON); while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; +#ifdef CONFIG_VIDEO_STM32 +/* Enable the SAI PLL */ + setbits_le32(®s->cr, RCC_CR_PLLSAION); + while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) + ; +#endif setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); if (priv->info.has_overdrive) { @@ -361,6 +385,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) u32 sysclk = 0; u32 vco; u32 sdmmcxsel_bit; + u32 saidivr; + u32 pllsai_rate; u16 pllm, plln, pllp, pllq; if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == @@ -438,6 +464,15 @@ static ulong stm32_clk_get_rate(struct clk *clk) case STM32F7_APB2_CLOCK(TIM11): return stm32_get_timer_rate(priv, sysclk, APB2); break; + + /* particular case for LTDC clock */ + case STM32F7_APB2_CLOCK(LTDC): + saidivr = readl(®s->dckcfgr); + saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK) + >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT; + pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); + + return pllsai_rate / pllsaidivr_table[saidivr]; } return (sysclk >> stm32_get_apb_shift(regs, APB2)); From patchwork Thu Feb 8 16:20:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870936 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zckBQ3lHVz9s72 for ; Fri, 9 Feb 2018 03:27:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 307B0C21EC2; Thu, 8 Feb 2018 16:23:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 95EAAC21EDC; Thu, 8 Feb 2018 16:21:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3EFB7C21E2C; Thu, 8 Feb 2018 16:21:40 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 843B3C21EB1 for ; Thu, 8 Feb 2018 16:21:36 +0000 (UTC) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GIaeF028657; Thu, 8 Feb 2018 17:21:35 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fxmgpt0et-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:35 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D4BE734; Thu, 8 Feb 2018 16:21:34 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 98CDDA6F9; Thu, 8 Feb 2018 16:21:34 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:34 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:50 +0100 Message-ID: <1518106851-18106-7-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG7NODE2.st.com (10.75.127.20) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 6/7] clk: clk_stm32f: Add set_rate for LTDC clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Implement set_rate() for LTDC clock only, set_rate for other clocks will be added if needed. This is needed by future LTDC driver improvements. Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a11d6dc242ba..a683911ebf00 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -136,6 +136,9 @@ struct stm32_clk { unsigned long hse_rate; }; +#ifdef CONFIG_VIDEO_STM32 +static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 }; +#endif static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 }; static int configure_clocks(struct udevice *dev) @@ -484,7 +487,104 @@ static ulong stm32_clk_get_rate(struct clk *clk) static ulong stm32_set_rate(struct clk *clk, ulong rate) { +#ifdef CONFIG_VIDEO_STM32 + struct stm32_clk *priv = dev_get_priv(clk->dev); + struct stm32_rcc_regs *regs = priv->base; + u32 pllsair_rate, pllsai_vco_rate, current_rate; + u32 best_div, best_diff, diff; + u16 div; + u8 best_plldivr, best_pllsaidivr; + u8 i, j; + bool found = false; + + /* Only set_rate for LTDC clock is implemented */ + if (clk->id != STM32F7_APB2_CLOCK(LTDC)) { + pr_err("set_rate not implemented for clock index %ld\n", + clk->id); + return 0; + } + + if (rate == stm32_clk_get_rate(clk)) + /* already set to requested rate */ + return rate; + + /* get the current PLLSAIR output freq */ + pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR); + best_div = pllsair_rate / rate; + + /* look into pllsaidivr_table if this divider is available*/ + for (i = 0 ; i < sizeof(pllsaidivr_table); i++) + if (best_div == pllsaidivr_table[i]) { + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, + RCC_DCKCFGR_PLLSAIDIVR_MASK, + pllsaidivr_table[i]); + return rate; + } + + /* + * As no pllsaidivr value is suitable to obtain requested freq, + * test all combination of pllsaidivr * pllsair and find the one + * which give freq closest to requested rate. + */ + + pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv); + best_diff = ULONG_MAX; + best_pllsaidivr = 0; + best_plldivr = 0; + /* + * start at index 2 of plldivr_table as divider value at index 0 + * and 1 are 0) + */ + for (i = 2; i < sizeof(plldivr_table); i++) { + for (j = 0; j < sizeof(pllsaidivr_table); j++) { + div = plldivr_table[i] * pllsaidivr_table[j]; + current_rate = pllsai_vco_rate / div; + /* perfect combination is found ? */ + if (current_rate == rate) { + best_pllsaidivr = j; + best_plldivr = i; + found = true; + break; + } + + diff = (current_rate > rate) ? + current_rate - rate : rate - current_rate; + + /* found a better combination ? */ + if (diff < best_diff) { + best_diff = diff; + best_pllsaidivr = j; + best_plldivr = i; + } + } + + if (found) + break; + } + + /* Disable the SAI PLL */ + clrbits_le32(®s->cr, RCC_CR_PLLSAION); + + /* set pll_saidivr with found value */ + clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK, + best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT); + + /* set pllsair with found value */ + clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK, + plldivr_table[best_plldivr] + << RCC_PLLSAICFGR_PLLSAIR_SHIFT); + + /* Enable the SAI PLL */ + setbits_le32(®s->cr, RCC_CR_PLLSAION); + while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) + ; + + div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr]; + return pllsai_vco_rate / div; +#else return 0; +#endif } static int stm32_clk_enable(struct clk *clk) From patchwork Thu Feb 8 16:20:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 870938 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zckCH43dtz9s72 for ; Fri, 9 Feb 2018 03:28:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1E56FC21ED5; Thu, 8 Feb 2018 16:23:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BB55BC21EA6; Thu, 8 Feb 2018 16:23:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3B11EC21E8A; Thu, 8 Feb 2018 16:21:41 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 03323C21EBE for ; Thu, 8 Feb 2018 16:21:36 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w18GJckQ005361; Thu, 8 Feb 2018 17:21:36 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fw3qx399j-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 08 Feb 2018 17:21:36 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7965D38; Thu, 8 Feb 2018 16:21:35 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 68291A6F7; Thu, 8 Feb 2018 16:21:35 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 8 Feb 2018 17:21:35 +0100 From: To: , , , Date: Thu, 8 Feb 2018 17:20:51 +0100 Message-ID: <1518106851-18106-8-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> References: <1518106851-18106-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-08_08:, , signatures=0 Subject: [U-Boot] [PATCH 7/7] clk: clk_stm32f: Add DSI clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard DSI clock is available on STM32F769-disco and STM32F469-disco board. Signed-off-by: Yannick Fertre Signed-off-by: Patrice Chotard --- drivers/clk/clk_stm32f.c | 2 +- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index a683911ebf00..d8eab1a88d7c 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -432,7 +432,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) return (sysclk >> stm32_get_apb_shift(regs, APB1)); /* APB2 CLOCK */ - case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): + case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI): switch (clk->id) { /* * particular case for SDMMC1 and SDMMC2 : diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index 44c091449381..c9087f5f3dac 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -106,6 +106,7 @@ #define STM32F7_RCC_APB2_SAI1 22 #define STM32F7_RCC_APB2_SAI2 23 #define STM32F7_RCC_APB2_LTDC 26 +#define STM32F7_RCC_APB2_DSI 27 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)