From patchwork Thu Dec 9 17:24:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565955 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=WAGsYADC; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Bm59vgz9sR4 for ; Fri, 10 Dec 2021 04:25:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242942AbhLIR2v (ORCPT ); Thu, 9 Dec 2021 12:28:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242969AbhLIR2s (ORCPT ); Thu, 9 Dec 2021 12:28:48 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1C40C061A72 for ; Thu, 9 Dec 2021 09:25:09 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id p18so4778496wmq.5 for ; Thu, 09 Dec 2021 09:25:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=njc6iBCIIcJEfBBmmi88h1svGLtR5R9x889jLiMbnc4=; b=WAGsYADCPH1KHkzvwQI6PBwxpAwVi0sg9KYjGD9Mnjohc0nCcNbaihIhSH2PFnhp1U Pb+SejMJK7q3MB8zY+Jn3a1QoL9rqSp/APDKAbr805KlD45UAxDs2Ub8EfMs+lTJ8VkS YmYc+xghWinFcbaH2TodCCpYcAEBoqys9zW5ScU/TmkJkPe1THBXtlzfwy9Aq+vE68Z2 8dp+SUGEBLulz/vVYmYF5apr9Ow4FRCXnuKF87KYSuBeDVjXAwqnAKewmtV9W3AkkRXQ nX6YJWEWlv/GsqmVpEUgZQWMMI5K7Zr8qliQPlHL47gQDSce/NDHuaZyNnA0qDGDdUFr xkCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=njc6iBCIIcJEfBBmmi88h1svGLtR5R9x889jLiMbnc4=; b=uWmSTDnMoC2W3Cgz3N/vKNrFGJ5jhEUr4DYiOhx7A5DGlkIJnCWfaP2hKAz0rNIIrz TiA6ki9e6HIOEckjFgUb1Vx0x3DYeh59uPf8tmpvDZmromf82cThng5bxC5N4Bogb5p9 TiHyZO8i9LGt4NosL7gVuuzvOH9gfjZsUy57TWi3KydeZ72A7ONGXNZ6Rae8Sa75ecNN r7ysUQN6Le2PFlX6eVLRetmke7y6996ko2V3cirubdnFft/J84Ks3RhPRx33CdYRJpwL r5P6KxvHKqeBX12+dM5/np/2mt5LQBNSyomaXwE9y1V6dMeTxGum73QSu7PmnrpTzsgr JVCA== X-Gm-Message-State: AOAM530Ljk50ZpY39ynHSpQktYKERd1giUK/NpAYZ505iu5ueIo8cs4H uTid1sY5Ip43F7mS/qFGyoRcL976I6VsMQ== X-Google-Smtp-Source: ABdhPJyThK80AEu7SSCweDHmSi7AqXmLZm2c2cU6txy2arIRq+0RXb5lqHb29NlXmd/X54gddAzB1A== X-Received: by 2002:a1c:1f94:: with SMTP id f142mr9151132wmf.192.1639070708365; Thu, 09 Dec 2021 09:25:08 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l26sm439210wms.15.2021.12.09.09.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:07 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 01/30] arm64: tegra: Rename top-level clocks Date: Thu, 9 Dec 2021 18:24:34 +0100 Message-Id: <20211209172503.617716-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 8a51751526ee..ecd58bd2770f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1023,7 +1023,7 @@ backlight: backlight { default-brightness-level = <6>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6077d572d828..d3e622c4a439 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -301,7 +301,7 @@ mmc@700b0600 { vqmmc-supply = <&vdd_1v8>; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 58aa0518965e..0a70daeffd85 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -40,7 +40,7 @@ mmc@700b0600 { non-removable; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 41beab626d95..ed73c3a0c140 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1586,7 +1586,7 @@ mmc@700b0600 { status = "okay"; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 030f264eccd5..cbd8cda48f37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1645,7 +1645,7 @@ flash@0 { }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 131c064d6991..43ff5e4bda19 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1726,7 +1726,7 @@ interrupt-controller@702f9000 { }; }; - clk32k_in: clock@0 { + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; #clock-cells = <0>; From patchwork Thu Dec 9 17:24:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=VIE5t8eu; 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Thu, 09 Dec 2021 09:25:11 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id r8sm414304wrz.43.2021.12.09.09.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:10 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 02/30] arm64: tegra: Rename top-level regulators Date: Thu, 9 Dec 2021 18:24:35 +0100 Message-Id: <20211209172503.617716-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 26 +++++++------- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 6 ++-- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++--- .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 10 +++--- .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 30 ++++++++-------- .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 36 +++++++++---------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 18 +++++----- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 16 ++++----- 12 files changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index ecd58bd2770f..c84ed1cb9a8c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -1057,7 +1057,7 @@ panel: panel { ddc-i2c-bus = <&dpaux>; }; - vdd_mux: regulator@0 { + vdd_mux: regulator-vdd-mux { compatible = "regulator-fixed"; regulator-name = "+VDD_MUX"; regulator-min-microvolt = <19000000>; @@ -1066,7 +1066,7 @@ vdd_mux: regulator@0 { regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "+5V_SYS"; regulator-min-microvolt = <5000000>; @@ -1076,7 +1076,7 @@ vdd_5v0_sys: regulator@1 { vin-supply = <&vdd_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; @@ -1086,7 +1086,7 @@ vdd_3v3_sys: regulator@2 { vin-supply = <&vdd_mux>; }; - vdd_3v3_run: regulator@3 { + vdd_3v3_run: regulator-vdd-3v3-run { compatible = "regulator-fixed"; regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; @@ -1098,7 +1098,7 @@ vdd_3v3_run: regulator@3 { vin-supply = <&vdd_3v3_sys>; }; - vdd_3v3_hdmi: regulator@4 { + vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { compatible = "regulator-fixed"; regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; @@ -1106,7 +1106,7 @@ vdd_3v3_hdmi: regulator@4 { vin-supply = <&vdd_3v3_run>; }; - vdd_led: regulator@5 { + vdd_led: regulator-vdd-led { compatible = "regulator-fixed"; regulator-name = "+VDD_LED"; regulator-min-microvolt = <3300000>; @@ -1116,7 +1116,7 @@ vdd_led: regulator@5 { vin-supply = <&vdd_mux>; }; - vdd_usb1_vbus: regulator@6 { + vdd_usb1_vbus: regulator-vdd-usb1-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; @@ -1127,7 +1127,7 @@ vdd_usb1_vbus: regulator@6 { vin-supply = <&vdd_5v0_sys>; }; - vdd_usb3_vbus: regulator@7 { + vdd_usb3_vbus: regulator-vdd-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; @@ -1138,7 +1138,7 @@ vdd_usb3_vbus: regulator@7 { vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_panel: regulator@8 { + vdd_3v3_panel: regulator-vdd-3v3-panel { compatible = "regulator-fixed"; regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; @@ -1148,7 +1148,7 @@ vdd_3v3_panel: regulator@8 { vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi_pll: regulator@9 { + vdd_hdmi_pll: regulator-vdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; regulator-min-microvolt = <1050000>; @@ -1157,7 +1157,7 @@ vdd_hdmi_pll: regulator@9 { vin-supply = <&vdd_1v05_run>; }; - vdd_5v0_hdmi: regulator@10 { + vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { compatible = "regulator-fixed"; regulator-name = "+5V_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -1167,7 +1167,7 @@ vdd_5v0_hdmi: regulator@10 { vin-supply = <&vdd_5v0_sys>; }; - vdd_5v0_ts: regulator@11 { + vdd_5v0_ts: regulator-vdd-5v0-ts { compatible = "regulator-fixed"; regulator-name = "+5V_VDD_TS"; regulator-min-microvolt = <5000000>; @@ -1178,7 +1178,7 @@ vdd_5v0_ts: regulator@11 { enable-active-high; }; - vdd_3v3_lp0: regulator@12 { + vdd_3v3_lp0: regulator-vdd-3v3-lp0 { compatible = "regulator-fixed"; regulator-name = "+3.3V_LP0"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 52fa258533e6..2883049c4edf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -2250,7 +2250,7 @@ volume-down { }; }; - vdd_sd: regulator@100 { + vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "SD_CARD_SW_PWR"; regulator-min-microvolt = <3300000>; @@ -2262,7 +2262,7 @@ vdd_sd: regulator@100 { vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@101 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -2274,7 +2274,7 @@ vdd_hdmi: regulator@101 { vin-supply = <&vdd_5v0_sys>; }; - vdd_usb0: regulator@102 { + vdd_usb0: regulator-vdd-usb0 { compatible = "regulator-fixed"; regulator-name = "VDD_USB0"; regulator-min-microvolt = <5000000>; @@ -2286,7 +2286,7 @@ vdd_usb0: regulator@102 { vin-supply = <&vdd_5v0_sys>; }; - vdd_usb1: regulator@103 { + vdd_usb1: regulator-vdd-usb1 { compatible = "regulator-fixed"; regulator-name = "VDD_USB1"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index fcd71bfc6707..4917b43995b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -393,7 +393,7 @@ psci { method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -402,7 +402,7 @@ gnd: regulator@0 { regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -411,7 +411,7 @@ vdd_5v0_sys: regulator@1 { regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index af33fe93e1d6..28d59792eaa1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -593,7 +593,7 @@ psci { method = "smc"; }; - gnd: regulator@0 { + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; regulator-min-microvolt = <0>; @@ -602,7 +602,7 @@ gnd: regulator@0 { regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -611,7 +611,7 @@ vdd_5v0_sys: regulator@1 { regulator-boot-on; }; - vdd_1v8_ap: regulator@2 { + vdd_1v8_ap: regulator-vdd-1v8-ap { compatible = "regulator-fixed"; regulator-name = "VDD_1V8_AP"; regulator-min-microvolt = <1800000>; @@ -623,7 +623,7 @@ vdd_1v8_ap: regulator@2 { vin-supply = <&vdd_1v8>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c4058ee36fec..ad217cac2b28 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -317,7 +317,7 @@ temperature-sensor@4c { }; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VIN_SYS_5V0"; regulator-min-microvolt = <5000000>; @@ -326,7 +326,7 @@ vdd_5v0_sys: regulator@0 { regulator-boot-on; }; - vdd_hdmi: regulator@1 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; @@ -335,7 +335,7 @@ vdd_hdmi: regulator@1 { enable-active-high; }; - vdd_3v3_pcie: regulator@2 { + vdd_3v3_pcie: regulator-vdd-3v3-pcie { compatible = "regulator-fixed"; regulator-name = "PEX_3V3"; regulator-min-microvolt = <3300000>; @@ -345,7 +345,7 @@ vdd_3v3_pcie: regulator@2 { enable-active-high; }; - vdd_12v_pcie: regulator@3 { + vdd_12v_pcie: regulator-vdd-12v-pcie { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; regulator-min-microvolt = <1200000>; @@ -354,7 +354,7 @@ vdd_12v_pcie: regulator@3 { regulator-boot-on; }; - vdd_5v_sata: regulator@4 { + vdd_5v_sata: regulator-vdd-5v0-sata { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SATA"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index a055f17218bb..8d3999cd1af2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2000,7 +2000,7 @@ power { }; }; - vdd_5v0_sys: regulator@100 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; regulator-min-microvolt = <5000000>; @@ -2009,7 +2009,7 @@ vdd_5v0_sys: regulator@100 { regulator-boot-on; }; - vdd_3v3_sys: regulator@101 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -2018,7 +2018,7 @@ vdd_3v3_sys: regulator@101 { regulator-boot-on; }; - vdd_3v3_ao: regulator@102 { + vdd_3v3_ao: regulator-vdd-3v3-ao { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_AO"; regulator-min-microvolt = <3300000>; @@ -2027,7 +2027,7 @@ vdd_3v3_ao: regulator@102 { regulator-boot-on; }; - vdd_1v8: regulator@103 { + vdd_1v8: regulator-vdd-1v8 { compatible = "regulator-fixed"; regulator-name = "VDD_1V8"; regulator-min-microvolt = <1800000>; @@ -2036,7 +2036,7 @@ vdd_1v8: regulator@103 { regulator-boot-on; }; - vdd_hdmi: regulator@104 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_HDMI_CON"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 14da4206ea66..8c2c709dd54c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -20,7 +20,7 @@ mmc@3400000 { }; }; - vdd_3v3_sd: regulator@0 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index d3e622c4a439..75eb743a7242 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -336,7 +336,7 @@ psci { method = "smc"; }; - vdd_gpu: regulator@100 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index d8409c1b4380..34276a84c68a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1555,7 +1555,7 @@ volume_up { }; }; - vdd_sys_mux: regulator@0 { + vdd_sys_mux: regulator-vdd-sys-mux { compatible = "regulator-fixed"; regulator-name = "VDD_SYS_MUX"; regulator-min-microvolt = <5000000>; @@ -1564,7 +1564,7 @@ vdd_sys_mux: regulator@0 { regulator-boot-on; }; - vdd_5v0_sys: regulator@1 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; regulator-min-microvolt = <5000000>; @@ -1576,7 +1576,7 @@ vdd_5v0_sys: regulator@1 { vin-supply = <&vdd_sys_mux>; }; - vdd_3v3_sys: regulator@2 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; regulator-min-microvolt = <3300000>; @@ -1591,7 +1591,7 @@ vdd_3v3_sys: regulator@2 { regulator-disable-ramp-delay = <10000>; }; - vdd_5v0_io: regulator@3 { + vdd_5v0_io: regulator-vdd-5v0-io { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_IO_SYS"; regulator-min-microvolt = <5000000>; @@ -1600,7 +1600,7 @@ vdd_5v0_io: regulator@3 { regulator-boot-on; }; - vdd_3v3_sd: regulator@4 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; regulator-min-microvolt = <3300000>; @@ -1613,7 +1613,7 @@ vdd_3v3_sd: regulator@4 { regulator-disable-ramp-delay = <4880>; }; - vdd_dsi_csi: regulator@5 { + vdd_dsi_csi: regulator-vdd-dsi-csi { compatible = "regulator-fixed"; regulator-name = "AVDD_DSI_CSI_1V2"; regulator-min-microvolt = <1200000>; @@ -1621,7 +1621,7 @@ vdd_dsi_csi: regulator@5 { vin-supply = <&vdd_sys_1v2>; }; - vdd_3v3_dis: regulator@6 { + vdd_3v3_dis: regulator-vdd-3v3-dis { compatible = "regulator-fixed"; regulator-name = "VDD_DIS_3V3_LCD"; regulator-min-microvolt = <3300000>; @@ -1632,7 +1632,7 @@ vdd_3v3_dis: regulator@6 { vin-supply = <&vdd_3v3_sys>; }; - vdd_1v8_dis: regulator@7 { + vdd_1v8_dis: regulator-vdd-1v8-dis { compatible = "regulator-fixed"; regulator-name = "VDD_LCD_1V8_DIS"; regulator-min-microvolt = <1800000>; @@ -1643,7 +1643,7 @@ vdd_1v8_dis: regulator@7 { vin-supply = <&vdd_1v8>; }; - vdd_5v0_rtl: regulator@8 { + vdd_5v0_rtl: regulator-vdd-5v0-rtl { compatible = "regulator-fixed"; regulator-name = "RTL_5V"; regulator-min-microvolt = <5000000>; @@ -1653,7 +1653,7 @@ vdd_5v0_rtl: regulator@8 { vin-supply = <&vdd_5v0_sys>; }; - vdd_usb_vbus: regulator@9 { + vdd_usb_vbus: regulator-vdd-usb-vbus { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN1"; regulator-min-microvolt = <5000000>; @@ -1663,7 +1663,7 @@ vdd_usb_vbus: regulator@9 { vin-supply = <&vdd_5v0_sys>; }; - vdd_hdmi: regulator@10 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; regulator-min-microvolt = <5000000>; @@ -1673,7 +1673,7 @@ vdd_hdmi: regulator@10 { vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator@11 { + vdd_cam_1v2: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; @@ -1683,7 +1683,7 @@ vdd_cam_1v2: regulator@11 { vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_2v8: regulator@12 { + vdd_cam_2v8: regulator-vdd-cam-2v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-2v8"; regulator-min-microvolt = <2800000>; @@ -1693,7 +1693,7 @@ vdd_cam_2v8: regulator@12 { vin-supply = <&vdd_3v3_sys>; }; - vdd_cam_1v8: regulator@13 { + vdd_cam_1v8: regulator-vdd-cam-1v8 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v8"; regulator-min-microvolt = <1800000>; @@ -1703,7 +1703,7 @@ vdd_cam_1v8: regulator@13 { vin-supply = <&vdd_3v3_sys>; }; - vdd_usb_vbus_otg: regulator@14 { + vdd_usb_vbus_otg: regulator-vdd-usb-vbus-otg { compatible = "regulator-fixed"; regulator-name = "USB_VBUS_EN0"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index ed73c3a0c140..5cfbc0394173 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1635,7 +1635,7 @@ psci { method = "smc"; }; - battery_reg: regulator@0 { + battery_reg: regulator-vdd-ac-bat { compatible = "regulator-fixed"; regulator-name = "vdd-ac-bat"; regulator-min-microvolt = <5000000>; @@ -1643,7 +1643,7 @@ battery_reg: regulator@0 { regulator-always-on; }; - vdd_3v3: regulator@1 { + vdd_3v3: regulator-vdd-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd-3v3"; regulator-enable-ramp-delay = <160>; @@ -1655,7 +1655,7 @@ vdd_3v3: regulator@1 { enable-active-high; }; - max77620_gpio7: regulator@2 { + max77620_gpio7: regulator-max77620-gpio7 { compatible = "regulator-fixed"; regulator-name = "max77620-gpio7"; regulator-enable-ramp-delay = <240>; @@ -1669,7 +1669,7 @@ max77620_gpio7: regulator@2 { enable-active-high; }; - lcd_bl_en: regulator@3 { + lcd_bl_en: regulator-lcd-bl-en { compatible = "regulator-fixed"; regulator-name = "lcd-bl-en"; regulator-min-microvolt = <1800000>; @@ -1680,7 +1680,7 @@ lcd_bl_en: regulator@3 { enable-active-high; }; - en_vdd_sd: regulator@4 { + en_vdd_sd: regulator-vdd-sd { compatible = "regulator-fixed"; regulator-name = "en-vdd-sd"; regulator-enable-ramp-delay = <472>; @@ -1692,7 +1692,7 @@ en_vdd_sd: regulator@4 { enable-active-high; }; - en_vdd_cam: regulator@5 { + en_vdd_cam: regulator-vdd-cam { compatible = "regulator-fixed"; regulator-name = "en-vdd-cam"; regulator-min-microvolt = <1800000>; @@ -1702,7 +1702,7 @@ en_vdd_cam: regulator@5 { enable-active-high; }; - vdd_sys_boost: regulator@6 { + vdd_sys_boost: regulator-vdd-sys-boost { compatible = "regulator-fixed"; regulator-name = "vdd-sys-boost"; regulator-enable-ramp-delay = <3090>; @@ -1714,7 +1714,7 @@ vdd_sys_boost: regulator@6 { enable-active-high; }; - vdd_hdmi: regulator@7 { + vdd_hdmi: regulator-vdd-hdmi { compatible = "regulator-fixed"; regulator-name = "vdd-hdmi"; regulator-enable-ramp-delay = <468>; @@ -1727,21 +1727,21 @@ vdd_hdmi: regulator@7 { enable-active-high; }; - en_vdd_cpu_fixed: regulator@8 { + en_vdd_cpu_fixed: regulator-vdd-cpu-fixed { compatible = "regulator-fixed"; regulator-name = "vdd-cpu-fixed"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - vdd_aux_3v3: regulator@9 { + vdd_aux_3v3: regulator-vdd-aux-3v3 { compatible = "regulator-fixed"; regulator-name = "aux-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vdd_snsr_pm: regulator@10 { + vdd_snsr_pm: regulator-vdd-snsr-pm { compatible = "regulator-fixed"; regulator-name = "snsr_pm"; regulator-min-microvolt = <3300000>; @@ -1750,7 +1750,7 @@ vdd_snsr_pm: regulator@10 { enable-active-high; }; - vdd_usb_5v0: regulator@11 { + vdd_usb_5v0: regulator-vdd-usb-5v0 { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd-usb-5v0"; @@ -1761,7 +1761,7 @@ vdd_usb_5v0: regulator@11 { enable-active-high; }; - vdd_cdc_1v2_aud: regulator@101 { + vdd_cdc_1v2_aud: regulator-vdd-cdc-1v2-aud { compatible = "regulator-fixed"; status = "disabled"; regulator-name = "vdd_cdc_1v2_aud"; @@ -1772,7 +1772,7 @@ vdd_cdc_1v2_aud: regulator@101 { enable-active-high; }; - vdd_disp_3v0: regulator@12 { + vdd_disp_3v0: regulator-vdd-disp-3v0 { compatible = "regulator-fixed"; regulator-name = "vdd-disp-3v0"; regulator-enable-ramp-delay = <232>; @@ -1784,7 +1784,7 @@ vdd_disp_3v0: regulator@12 { enable-active-high; }; - vdd_fan: regulator@13 { + vdd_fan: regulator-vdd-fan { compatible = "regulator-fixed"; regulator-name = "vdd-fan"; regulator-enable-ramp-delay = <284>; @@ -1795,7 +1795,7 @@ vdd_fan: regulator@13 { enable-active-high; }; - usb_vbus1: regulator@14 { + usb_vbus1: regulator-usb-vbus1 { compatible = "regulator-fixed"; regulator-name = "usb-vbus1"; regulator-min-microvolt = <5000000>; @@ -1806,7 +1806,7 @@ usb_vbus1: regulator@14 { gpio-open-drain; }; - usb_vbus2: regulator@15 { + usb_vbus2: regulator-usb-vbus2 { compatible = "regulator-fixed"; regulator-name = "usb-vbus2"; regulator-min-microvolt = <5000000>; @@ -1817,7 +1817,7 @@ usb_vbus2: regulator@15 { gpio-open-drain; }; - vdd_3v3_eth: regulator@16 { + vdd_3v3_eth: regulator-vdd-3v3-eth { compatible = "regulator-fixed"; regulator-name = "vdd-3v3-eth-a02"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index cbd8cda48f37..283b50febb6f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1762,7 +1762,7 @@ psci { method = "smc"; }; - vdd_5v0_sys: regulator@0 { + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V0_SYS"; @@ -1772,7 +1772,7 @@ vdd_5v0_sys: regulator@0 { regulator-boot-on; }; - vdd_3v3_sys: regulator@1 { + vdd_3v3_sys: regulator-vdd-3v3-sys { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SYS"; @@ -1789,7 +1789,7 @@ vdd_3v3_sys: regulator@1 { vin-supply = <&vdd_5v0_sys>; }; - vdd_3v3_sd: regulator@2 { + vdd_3v3_sd: regulator-vdd-3v3-sd { compatible = "regulator-fixed"; regulator-name = "VDD_3V3_SD"; @@ -1802,7 +1802,7 @@ vdd_3v3_sd: regulator@2 { vin-supply = <&vdd_3v3_sys>; }; - vdd_hdmi: regulator@3 { + vdd_hdmi: regulator-vdd-hdmi-5v0 { compatible = "regulator-fixed"; regulator-name = "VDD_HDMI_5V0"; @@ -1812,7 +1812,7 @@ vdd_hdmi: regulator@3 { vin-supply = <&vdd_5v0_sys>; }; - vdd_hub_3v3: regulator@4 { + vdd_hub_3v3: regulator-vdd-hub-3v3 { compatible = "regulator-fixed"; regulator-name = "VDD_HUB_3V3"; @@ -1825,7 +1825,7 @@ vdd_hub_3v3: regulator@4 { vin-supply = <&vdd_5v0_sys>; }; - vdd_cpu: regulator@5 { + vdd_cpu: regulator-vdd-cpu { compatible = "regulator-fixed"; regulator-name = "VDD_CPU"; @@ -1840,7 +1840,7 @@ vdd_cpu: regulator@5 { vin-supply = <&vdd_5v0_sys>; }; - vdd_gpu: regulator@6 { + vdd_gpu: regulator-vdd-gpu { compatible = "pwm-regulator"; pwms = <&pwm 1 8000>; @@ -1855,7 +1855,7 @@ vdd_gpu: regulator@6 { vin-supply = <&vdd_5v0_sys>; }; - avdd_io_edp_1v05: regulator@7 { + avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 { compatible = "regulator-fixed"; regulator-name = "AVDD_IO_EDP_1V05"; @@ -1868,7 +1868,7 @@ avdd_io_edp_1v05: regulator@7 { vin-supply = <&avdd_1v05_pll>; }; - vdd_5v0_usb: regulator@8 { + vdd_5v0_usb: regulator-vdd-5v-usb { compatible = "regulator-fixed"; regulator-name = "VDD_5V_USB"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 43ff5e4bda19..6d59c28ff2a3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1807,7 +1807,7 @@ psci { method = "smc"; }; - ppvar_sys: regulator@0 { + ppvar_sys: regulator-ppvar-sys { compatible = "regulator-fixed"; regulator-name = "PPVAR_SYS"; regulator-min-microvolt = <4400000>; @@ -1815,7 +1815,7 @@ ppvar_sys: regulator@0 { regulator-always-on; }; - pplcd_vdd: regulator@1 { + pplcd_vdd: regulator-pplcd-vdd { compatible = "regulator-fixed"; regulator-name = "PPLCD_VDD"; regulator-min-microvolt = <4400000>; @@ -1825,7 +1825,7 @@ pplcd_vdd: regulator@1 { regulator-boot-on; }; - pp3000_always: regulator@2 { + pp3000_always: regulator-pp3000-always { compatible = "regulator-fixed"; regulator-name = "PP3000_ALWAYS"; regulator-min-microvolt = <3000000>; @@ -1833,7 +1833,7 @@ pp3000_always: regulator@2 { regulator-always-on; }; - pp3300: regulator@3 { + pp3300: regulator-pp3000 { compatible = "regulator-fixed"; regulator-name = "PP3300"; regulator-min-microvolt = <3300000>; @@ -1843,7 +1843,7 @@ pp3300: regulator@3 { enable-active-high; }; - pp5000: regulator@4 { + pp5000: regulator-pp5000 { compatible = "regulator-fixed"; regulator-name = "PP5000"; regulator-min-microvolt = <5000000>; @@ -1851,7 +1851,7 @@ pp5000: regulator@4 { regulator-always-on; }; - pp1800_lcdio: regulator@5 { + pp1800_lcdio: regulator-pp1800-lcdio { compatible = "regulator-fixed"; regulator-name = "PP1800_LCDIO"; regulator-min-microvolt = <1800000>; @@ -1861,7 +1861,7 @@ pp1800_lcdio: regulator@5 { regulator-boot-on; }; - pp1800_cam: regulator@6 { + pp1800_cam: regulator-pp1800-cam { compatible = "regulator-fixed"; regulator-name = "PP1800_CAM"; regulator-min-microvolt = <1800000>; @@ -1870,7 +1870,7 @@ pp1800_cam: regulator@6 { enable-active-high; }; - usbc_vbus: regulator@7 { + usbc_vbus: regulator-usbc-vbus { compatible = "regulator-fixed"; regulator-name = "USBC_VBUS"; regulator-min-microvolt = <5000000>; From patchwork Thu Dec 9 17:24:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Thu, 09 Dec 2021 09:25:13 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id f7sm379144wri.74.2021.12.09.09.25.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:12 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 03/30] arm64: tegra: Add native timer support on Tegra186 Date: Thu, 9 Dec 2021 18:24:36 +0100 Message-Id: <20211209172503.617716-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index eb739ffbdfce..35679d2eda69 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -508,6 +508,22 @@ emc: external-memory-controller@2c60000 { }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From patchwork Thu Dec 9 17:24:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565958 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=UY7Q0hMm; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Bq42txz9sR4 for ; Fri, 10 Dec 2021 04:25:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242829AbhLIR2y (ORCPT ); Thu, 9 Dec 2021 12:28:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242945AbhLIR2v (ORCPT ); Thu, 9 Dec 2021 12:28:51 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0C7EC0617A1 for ; Thu, 9 Dec 2021 09:25:17 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id p3-20020a05600c1d8300b003334fab53afso7109515wms.3 for ; Thu, 09 Dec 2021 09:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2kUnaropDSfgAFAoPXYMrt/i70qqRLbXmDJJOmkmxTA=; b=UY7Q0hMmgf5ByDdHsaU5DbWdEwbifXL19W18Vo+g4rpsCUekAWmSjj3iplJmXFOxd/ HT2cqkPmknqxxf4hIcO2puMhu8U+QtHMW7G8uDefAHQIdivvq2eV3cdEOhtsrHBJSeM7 n+DHilYYSoPVcBnc9NBVYpuJxW2tTIN/D38NEZlJ7eMoh53czacPOv/kvd4ZcA0NkWv3 eW45Kni1LIfFDNFkjBawgGiIizH0nkfgXlwZWSr94KfFVjMufWXUOjg+qSsGnyOss47D uszOp+aWCyKZ8POULWuB4h4qsOgEFxVJTG6WeHy/1chbycIk3jYF2Z0Hy9Dc1yjcdtUi C6iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2kUnaropDSfgAFAoPXYMrt/i70qqRLbXmDJJOmkmxTA=; b=A02kbK2Ui6G+iQ/VCgvAtYzx61R9Kzy3SOHQd4zUCbfRYbIDc49NA1L53KlCQlbc5J iMrJN/KyXkJdjnbYTy7YekeDfd+AOgHW/AIRMxZaELl4vjw29B2P4SJQ/QBBeALlgABJ u6mrDMrhH4mRwTC9Jkyl0+Y4euiya99V3xKVbXGA0RE+gyET4dnYktBsOTwpyEbDsxdr wNMW8XIK94BIBJEOkp+rsphQNuowe6EA3OAb0dDSRElrJ/XVaChFMkqDuiPNXr/x1u5o Fb37XNRjN42o3Aq0sXOTbZItaR+szlCSZVRuePKwTukVT1tS4QOlvlX/Sd4KEN4lnfPW ympA== X-Gm-Message-State: AOAM530MJXwquCk527Xh2/yJxSc/O0GKnr/ZhlzVGoyxj3y68Xirj1G+ ehBCzS7wLW8z6iNnfZ3QGSE= X-Google-Smtp-Source: ABdhPJy/W80L/RhPWYKUOB0onQNZyiimNKQZBS9Xi2uAYeF0w7iU+b7mYS9AyXrhyMM4VHqoYXJkQA== X-Received: by 2002:a1c:6a0e:: with SMTP id f14mr8991170wmc.58.1639070716101; Thu, 09 Dec 2021 09:25:16 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id z6sm275953wrm.93.2021.12.09.09.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:15 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 04/30] arm64: tegra: Fix unit-addresses on Norrin Date: Thu, 9 Dec 2021 18:24:37 +0100 Message-Id: <20211209172503.617716-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index c84ed1cb9a8c..f9604968c01f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -564,7 +564,7 @@ as3722: pmic@40 { pinctrl-names = "default"; pinctrl-0 = <&as3722_default>; - as3722_default: pinmux@0 { + as3722_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -770,7 +770,7 @@ i2c_20: i2c-tunnel { google,remote-bus = <0>; - charger: bq24735 { + charger: bq24735@9 { compatible = "ti,bq24735"; reg = <0x9>; interrupt-parent = <&gpio>; @@ -781,7 +781,7 @@ TEGRA_GPIO(J, 0) GPIO_ACTIVE_HIGH>; }; - battery: smart-battery { + battery: smart-battery@b { compatible = "sbs,sbs-battery"; reg = <0xb>; sbs,i2c-retry-count = <2>; From patchwork Thu Dec 9 17:24:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565959 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=B/Mwt8QH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Br6mLPz9sR4 for ; Fri, 10 Dec 2021 04:25:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242892AbhLIR2z (ORCPT ); Thu, 9 Dec 2021 12:28:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242878AbhLIR2x (ORCPT ); Thu, 9 Dec 2021 12:28:53 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF929C061746 for ; Thu, 9 Dec 2021 09:25:19 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id i5so10970188wrb.2 for ; Thu, 09 Dec 2021 09:25:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ggiAP2ZX5X2LM7JWPYu3dtCeeeNVwHBEcMH0iW6rj/s=; b=B/Mwt8QH6kkqGwB7Z0mWvmiYfy6JNxJzYqoZHkEgx9RhC1liYxdWW7X6yQ6j2WicVT Iyibc1mjSb4vT9RD6UiQFEFuPqyhWpetsTmDvH3jdxyyPHRzgJdEERMKNoqUgQh1ElxI bhM4dZN1MR61Hjm6J20I0X7ErxjI/vnZiaD0SrCmnO4DdUs2JcVNiKIvif2D/5VEIwxX EBhOTqD6xieLbzsxdEQrcfAdLxltni76KwF3tSrAw7YyPbvTNaDENUktadGenqT/rA9y aAV1w8WUqLm2QI0AYsj8567EQ2gBi9Z0p91AUFgJtgBusuyxA1YM+VBi0BILhG3B1YE0 YYUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ggiAP2ZX5X2LM7JWPYu3dtCeeeNVwHBEcMH0iW6rj/s=; b=RGzqTo4bOjietvJBxwjNT9nQcEhuPRMEOHUmmAYLdDaWuniEXuHtHZPVF1T1t3VaA0 UQ2I33pjs7MnLxlPKHx/kvpBH6zvLVQnzV/jvyB9tZ73YW1zEvwRcNIItgqPUNU00vHs mRgkkZr+fBCu8AdXh3v3tBSjZ7BqOiVKynkmGVcZprDj1ezxuV5yp0mR9GB3CJI+GaZT oHVmYWHvA3FLIb++SeuTl8Vw5H6pH6CwDgOVxba1NdYVxeVSWSJQfoNOrsHxIHyHjR/s Tt0XlKMITfv8wVXUMzdNhrBD7PK+ZXpXjo9ZGoKDivc57t3dwhYSWDG9vZ7ilmygzwjc PZyQ== X-Gm-Message-State: AOAM530QqRf/5rYF0l6N2dAHCCMlmPNNorLAk5H4iSzRXBiyWjvNuy76 05lM8P3eSFWKmaL2bxdQnSM= X-Google-Smtp-Source: ABdhPJwKM9bYVyX54vzHAh3QIk74x2OXcBj5A1ABgPNzRG38Cd1wihi05U8cgSEmyaoSUkhzI2iUiA== X-Received: by 2002:a05:6000:11c3:: with SMTP id i3mr7764971wrx.426.1639070718386; Thu, 09 Dec 2021 09:25:18 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id az4sm9624392wmb.20.2021.12.09.09.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:17 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 05/30] arm64: tegra: Remove unsupported properties on Norrin Date: Thu, 9 Dec 2021 18:24:38 +0100 Message-Id: <20211209172503.617716-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index f9604968c01f..f16acb4cabaa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -885,14 +885,12 @@ MATRIX_KEY(0x07, 0x0b, KEY_UP) pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; - #wake-cells = <3>; nvidia,cpu-pwr-good-time = <500>; nvidia,cpu-pwr-off-time = <300>; nvidia,core-pwr-good-time = <641 3845>; nvidia,core-pwr-off-time = <61036>; nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; }; usb@70090000 { From patchwork Thu Dec 9 17:24:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=LmidNwLq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Bs4X5lz9sRK for ; Fri, 10 Dec 2021 04:25:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242878AbhLIR26 (ORCPT ); Thu, 9 Dec 2021 12:28:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242896AbhLIR2z (ORCPT ); Thu, 9 Dec 2021 12:28:55 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39E16C061746 for ; Thu, 9 Dec 2021 09:25:22 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id p3-20020a05600c1d8300b003334fab53afso7109684wms.3 for ; Thu, 09 Dec 2021 09:25:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=30Wkjiv7hi0QMKF3Sk+crW/FAw21BP8yvQUN4NXV1W8=; b=LmidNwLqdef9oCqSmlszxBOyHY5A+YD0dSElJLlED69wH44Viu5+YRTnn51SxmOlVb sQaqTPQOtEx1UfTTQMxrBzn3nD7Ma/TOEZT5l7vsSIkCUYA/idSDPBbvRCb+4vec5B2o Y/jyp6IicWMo6kcvoZQWf90jm+GV0XuEGRlFA0h8dGjxZc1WL4lfX8pFmWt00jXSBNLI KaLoaYPjLKVTBY2W+VB6fHB1hRwudhTBt5q+BGmEjlFF11gvjW4k+Qgj2ZIP5E51thYh oG2rIDV54G+9SkR3TgCsrJjubdH3ZfthvdXEvU9/3z0RzAy09Ng+D5UImuxqF+3TVdZB jvUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=30Wkjiv7hi0QMKF3Sk+crW/FAw21BP8yvQUN4NXV1W8=; b=whM5wE8ww304NVxdfv/4t7EtvxD1rPzbhbXcvobmNK3aVD+pwwUHMZN6khaZOrgGzM 7520ue5Xf4kxfS6dJkh/GjnTm4AshTqMnvkVBUD9kg6qo+Y+Tus5wHQFClzhC/de3jnf 4vw05v0yuytlsHfgGE1IVv1K99db7LrXOMcYKiz+qxwBxu5vCe7ZHc9NR+GGYQYzGvbO ofrHlu84kYMXRMYpIvrxpjxLD6w8c+EOnsoCLPvtEE5KWzZtpmDdfmsk5h1s6OpS2jF/ Z2DvFLf/7/nHEpAy8bEBXafBpS8sWmmksZp5/3QxlCLLWLs3XBx9/QHgLkjr5trgaHCH 75MA== X-Gm-Message-State: AOAM533ysiXqX8pWxdbcerH+7+v5Mkdia+xh/KVvZuAn+u3hNHLW7Oxk HRbb2f421sRmtLq1TCPu+GJJXikPtUlV9Q== X-Google-Smtp-Source: ABdhPJwKWlbsiQBw59JwZTrYYYvBQJIKa2jH+LvwmoJmWEygw4GeMSPre0P7hIEJ1UH5D7/QehlNFw== X-Received: by 2002:a7b:c934:: with SMTP id h20mr9161607wml.94.1639070720785; Thu, 09 Dec 2021 09:25:20 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h204sm444400wmh.33.2021.12.09.09.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:20 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 06/30] arm64: tegra: Fix compatible string for Tegra132 timer Date: Thu, 9 Dec 2021 18:24:39 +0100 Message-Id: <20211209172503.617716-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 63aa3129d8fc..95bdcc8f31c9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -210,7 +210,7 @@ lic: interrupt-controller@60004000 { }; timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , From patchwork Thu Dec 9 17:24:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Ai7S/HSr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Bt25fbz9sR4 for ; Fri, 10 Dec 2021 04:25:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242903AbhLIR27 (ORCPT ); Thu, 9 Dec 2021 12:28:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242896AbhLIR26 (ORCPT ); Thu, 9 Dec 2021 12:28:58 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13B3C061746 for ; Thu, 9 Dec 2021 09:25:24 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id j3so10995067wrp.1 for ; Thu, 09 Dec 2021 09:25:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TPLnyhEeQ8IC1sdxs0QOSr1vVJg7XkLsG/OIFsZnjpc=; b=Ai7S/HSrZ9tGeRBB4PUtas59Ure6akb2myH5cdbCQZ1yQqbUonPMI+SSsEptRPGBre m6/4uf2zrLC7hdzQYah6kzCB8vv4K5gGoK7GeaJBjMre2DwaqChFFcW1Z+hpVcfl6UX3 uLIkwidz6gb4wpyRrbujN5W/EqBikkQNvaR2NQYAYtPs5RKOfW+FJWcO3dVDYlii8TvZ u5u2S6CXaoHCMkrlmLyCXae13gtt59E5DiSFjJrKwB1rEBxzGS1PVpDbCQP0IL2EoUvk 4V1SzBifH2JedJMo0Y6Zs/do1YsxmyjASAe3o1gGhSKIfl57SOutBnrjgAueK/NMqwJ0 oIjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TPLnyhEeQ8IC1sdxs0QOSr1vVJg7XkLsG/OIFsZnjpc=; b=lhWWtEDpoDxwvskgMguOEltMHHvHokNNo2lxZhPnqLCGIIKu/lxURDocVRIc54eVQq dWqawHHC1qiTju8mKN6yAGZlIRNsrKvF5eeI/8KFBcTpJLm4DWqIHRTVSnNOkVLIl0Yd LxXSDRHUrfG1vAUWDpOUuhB72IJW1G0B0v74MsyqEu7MYLQWsjNAGBcRy20H8qJinKv7 Vhw3z1o/4PHT0uTKXxrIp/ckTrFlBJx9KzAjWcKAEwl49SgD1sFQ02S4Xyn4hdoIfDeM JyCzpuxafKQkDsufeN2UMrT2LqQKbBAbgDpDw8/ghJqbDmZWDOLDRrpQc9BjJ2Uh/J+6 iIWA== X-Gm-Message-State: AOAM531JpxGnbG1XA6o3lvffXxce64MvhvAbFEyT7UBTBmF/KlPEBdls xKH2ZC+V8uzStgqJ08DD3Zca/4hRGttFtQ== X-Google-Smtp-Source: ABdhPJyQHcbsBbFGhsCKl2ygbJnCchNGMizaQIaofW/ErbBUQDJq/EvEzI3cVWL5m5oEpCsDfLSxBQ== X-Received: by 2002:a5d:6da9:: with SMTP id u9mr7939472wrs.237.1639070723251; Thu, 09 Dec 2021 09:25:23 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id 138sm9487899wma.17.2021.12.09.09.25.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:22 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 07/30] arm64: tegra: Add OPP tables on Tegra132 Date: Thu, 9 Dec 2021 18:24:40 +0100 Message-Id: <20211209172503.617716-8-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra132-peripherals-opp.dtsi | 426 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra132.dtsi | 13 +- 2 files changed, 438 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi new file mode 100644 index 000000000000..66ffb7f8aaa7 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra132-peripherals-opp.dtsi @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* EMC DVFS OPP table */ + emc_icc_dvfs_opp_table: opp-table-dvfs0 { + compatible = "operating-points-v2"; + + opp-12750000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp-12750000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp-12750000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp-12750000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp-20400000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp-20400000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp-20400000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp-20400000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp-40800000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp-40800000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp-40800000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp-40800000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp-68000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp-68000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp-68000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp-68000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp-102000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp-102000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp-102000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp-102000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp-204000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + opp-suspend; + }; + + opp-204000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + opp-suspend; + }; + + opp-204000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + opp-suspend; + }; + + opp-204000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + opp-suspend; + }; + + opp-264000000-800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp-264000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp-264000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp-264000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp-300000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp-300000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp-300000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp-300000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp-348000000-850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp-348000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp-348000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp-348000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp-396000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp-396000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp-396000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp-396000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp-528000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp-528000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp-528000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp-528000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp-600000000-950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp-600000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp-600000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp-600000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp-792000000-1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp-792000000-1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp-792000000-1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp-924000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp-1200000000-1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + /* EMC bandwidth OPP table */ + emc_bw_dfs_opp_table: opp-table-dvfs1 { + compatible = "operating-points-v2"; + + opp-12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp-20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp-40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp-68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp-102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp-204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + opp-suspend; + }; + + opp-264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp-396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 95bdcc8f31c9..7f5cbcd63a25 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra132-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra132", "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -244,6 +246,10 @@ actmon@6000c800 { clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; + #cooling-cells = <2>; }; gpio: gpio@6000d000 { @@ -607,15 +613,20 @@ mc: memory-controller@70019000 { interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc"; + compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; + + #interconnect-cells = <0>; }; sata@70020000 { From patchwork Thu Dec 9 17:24:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7f5cbcd63a25..0e8903027f04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -400,7 +400,7 @@ pwm: pwm@7000a000 { }; i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -415,7 +415,7 @@ i2c@7000c000 { }; i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -430,7 +430,7 @@ i2c@7000c400 { }; i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -445,7 +445,7 @@ i2c@7000c500 { }; i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -460,7 +460,7 @@ i2c@7000c700 { }; i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; @@ -475,7 +475,7 @@ i2c@7000d000 { }; i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + compatible = "nvidia,tegra124-i2c"; reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; From patchwork Thu Dec 9 17:24:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Thu, 09 Dec 2021 09:25:28 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id u2sm380388wrs.17.2021.12.09.09.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:27 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 09/30] arm64: tegra: Drop unused AHCI clocks on Tegra132 Date: Thu, 9 Dec 2021 18:24:42 +0100 Message-Id: <20211209172503.617716-10-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0e8903027f04..16673d3bf6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -635,10 +635,8 @@ sata@70020000 { <0x0 0x70020000 0x0 0x7000>; /* SATA */ interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; + <&tegra_car TEGRA124_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, <&tegra_car 129>, <&tegra_car 123>; From patchwork Thu Dec 9 17:24:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=ZiqHt46G; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91C40cRHz9sR4 for ; Fri, 10 Dec 2021 04:25:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236262AbhLIR3I (ORCPT ); Thu, 9 Dec 2021 12:29:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242877AbhLIR3G (ORCPT ); Thu, 9 Dec 2021 12:29:06 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A778C061B38 for ; Thu, 9 Dec 2021 09:25:32 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id i5so10971144wrb.2 for ; Thu, 09 Dec 2021 09:25:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AhDEjMctY7GtlKZfNF5JSWA+ovioh6zSyR/7n1Spgjw=; b=ZiqHt46GorAw7R2928r19+8f3VnmWs+rJRs1e4bHAufiwlorowjivPEaCuxBNCNKrd xuAkN5+PDf+C4y/xpJjreWAydONMDO7Q5QGAKS7/+uokL80wX5uv7NpTbOY/562VzidI SWwMer5Am8El4QI607iI/fE7TxUlm+F8HbO0AMXzw+XutyKb8QqFdwXNJpDZit7Bx+wm bd/JZWVY2Yw436cVI3XIpZs/u927zJ2EYFAkwoTHVGY86kq+Yocg9L2wtrlfvhD9zIDc c7WHy/JkOCQuWRnN/0WsbDl6aWNGBw5rAUj0cXW9YR/Gr+bxb9SXTTGlIFeJXKLu7d0B pD+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AhDEjMctY7GtlKZfNF5JSWA+ovioh6zSyR/7n1Spgjw=; b=ZLqCBbajYPs05KlcFqNZk6IkC0Dl8+kmNvd5LXwXNry7q+ZacaSF/X/bS70lidrqsD O/V3o9QxYaXD4cn0CNvXuNCKmna25tHY6/wfuAOo0skHaXSesyRYWRBMyuhkC1NxiYQT 2p2BDOg4r4/8xLJE6jdYvg/qCEgli/eu2eRa/AuWihtnTpErZUj0S9VVQ5td142IyjFE LvnWJCBdCZ1NtG2gnDdMEaMf/H/LxEcmEJ7YttqzYBZZs6cfrcqODyKN3OkFxW3tp4m7 Htdvy6jtAXe5QEpKdRIgWOkM81p2GHw3IDlzcrPOk0wzEiD9BhWZk6mDli40E39WY+j7 CRVA== X-Gm-Message-State: AOAM5315qwsUVOsz15LXxnDOIpL3sWLWMA782C+SpR67hAfa/p0yB7Tm 747yP+gKsWA4bYNj7j2TZoo= X-Google-Smtp-Source: ABdhPJzJ2KzxnXFloDGIrp8LKWY9BfudzTDmjLZBexsq/O9fQxHAdgHqcCSC/myjCcusp3tJVWOzcQ== X-Received: by 2002:a5d:6c67:: with SMTP id r7mr7963995wrz.286.1639070730879; Thu, 09 Dec 2021 09:25:30 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id u23sm326672wru.21.2021.12.09.09.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:30 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 10/30] arm64: tegra: Sort Tegra132 XUSB clocks correctly Date: Thu, 9 Dec 2021 18:24:43 +0100 Message-Id: <20211209172503.617716-11-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 16673d3bf6f9..e41671fcd7e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -674,8 +674,8 @@ usb@70090000 { <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA124_CLK_PLL_U_480M>, @@ -683,7 +683,7 @@ usb@70090000 { <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From patchwork Thu Dec 9 17:24:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=bJVcZgZA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91C45VZSz9sR4 for ; Fri, 10 Dec 2021 04:25:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233670AbhLIR3J (ORCPT ); Thu, 9 Dec 2021 12:29:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242862AbhLIR3I (ORCPT ); Thu, 9 Dec 2021 12:29:08 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9AB7C061746 for ; Thu, 9 Dec 2021 09:25:34 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id q3so10939880wru.5 for ; Thu, 09 Dec 2021 09:25:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NwDVLLOpstvURWBNQkl8aI5dnUgYEM/XX1KwlvI9g3U=; b=bJVcZgZAnvKwdsFo1J1oS8SVcxKekJvx3FqsppsJDi7qvt/5Im+7gWhMue20L7Szu8 IZqkkKe3cSbMEfok3OI7kn4NjxqvmFTEgjDC8q8KnB89oF099nQe45iEYhzo5q+KeP6a f17v1ZubegKUiY0yHtw+YKVMmjKQfPhidzU+cHCPfQUIcwQPq4y2HgQZsTMGQ10sTUXs z7B6yGIzlIoizYHse6o7Sdbjqj/M98u89J0IzeVr/JeKLs61gcvBy19cDCo7oQxo3SvN q5sNWFH4Ih3Xir6+ByawaeL1YNGiIEbtgtF7vqRQb8Zxk9i3OWJ1fI6lZzds1JBSTQUi UO2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NwDVLLOpstvURWBNQkl8aI5dnUgYEM/XX1KwlvI9g3U=; b=4FDmxBgrh9+UK9+sk77+NH3mhQEXvIO6MqVBj5qP1wEK2Pc0fzPVRtZPO/aizTaLhK nenh3KVF1M0DNYkEFdgMq2MCAd4+SOzr083sJYBpCf4ZekeUBWVr4bHAnN9h4iGK4AQY yaRwT+IJrxyQSh++AqA6+QbBKMuVaZYBTsFaR6Qog1Kf3wNgxlPLPyPY56TtJDZ1/mkX HvbPAicjuuURxSxqRNFi78aWa6wMcQGyjYlq0HBiuJdRUS3CHdIJVVQB6wM8S+BlrB7O 9pfecLBlpQ1QNvTPAi0LbgbAFW6y41633MISHLQhLZCU2w2DoSIbC1A6czIzwjHjIEXU S49A== X-Gm-Message-State: AOAM532eDeNd6WGykGM4Ug2eXnV3vGCCZPxanN74DRtmQi1dzek+lZR6 6e39jlf4BFK//vPOPKEuJcU= X-Google-Smtp-Source: ABdhPJxezVtcfmx4G3QQg3qyaIrvYPazNU/62Orq4RW1Js9N6F4dZW+avFua0TsmdbfAntdZ9LqBOg== X-Received: by 2002:a5d:4b0f:: with SMTP id v15mr7889014wrq.264.1639070733383; Thu, 09 Dec 2021 09:25:33 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h2sm290009wrz.23.2021.12.09.09.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:32 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 11/30] arm64: tegra: Rename thermal zones nodes Date: Thu, 9 Dec 2021 18:24:44 +0100 Message-Id: <20211209172503.617716-12-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 11 ++++--- .../nvidia/tegra186-p3509-0000+p3636-0001.dts | 14 ++++----- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 27 ++++++++--------- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 6 ++-- .../boot/dts/nvidia/tegra194-p3509-0000.dtsi | 6 ++-- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 30 ++++++++----------- .../boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++--- 8 files changed, 49 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e41671fcd7e3..3673f79adf1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -895,7 +895,7 @@ throttle_heavy: heavy { }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -923,7 +923,8 @@ map0 { }; }; }; - mem { + + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -950,7 +951,8 @@ cooling-maps { */ }; }; - gpu { + + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -978,7 +980,8 @@ map0 { }; }; }; - pllx { + + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 28d59792eaa1..33e707ef883b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -633,7 +633,7 @@ vdd_hdmi: regulator-vdd-hdmi { }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -687,28 +687,28 @@ cpu-passive { }; }; - gpu { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; trips { - gpu_alert0: critical { - temperature = <99000>; + aux_alert0: critical { + temperature = <90000>; hysteresis = <0>; type = "critical"; }; }; }; - aux { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; trips { - aux_alert0: critical { - temperature = <90000>; + gpu_alert0: critical { + temperature = <99000>; hysteresis = <0>; type = "critical"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 35679d2eda69..f4642ceacc63 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1946,12 +1946,12 @@ sound { }; thermal-zones { - a57 { + /* Cortex-A57 cluster */ + cpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; trips { critical { @@ -1965,12 +1965,12 @@ cooling-maps { }; }; - denver { + /* Denver cluster */ + aux-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; trips { critical { @@ -1984,12 +1984,11 @@ cooling-maps { }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; trips { critical { @@ -2003,12 +2002,11 @@ cooling-maps { }; }; - pll { + pll-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; trips { critical { @@ -2022,12 +2020,11 @@ cooling-maps { }; }; - always_on { + ao-thermal { polling-delay = <0>; polling-delay-passive = <1000>; - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; + thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; trips { critical { diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 9f34871b8f60..b79d7d89cf62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2097,7 +2097,7 @@ sound { }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2151,7 +2151,7 @@ cpu-passive { }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2165,7 +2165,7 @@ gpu_alert0: critical { }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8d3999cd1af2..76d94ecd1cfe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2103,7 +2103,7 @@ sound { }; thermal-zones { - cpu { + cpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2157,7 +2157,7 @@ cpu-passive { }; }; - gpu { + gpu-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; @@ -2171,7 +2171,7 @@ gpu_alert0: critical { }; }; - aux { + aux-thermal { polling-delay = <0>; polling-delay-passive = <500>; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index a0025b1c425f..14868e877c63 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2739,39 +2739,33 @@ tcu: tcu { }; thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; status = "disabled"; }; - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; status = "disabled"; }; - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; + aux-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; status = "disabled"; }; - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; + pllx-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; status = "disabled"; }; - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; + ao-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; status = "disabled"; }; - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 283b50febb6f..9e60ebf2f5c0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1684,7 +1684,7 @@ fan: fan { }; thermal-zones { - cpu { + cpu-thermal { trips { cpu_trip_critical: critical { temperature = <96500>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ccdc0dec4e59..af9237ad03c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1981,7 +1981,7 @@ sound { }; thermal-zones { - cpu { + cpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2010,7 +2010,7 @@ map0 { }; }; - mem { + mem-thermal { polling-delay-passive = <0>; polling-delay = <0>; @@ -2056,7 +2056,7 @@ dram-active { }; }; - gpu { + gpu-thermal { polling-delay-passive = <1000>; polling-delay = <0>; @@ -2085,7 +2085,7 @@ map0 { }; }; - pllx { + pllx-thermal { polling-delay-passive = <0>; polling-delay = <0>; From patchwork Thu Dec 9 17:24:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=ZItBa/3I; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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Thu, 09 Dec 2021 09:25:35 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id g18sm290187wrv.42.2021.12.09.09.25.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:35 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 12/30] arm64: tegra: Rename power-monitor input nodes Date: Thu, 9 Dec 2021 18:24:45 +0100 Message-Id: <20211209172503.617716-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++------ arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 12 ++++++------ .../dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 8 ++++---- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 2883049c4edf..c4dee05f330c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -1945,19 +1945,19 @@ power-monitor@42 { #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_MUX"; shunt-resistor-micro-ohms = <20000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_5V0_IO_SYS"; shunt-resistor-micro-ohms = <5000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V3_SYS"; shunt-resistor-micro-ohms = <10000>; @@ -1970,19 +1970,19 @@ power-monitor@43 { #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_3V3_IO_SLP"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_1V8_IO"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_M2_IN"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 4917b43995b0..3d8878c0ec03 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -73,19 +73,19 @@ power-monitor@40 { #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_SYS_GPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_SOC"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_3V8_WIFI"; shunt-resistor-micro-ohms = <10000>; @@ -98,19 +98,19 @@ power-monitor@41 { #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0x0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5000>; }; - channel@1 { + input@1 { reg = <0x1>; label = "VDD_SYS_CPU"; shunt-resistor-micro-ohms = <10000>; }; - channel@2 { + input@2 { reg = <0x2>; label = "VDD_5V0_DDR"; shunt-resistor-micro-ohms = <10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 33e707ef883b..6cc51083adb7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -81,22 +81,22 @@ power-monitor@40 { #address-cells = <1>; #size-cells = <0>; - channel@0 { + input@0 { reg = <0>; label = "VDD_IN"; shunt-resistor-micro-ohms = <5>; }; - channel@1 { + input@1 { reg = <1>; label = "VDD_CPU_GPU"; shunt-resistor-micro-ohms = <5>; }; - channel@2 { + input@2 { reg = <2>; label = "VDD_SOC"; - shunt-resistor-micro-ohms = <>; + shunt-resistor-micro-ohms = <5>; }; }; }; From patchwork Thu Dec 9 17:24:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=V1nd22iN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CF0lXsz9sR4 for ; Fri, 10 Dec 2021 04:25:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232940AbhLIR3P (ORCPT ); Thu, 9 Dec 2021 12:29:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233067AbhLIR3N (ORCPT ); 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Thu, 09 Dec 2021 09:25:37 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 13/30] arm64: tegra: Fix Tegra186 compatible string list Date: Thu, 9 Dec 2021 18:24:46 +0100 Message-Id: <20211209172503.617716-14-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index f4642ceacc63..e8886c9f54da 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -585,7 +585,7 @@ uartf: serial@3150000 { }; gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03160000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -598,7 +598,7 @@ gen1_i2c: i2c@3160000 { }; cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03180000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -612,7 +612,7 @@ cam_i2c: i2c@3180000 { /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x03190000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -629,7 +629,7 @@ dp_aux_ch1_i2c: i2c@3190000 { /* controlled by BPMP, should not be enabled */ pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031a0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -643,7 +643,7 @@ pwr_i2c: i2c@31a0000 { /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -659,7 +659,7 @@ dp_aux_ch0_i2c: i2c@31b0000 { }; gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -672,7 +672,7 @@ gen7_i2c: i2c@31c0000 { }; gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1089,7 +1089,7 @@ hsp_top0: hsp@3c00000 { }; gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = ; #address-cells = <1>; @@ -1102,7 +1102,7 @@ gen2_i2c: i2c@c240000 { }; gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; + compatible = "nvidia,tegra186-i2c"; reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = ; #address-cells = <1>; From patchwork Thu Dec 9 17:24:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565968 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=R1JGNzqx; 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Thu, 09 Dec 2021 09:25:41 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id b14sm440562wrd.24.2021.12.09.09.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:40 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 14/30] arm64: tegra: Adjust length of CCPLEX cluster MMIO region Date: Thu, 9 Dec 2021 18:24:47 +0100 Message-Id: <20211209172503.617716-15-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e8886c9f54da..e4b0c9835fbe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1215,7 +1215,7 @@ sdmmc3_1v8: sdmmc3-1v8 { ccplex@e000000 { compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; + reg = <0x0 0x0e000000 0x0 0x400000>; nvidia,bpmp = <&bpmp>; }; From patchwork Thu Dec 9 17:24:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565971 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=e/FCDQSq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CS38wsz9sR4 for ; Fri, 10 Dec 2021 04:25:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242848AbhLIR32 (ORCPT ); Thu, 9 Dec 2021 12:29:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242855AbhLIR3T (ORCPT ); Thu, 9 Dec 2021 12:29:19 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C52D1C061D5F for ; Thu, 9 Dec 2021 09:25:45 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id v11so10903046wrw.10 for ; Thu, 09 Dec 2021 09:25:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9dBk4A4FMc50NWYfa3dsHQucQqrnFqo52HH78dud0bw=; b=e/FCDQSq0q8eLZi/2vG1I+77gSYa2Mo2RYTFUrl1oAaSxSqGrRBgXPG7/sqW8Um7EB WOYyy9e015iO2dmp5WMFOuSD6mYxCHEDoPFd95pdH8pjqHu4/3mzABBZX+DvwsVriTzP NyWLsDAwspqOw020kmxh+Gu9Emt1T/trP4nkr5/QlwUiY3HKQHEXXo4VFSQhDxsCynpB SyuiLKmFtSUaXWdC6oQ372ji3oztZwFwWSunUYNce+aPCJsGoWbo6lJ7GItZLE8Ff1Cj jBMEQWgpPR98DJ9oa3Ir8zRW5vxcpYYPrIc5/GcQlN96HbWUdPIS/rW+R24n7Ot3ssn2 ylPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9dBk4A4FMc50NWYfa3dsHQucQqrnFqo52HH78dud0bw=; b=6xbExOkd9/Jp8GlyIQG8zPssdA31odrQk/qFDrZEbNVPt/KRQgsr7ax4aWp7r3NFjN N4C8w/kzzSisvfk/NSBIjdPEqzaMiwNjVMhQf76W6hYitloZw3iXBtc2XKBFW+nAbQ+t HgEr1llaCl/DR8lcXv/mlZwTenKsjU3jvA20CJLCfUOm75odnQ+n6IbEg5zuY4lg4z8i aobOJ8sosSyZpKi/Wp8xtXLoHhU6wtRllgJPrCP5yJlKlj8Z9HC70RE3Xdflf8Ulqh7A epfL0n2F0TdjwTX12LPdiQkRC130I+cFXfjtvL3mW9Rzikmkz2I9enI/wCZyxosmnpzW XF2w== X-Gm-Message-State: AOAM532PHqjt1BTSbEjI1HwCdXB944jAqdipX8lh0Zusf/hhc1bLhx4t mJXFTUTi/+x/2WacU+NUTJV2dBVLosXWRg== X-Google-Smtp-Source: ABdhPJwJK/2eISWuMLhMgXvi4JhTRP/8iFM7tYYCkc5rnJmrp+EafraAsY3ZCise72zyc4h/DQx8Ew== X-Received: by 2002:adf:f489:: with SMTP id l9mr8186066wro.268.1639070744344; Thu, 09 Dec 2021 09:25:44 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id s63sm406316wme.22.2021.12.09.09.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:43 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 15/30] arm64: tegra: Drop unit-address for audio card graph endpoints Date: Thu, 9 Dec 2021 18:24:48 +0100 Message-Id: <20211209172503.617716-16-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Audio graph endpoints don't have a "reg" property, so they shouldn't have a unit-address either. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index b79d7d89cf62..2478ece9e67c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1031,7 +1031,7 @@ i2s6_cif_ep: endpoint { i2s6_port: port@1 { reg = <1>; - i2s6_dap_ep: endpoint@0 { + i2s6_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 76d94ecd1cfe..6d4ed67ffeda 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -989,7 +989,7 @@ i2s5_cif_ep: endpoint { i2s5_port: port@1 { reg = <1>; - i2s5_dap_ep: endpoint@0 { + i2s5_dap_ep: endpoint { dai-format = "i2s"; /* Place holder for external Codec */ }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9e60ebf2f5c0..260de1122aa3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -688,7 +688,7 @@ i2s4_cif_ep: endpoint { i2s4_port: port@1 { reg = <1>; - i2s4_dap_ep: endpoint@0 { + i2s4_dap_ep: endpoint { dai-format = "i2s"; /* Placeholder for external Codec */ }; @@ -706,7 +706,7 @@ ports { port@0 { reg = <0>; - dmic1_cif_ep: endpoint@0 { + dmic1_cif_ep: endpoint { remote-endpoint = <&xbar_dmic1_ep>; }; }; @@ -714,7 +714,7 @@ dmic1_cif_ep: endpoint@0 { dmic1_port: port@1 { reg = <1>; - dmic1_dap_ep: endpoint@0 { + dmic1_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; @@ -731,7 +731,7 @@ ports { port@0 { reg = <0>; - dmic2_cif_ep: endpoint@0 { + dmic2_cif_ep: endpoint { remote-endpoint = <&xbar_dmic2_ep>; }; }; @@ -739,7 +739,7 @@ dmic2_cif_ep: endpoint@0 { dmic2_port: port@1 { reg = <1>; - dmic2_dap_ep: endpoint@0 { + dmic2_dap_ep: endpoint { /* Placeholder for external Codec */ }; }; From patchwork Thu Dec 9 17:24:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565970 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=MZf+2G7e; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CR3kqkz9sR4 for ; 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Thu, 09 Dec 2021 09:25:46 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 16/30] arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips Date: Thu, 9 Dec 2021 18:24:49 +0100 Message-Id: <20211209172503.617716-17-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The standard "jedec," vendor prefix should be used for SPI NOR flash chips. This allows the right DT schema to be picked for validation. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 6d4ed67ffeda..1323fa9b8301 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1878,7 +1878,7 @@ spi@3270000 { status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <102000000>; spi-tx-bus-width = <4>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 260de1122aa3..9fc4a8f46250 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1637,7 +1637,7 @@ spi@70410000 { status = "okay"; flash@0 { - compatible = "spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <104000000>; spi-tx-bus-width = <2>; From patchwork Thu Dec 9 17:24:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=hNYAQ2qI; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CR18ftz9sRK for ; Fri, 10 Dec 2021 04:25:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236159AbhLIR32 (ORCPT ); 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Thu, 09 Dec 2021 09:25:48 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 17/30] arm64: tegra: Drop unsupported nvidia,lpdr property Date: Thu, 9 Dec 2021 18:24:50 +0100 Message-Id: <20211209172503.617716-18-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property, so drop them from the device trees that have listed them. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 14868e877c63..8bdb129c4094 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -535,7 +535,6 @@ pex_rst_c5_out_state: pex_rst_c5_out { pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; @@ -547,7 +546,6 @@ clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = ; - nvidia,lpdr = ; nvidia,enable-input = ; nvidia,io-hv = ; nvidia,tristate = ; From patchwork Thu Dec 9 17:24:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=YVCSwtro; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CS6FYbz9sRK for ; Fri, 10 Dec 2021 04:25:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242834AbhLIR33 (ORCPT ); Thu, 9 Dec 2021 12:29:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242876AbhLIR31 (ORCPT ); Thu, 9 Dec 2021 12:29:27 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F13CEC0617A2 for ; Thu, 9 Dec 2021 09:25:52 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id c4so10909578wrd.9 for ; Thu, 09 Dec 2021 09:25:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hP601Qhn37r3S327PJpYVEaLJVJMjD0XlEb0Nd2Ee0w=; b=YVCSwtroXXa3lCMUR/HRw684kXBTZhm2Km9lRyf98zsHFHi+j0c5ta/kJpub61SI8t Ln2iTRY/PZ85KEvQMhOC+6IhbwqUMqbLzz/SI3A7OQQT6XQLG5tLATNjC/PTGf28CW9z Og5VNH4Y9AAndkLenVN4e8HaGEU0MM54KGxh3kvxLcna3Llo7NRszp+XUVV4Brl/2/xj 9aai4CdQNnmlHlqF4nHQ2SSpl004bJaRW8OdZ+75bOSmgqOcYDRC225opbIMmK3e5IFq M8W9Mig+D2/giN8nSAAuw73m/VfJ880XiiYB/4sBj3mSQLi4+YJdDxE5R4ZmZzOG/pmQ tP4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hP601Qhn37r3S327PJpYVEaLJVJMjD0XlEb0Nd2Ee0w=; b=3nLVO7FMMA8VDJwwQAR62J33U2Vj/9p0fjsJ3ObNGVfvUlvvEFsGnXh6cdAxJCHOLg QcUEhYgb35on5D0PKoDIOdyxuFc4bZRZVdEmcQ+5mpNpaSSx2YqDrQY3LPnnw/YXLnJs NJpccyHeUR8N8OXs5K9IfSCFyaWCCLuuhKoO4FwJugogCQqHDuso0mix6aypDS5sGuLo nFCr5Ahxl7zZzpXBhbRkyJf6BKFv04eJe3Q304mfcp3ksIsqhoVurU//zUIm7+wy+VCH xxWHic1rMI+VwRsjYWHcm3PUIUqBoW0bvqQX+PvuSjNR03+RqGCfBymblBwA3WqlS8Qe FxUA== X-Gm-Message-State: AOAM532hr57kM8AJoPMZG0SSkoiNfkTuF6qPFzTmPeFr6qBjaN67H/Vx Z9p4OiVmwfmct4lSzSWkH8M= X-Google-Smtp-Source: ABdhPJwBSm4s7i86a0XOZxgCrsSoj366T63caTQMt3EhMehg8rC9lkEeA2CNDRf5ob/NtEodnWM4SQ== X-Received: by 2002:a5d:668f:: with SMTP id l15mr7988722wru.182.1639070751346; Thu, 09 Dec 2021 09:25:51 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id d15sm393909wri.50.2021.12.09.09.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:50 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 18/30] arm64: tegra: Fix Tegra194 HSP compatible string Date: Thu, 9 Dec 2021 18:24:51 +0100 Message-Id: <20211209172503.617716-19-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The HSP instances on Tegra194 are not fully compatible with the version found on Tegra186, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 8bdb129c4094..675e9f5db2c3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1180,7 +1180,7 @@ cec@3960000 { }; hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; interrupts = , , @@ -1358,7 +1358,7 @@ p2u_hsio_11: phy@3f40000 { }; hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; + compatible = "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; interrupts = , , From patchwork Thu Dec 9 17:24:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565973 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=OC1woNge; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CV4gkqz9sR4 for ; Fri, 10 Dec 2021 04:25:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242876AbhLIR3a (ORCPT ); Thu, 9 Dec 2021 12:29:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242849AbhLIR33 (ORCPT ); Thu, 9 Dec 2021 12:29:29 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 254C9C061746 for ; Thu, 9 Dec 2021 09:25:55 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id v11so10903776wrw.10 for ; Thu, 09 Dec 2021 09:25:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QU8yqsZf4hKB+fILRAdxJxvXG8LL+orBzsCkhhSWakA=; b=OC1woNge25SlEzP+3iif4IbgPczqrCHBzT7D6IyUzio7aWgPzTIzIngaa856ksv0za p/VFpzmDj4BSNdEvwrxkdRyz1nhh4GQU8iaU9qgFQc47Yb069JrHA/eZuT9Z0LgERJt3 8ls8+sBw3JFmO1CHEG8miWFST84oNKpoysKL/Dj+04RNZ9Cz+fxaaf2PZvPHuWDYrzXs q8Rn7PWel3QuXfKwxhu5dNDsuODKfa8aRig/O/5Uo7wxNopGCbu8+vm/vADv20NZ/TJN zpL2G9BPa/aWACMDYc1MjtteCuIT8VQO1dX0JTtrlY9YN/WFFiMmFDRUF9GyH4z8Qs6o w7sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QU8yqsZf4hKB+fILRAdxJxvXG8LL+orBzsCkhhSWakA=; b=RSW6ZXqQ1b6DfP0bwx8fEakR4tQwnv9tZ6HBpmBOcuoSBcOIv49NNZf+5arFuxK0k5 1VCqAtSEeY89a08fQWB8yeElireGdkcQFP6hbkPXYWiPSgBAjONUPcDkV+1qKNBf+IDP NnIkT2005qDfT7I7PUrsKfR5XApghVPX541zxDYDnAXkQEHAn+kwzOANMpGZR3I6WRvs 9HY2oIvxxI+O8Mcj2egbropv86p8nZuQlCfbORqfrZXIjQ99qWJms8pAfgkUKPU/uOL8 Ed5Sc38ElQYbLxwRbvwa4xJIOi3hHO+kjRW5b+y0H9mnAty3FAwW1sK0Py5WxuG4n0KS jqpQ== X-Gm-Message-State: AOAM532nDETneaZKV7y6GJTz6nxgxdXw3lFa65ck190+xqa1QXrHxdQc qxy+BjYD4DxZ2o+VAjdPHGE= X-Google-Smtp-Source: ABdhPJzc8U18ZKJcnbp8ybrgXYC9jkmJdpzM+OiKbEt25MyB+vQgyCvrwOM0Uk+tIwirt4ut6SJ5sA== X-Received: by 2002:a05:6000:144a:: with SMTP id v10mr7803206wrx.315.1639070753710; Thu, 09 Dec 2021 09:25:53 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id x4sm9191551wmi.3.2021.12.09.09.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:52 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 19/30] arm64: tegra: Drop unused properties for Tegra194 PCIe Date: Thu, 9 Dec 2021 18:24:52 +0100 Message-Id: <20211209172503.617716-20-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The num-viewport property is never used and can be dropped, whereas the "iommus" property is not needed since we use "iommu-map-mask" and "iommu-map" already. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 675e9f5db2c3..969b965ee125 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2005,7 +2005,6 @@ pcie@14100000 { #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <1>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; @@ -2038,7 +2037,6 @@ pcie@14100000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE1>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2059,7 +2057,6 @@ pcie@14120000 { #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <2>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; @@ -2092,7 +2089,6 @@ pcie@14120000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE2>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2113,7 +2109,6 @@ pcie@14140000 { #size-cells = <2>; device_type = "pci"; num-lanes = <1>; - num-viewport = <8>; linux,pci-domain = <3>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; @@ -2146,7 +2141,6 @@ pcie@14140000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE3>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2167,7 +2161,6 @@ pcie@14160000 { #size-cells = <2>; device_type = "pci"; num-lanes = <4>; - num-viewport = <8>; linux,pci-domain = <4>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; @@ -2200,7 +2193,6 @@ pcie@14160000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2221,7 +2213,6 @@ pcie@14180000 { #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <0>; clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; @@ -2254,7 +2245,6 @@ pcie@14180000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2275,7 +2265,6 @@ pcie@141a0000 { #size-cells = <2>; device_type = "pci"; num-lanes = <8>; - num-viewport = <8>; linux,pci-domain = <5>; pinctrl-names = "default"; @@ -2312,7 +2301,6 @@ pcie@141a0000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2352,7 +2340,6 @@ pcie-ep@14160000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE4>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2392,7 +2379,6 @@ pcie-ep@14180000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE0>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; iommu-map-mask = <0x0>; dma-coherent; @@ -2435,7 +2421,6 @@ pcie-ep@141a0000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_PCIE5>; iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 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Thu, 09 Dec 2021 09:25:55 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 20/30] arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock Date: Thu, 9 Dec 2021 18:24:53 +0100 Message-Id: <20211209172503.617716-21-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The "core_m" clock is not documented in the Tegra194 PCIe device tree bindings, so remove it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 969b965ee125..941027049b9a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2270,9 +2270,8 @@ pcie@141a0000 { pinctrl-names = "default"; pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, <&bpmp TEGRA194_RESET_PEX1_CORE_5>; From patchwork Thu Dec 9 17:24:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=WEVbplv7; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91CY6LjQz9sRK for ; Fri, 10 Dec 2021 04:26:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242861AbhLIR3e (ORCPT ); Thu, 9 Dec 2021 12:29:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242916AbhLIR3e (ORCPT ); Thu, 9 Dec 2021 12:29:34 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231B6C061D5E for ; Thu, 9 Dec 2021 09:26:00 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id o13so10887113wrs.12 for ; Thu, 09 Dec 2021 09:26:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YKUA83lC1/7b/546A55OKYb7LyGPLVF+6DqqJAKToS8=; b=WEVbplv7KC6XbtcYK6JIx/5PAvv/eNcML2pf8jhRy9KiIr5YhvHBgSyjrPq4VpEhWZ LzcUk0eMMLvN3RC5hgUNzeFphfR2fkFGVlcV9LOCXm/fXXr2Veo8oLsVTXuPay1CfGQP 3CkpSFjyYveFz/NT99SuyEMhRci6Y9CIu8Kz9a1aRr/zjZWqLA2G6kKn+vKW9GaDaCTA 5W62+u0VeUsgx51HXzhQn7U2uj4plrgpLmBOtQiSsAIQtA8hnOjlR1iXWEtfIhVr+Xje 1zUORBJ5FInmL+pC+z05XjtE94Xne1y/1Yex5+s3pOAvOqGHL4KozwcZkdPnKLmQyG3t 3MDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YKUA83lC1/7b/546A55OKYb7LyGPLVF+6DqqJAKToS8=; b=2OS0fnxc1C43VRTRlt0XnpDJq0ZwHvyEeWp6BI3OZdrJXKVKwY/z1kaOoTdbTVFVIR KER5aplj5w+zKAJH0hgKqFuROo16fgbu0/0xj1S7tO4hUnTTUkwcSBK8boNWDMk5lF/s 5WkZCwhizcbekKpGS/msIeMM8YnHT1pfQxLIioCbSP2ACLLg3qrhRjWDHEmC/xWe6El8 jo9LvgN0H92ymtTK7qvkqh9+1ia/5AuFR+zcXIvoCIsvFqtXFicXk/hz+dv0R6XGw+M8 hkhiDGgbpDq0l8f8/PoAZDPOzwOrZYIpL1Jgg2yCpEjkxINhwVcO95SImCD0a4jKmd1j zd1g== X-Gm-Message-State: AOAM533w3Pehx+O9z86ATyPhLBWCU/SVrMql1AD3hePaDMuf3aC0TE9b osweWYZFDJp78QLirPvA5wA= X-Google-Smtp-Source: ABdhPJyE/QDqhv8fr9mjeV2q1AwMlgIfnydsUKRBeznCkUdg3mWVHniDf+Liv2IYOEa5HmgE114tXA== X-Received: by 2002:a05:6000:381:: with SMTP id u1mr8126145wrf.383.1639070758607; Thu, 09 Dec 2021 09:25:58 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id 4sm432348wrz.90.2021.12.09.09.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:25:57 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 21/30] arm64: tegra: Rename TCU node to "serial" Date: Thu, 9 Dec 2021 18:24:54 +0100 Message-Id: <20211209172503.617716-22-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The TCU is basically a serial port (albeit a fancy one), so it should be named "serial". Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 941027049b9a..416a6b6e434c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2713,7 +2713,7 @@ sound { iommus = <&smmu TEGRA194_SID_APE>; }; - tcu: tcu { + tcu: serial { compatible = "nvidia,tegra194-tcu"; mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; From patchwork Thu Dec 9 17:24:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Pgh6SkNp; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Cc05Vcz9sR4 for ; Fri, 10 Dec 2021 04:26:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242881AbhLIR3g (ORCPT ); Thu, 9 Dec 2021 12:29:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242895AbhLIR3g (ORCPT ); Thu, 9 Dec 2021 12:29:36 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E926C0617A2 for ; Thu, 9 Dec 2021 09:26:02 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id v11so10904330wrw.10 for ; Thu, 09 Dec 2021 09:26:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MARabD0/4tRPvJ2q3gq3hMDxVcq3lmHsCCAcfrcrGRQ=; b=Pgh6SkNp8ipGo+YONGbeMrBjOAG2siAvvMxl4Hv8g/SYJCGLEGTh43Cul+zvyymdYD TYYIFnIm6fEKQ0lRCiF7lNa3Pa4bvNXYc1frF7mToDMLcx/fg9YSXYgJMUP1d3f7B4s5 PLylNdV+aciMIs28zNNXhnseeMNX/sSZd36vk7x40ZKmG8wQgDqIb0UElaf9sqbsIOSO Bvw0tz1MG6J0ZEFbWuGb5iFnBc50xuu6zSo6z/7g28tqom2AvBDkaN/qRGEkr1Af7IRx lP3zrgVBDSRNkcDEI+y4e/34nSYXniPf+1QchEG/gF1ExN5fOHLpsqAq4WednMHaV5AW CF/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MARabD0/4tRPvJ2q3gq3hMDxVcq3lmHsCCAcfrcrGRQ=; b=qo3yGaYPWcUsK+6/9SnYc9OLR3GqvVKz6xUjn6mQTCYA0ifY79Cd2K9FlrqH5AwENt lrSZzqSyY1shM1eII0VMmJR9I62oUI2D2HoBDmE49bSWC3M468q0TpCWyeIA6Y5A4sd/ Jsbhn63D9xF+YWxDcoMy7kyqpkZkKKyUQJTJMUZ85KPMTCmirn7g60FZ4mBCTHboC3PQ onyUPT33Y9/ZXavtJedNnCKcNuSStnANRXyDMNzcVxvQkvvXnXN3l/0ZMrqmnIM3cnCB 8o+q1KKDwI4uGqum4rEe5QY5A4v2qTC8e9x5FmVBAXkHAzaASXNJfxvxZ8+UFN2aa79M Vvuw== X-Gm-Message-State: AOAM530KR7AwbvhP+Qzc2elp6+wf9GfUQZnc1a1yc/IxLnfQkxEN9TRN fjSdDfSrAvGyggnOO9Dd/pU= X-Google-Smtp-Source: ABdhPJytmdKZALxP3eJo+Xg//9iF9Moln4fv2YfXemfZ35DJZUpa9a4BEScMUtCRvzv36EWAbmUcPA== X-Received: by 2002:a05:6000:258:: with SMTP id m24mr7897594wrz.471.1639070761124; Thu, 09 Dec 2021 09:26:01 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l8sm11115858wmc.40.2021.12.09.09.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:00 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 22/30] arm64: tegra: Remove unsupported regulator properties Date: Thu, 9 Dec 2021 18:24:55 +0100 Message-Id: <20211209172503.617716-23-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Remove the unsupported "regulator-disable-ramp-delay" properties which ended up in various DTS files for some reason. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 2 -- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 11 ----------- 2 files changed, 13 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 34276a84c68a..21d7e653ea5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1588,7 +1588,6 @@ vdd_3v3_sys: regulator-vdd-3v3-sys { vin-supply = <&vdd_sys_mux>; regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; }; vdd_5v0_io: regulator-vdd-5v0-io { @@ -1610,7 +1609,6 @@ vdd_3v3_sd: regulator-vdd-3v3-sd { vin-supply = <&vdd_3v3_sys>; regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; }; vdd_dsi_csi: regulator-vdd-dsi-csi { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 9fc4a8f46250..542f51c07781 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ vdd_soc: sd0 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -282,7 +281,6 @@ vdd_ddr: sd1 { regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <300>; regulator-always-on; @@ -298,7 +296,6 @@ vdd_pre: sd2 { regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <350>; regulator-always-on; @@ -314,7 +311,6 @@ vdd_1v8: sd3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; regulator-ramp-delay = <27500>; regulator-ramp-delay-scale = <360>; regulator-always-on; @@ -330,7 +326,6 @@ vdd_sys_1v2: ldo0 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-always-on; @@ -346,7 +341,6 @@ vdd_pex_1v05: ldo1 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -360,7 +354,6 @@ vddio_sdmmc: ldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -378,7 +371,6 @@ vdd_rtc: ldo4 { regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; @@ -403,7 +395,6 @@ avdd_1v05_pll: ldo7 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -417,7 +408,6 @@ avdd_1v05: ldo8 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; regulator-ramp-delay = <100000>; regulator-ramp-delay-scale = <200>; @@ -1779,7 +1769,6 @@ vdd_3v3_sys: regulator-vdd-3v3-sys { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; regulator-always-on; regulator-boot-on; From patchwork Thu Dec 9 17:24:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Thu, 09 Dec 2021 09:26:03 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id b14sm441673wrd.24.2021.12.09.09.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:02 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 23/30] arm64: tegra: Rename GPIO hog nodes to match schema Date: Thu, 9 Dec 2021 18:24:56 +0100 Message-Id: <20211209172503.617716-24-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 5cfbc0394173..10347b6e6e84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1383,7 +1383,7 @@ gpio5_6_7 { }; }; - gpio@0 { + hog-0 { gpio-hog; output-high; gpios = <2 GPIO_ACTIVE_HIGH>, From patchwork Thu Dec 9 17:24:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=f8X14Sof; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Cj0Zsgz9sR4 for ; Fri, 10 Dec 2021 04:26:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242897AbhLIR3l (ORCPT ); Thu, 9 Dec 2021 12:29:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242849AbhLIR3l (ORCPT ); Thu, 9 Dec 2021 12:29:41 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89756C0617A2 for ; Thu, 9 Dec 2021 09:26:07 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id p18so4780503wmq.5 for ; Thu, 09 Dec 2021 09:26:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FmEinY/5uVNYNxyaDWgspKUD761Zc1fxSgpPY3U7fJ0=; b=f8X14SofaJszvmVzFDRNorfFSW8EXqQ33rMO0IzahPsJLwulkiUd7Vuw9LHQ3nABhT Fp0rM3gXyjimYC6YfhFgwWgtZG6QuFqXVqkxvQfRlxLqIiHdZz3ftrE/kMzGXcE37wxN UBVSIsXA4PihStMsZ4FoXCLXLslPCIJjReTOxW9Wugh2gVMAUF8rAOFUYS7l2bSj1s1e bvPSWXZHM0ak/XjISJ6MP8EL88nNtRYvCz07IGm4YO7g79UJHZdrXNhVub83U0OoLxg1 NBaB2kmVB4oZKORPVS8iHs8vFekbHqRNA1yw/Rnh33zUkq5sSLlcoRgMwGMp1JuGMGrE U65w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FmEinY/5uVNYNxyaDWgspKUD761Zc1fxSgpPY3U7fJ0=; b=eeE76rcotQfw76ofPKFvAqeE73WIuoU2Rewja4M4Edi8dCtwWMm7Q2xIBh+jphJ9L3 pI2h6xRrJmF/Iwt8m9CAzA17UZHeZUt1XA6CyAy6wXbV4xcQ/P3dYDKEKZUEfc7rBsGP HQGM3XCqmXnxXXKzamrye7mayOwSo6robcV3zaNam4pN+WsG5jmdCVXTR6IqYrrdyMCF uz5xi7nZ2jgXpl2RPjqcTuagjUioOmBon9uGDmt5khe0kg8fEaPSpv3qHm72xOuzHD6W jGR3IJVOHC+Z7WLfi1njpZozJfI0PfvIKAo8rRm6jEXHMQF8XwkqQ8UHSx9Oemn6SyyW mYaQ== X-Gm-Message-State: AOAM531ZkBMxliqeC3FEVWnp+HcmRSd+k2tCMLkA6OOBhdgyueybbNpK 4aBFuHTDJ8NclqmwZZtj+9TLaRqhGpkXXQ== X-Google-Smtp-Source: ABdhPJzwGfGNrKmaUyd3r4UUunTFHz42p3rF8V2nuXn+EQv3Q8BHY3WygiKPPGxcu09O3RUneBOdNQ== X-Received: by 2002:a05:600c:1914:: with SMTP id j20mr9088201wmq.26.1639070766084; Thu, 09 Dec 2021 09:26:06 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id l21sm287278wrb.38.2021.12.09.09.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:05 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 24/30] arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB Date: Thu, 9 Dec 2021 18:24:57 +0100 Message-Id: <20211209172503.617716-25-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 3 --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 5 ----- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 2e17df6f20ad..328fbfec4ee8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -11,11 +11,8 @@ / { pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 21d7e653ea5b..4b43b89a9651 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1361,11 +1361,6 @@ usb@70090000 { dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; From patchwork Thu Dec 9 17:24:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=m6X4gLD0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Cl4v1Yz9sR4 for ; Fri, 10 Dec 2021 04:26:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242895AbhLIR3o (ORCPT ); Thu, 9 Dec 2021 12:29:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242849AbhLIR3o (ORCPT ); Thu, 9 Dec 2021 12:29:44 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31EADC061746 for ; Thu, 9 Dec 2021 09:26:10 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id a9so10923109wrr.8 for ; Thu, 09 Dec 2021 09:26:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1GO+LWP+0ftFzZu1gijSvoWuq3Wg7/UVL1CoHMkD1ak=; b=m6X4gLD0DBdK5SxESy75nWOsokb5EQ00UhRKd6WiD16Sq9AITPvfB4d+7mnCXV7x9z nC+s5zvOc4CMX3VhSQtHYSkNkoat4Kt4AA2UQGapgHrz+oi8JfimAxrb9IJXe23wdP/F qzmEZrmoLSoaDgFm+V8tf2Ux36Ze/0TzjlVyOqiowaXXd3om+Y2eaeNf8g/pLIm+siwQ SQtblVE1g9BUQoW26G/VcIZLsUdyY81ozq81w4rB1sUeInQW31YFsAa9dP5hJK9R27Hi wcJW1emknHZtT/8JVz1hoH6x9/hQefKkvVfLmcX2IDLH5oUON4NK69JoMDUUkafVzrgF 925A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1GO+LWP+0ftFzZu1gijSvoWuq3Wg7/UVL1CoHMkD1ak=; b=1IZzqIWjEL/c+rRiB9TbRxZ0tn3aNfRvz/3u+jXLvoQkhsbjbulTMnftQw8X180NG5 5uK9zBCN2a3T/ot8wGz+QRRxWHogtXIpqnU9Zy28qBT+uEDjOi/3EGgwpF3VgxkUwhbd Iu4zhdQ5DkAF0qc7oSqTzD8DLWoNXSkqXV6cCKsk0VzrdqEpisbYhMqDNT8r+4e+xVtc tGvB68klBMUjlvRjglUtpAi4o6CIa4a8Den07poyYDBf6b8JLmAxnQZDh49TYvRQkgAl 7sGj/9xaiGJ/wT7V3YUsZ7L9f4qgCjRXv2HNibYw0LULBT3fB6U6OGHvquXyTYviZ0xD Aa1Q== X-Gm-Message-State: AOAM533udLfAxCert91sEFC13ufS5cnXdgixhxipic6S+V+9j0297jrS ln/ZDL/eQFedlBiQL6vTsWg= X-Google-Smtp-Source: ABdhPJwQfseReUP1gr6d43JoaLvYfLkOkNSwBUsFZ2MJ5yfrFeLcL4cMnIVRS/Nh3EFGXD/IpicXiQ== X-Received: by 2002:a5d:4ccc:: with SMTP id c12mr8078753wrt.453.1639070768703; Thu, 09 Dec 2021 09:26:08 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id m1sm381360wme.39.2021.12.09.09.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:07 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 25/30] arm64: tegra: smaug: Remove extra PLL power supplies for XUSB Date: Thu, 9 Dec 2021 18:24:58 +0100 Message-Id: <20211209172503.617716-26-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the XUSB controller device tree node. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 6d59c28ff2a3..a263d51882ee 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1642,10 +1642,6 @@ usb@70090000 { dvddio-pex-supply = <&avddio_1v05>; hvddio-pex-supply = <&pp1800>; avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; status = "okay"; }; From patchwork Thu Dec 9 17:24:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565980 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=HayYS88h; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Cn432xz9sR4 for ; Fri, 10 Dec 2021 04:26:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242849AbhLIR3q (ORCPT ); Thu, 9 Dec 2021 12:29:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242908AbhLIR3q (ORCPT ); Thu, 9 Dec 2021 12:29:46 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 722EDC0617A1 for ; Thu, 9 Dec 2021 09:26:12 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id c4so10910880wrd.9 for ; Thu, 09 Dec 2021 09:26:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JtXU+DMDLDfLNzDZiFdyBboIv/D+jS1WmRGKpwuk5kU=; b=HayYS88hRj4tw298S/zFWFJnR8qPyxZ61yNfsaOIS2Fycf9m+T/8aEzE6RnsrRRmGy Epz4RkGl89IFHW+RuGGjoR708z8TQY7j8YlteSzwvKWZQAjtg0jXOPqncnIoZWvnQvK6 TTld3pk5wJrl3v20Z4E40CGGcPfopAyCoFo49iZcdmxMsmOrsHBHmK0qJVaNg/Ut8Sav A0FNJvHa/zhDect07WVtM9SCxxCtNAEtmKC3b6sVVexR+bn62XT2LEvR0Khpfr9yOt0E SHaZyrQhdL8di2evVrI4qZR1RS5WZG9UgHE96Zoid7sDgT1qShGG7akzg8qvpMEO7jih IPjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JtXU+DMDLDfLNzDZiFdyBboIv/D+jS1WmRGKpwuk5kU=; b=zgYXsbci4zIrKHA5E7vSmXzcAdAoTK4Omk8uu+Kh7Fzw8huQaG+nKsleI8pwA7LrmN dSxlE+dz8HEYFEsDaJq+WTDe0+HWjOS01OlKdN81ZOC9Yo2GzjBJzM2yqf6f99coX6iX qTjjH+jAn57gRA0sRzjETaAIczqW/XDRxHQo0D6wfBHxEzZ8Q9ZPp+c4DsV1WdMjJ1fy K3Lvpcf1cfVqjSsCRmweTdHbTvd4rrW2g+rqySB7MeWH8b+L/mWxnNo9uOcfg/M9gVK9 JZa2JbReoWkjn8uytsFYJmcBn01yWrfLNv0rw1ZKU0louErpfkepp5lsA48jg1GZX506 zMGQ== X-Gm-Message-State: AOAM532uRnn05okhNWmn+PnYzsMw1qSmsV5uXpZlKrFWGt/AF2WURaV0 qAoZEkuHgwazpKHx2d1niEs= X-Google-Smtp-Source: ABdhPJxC8rEm7rFuNzhWNt1v6BNg5BUwhPLtSP/AmT7HI8XWWAlfYt1/xjhr8chmvcu8NYfXOCmfgw== X-Received: by 2002:a5d:614f:: with SMTP id y15mr7937627wrt.587.1639070770989; Thu, 09 Dec 2021 09:26:10 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id v2sm355105wmc.36.2021.12.09.09.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:10 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 26/30] arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB Date: Thu, 9 Dec 2021 18:24:59 +0100 Message-Id: <20211209172503.617716-27-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The XUSB pad controller handles the various PLL power supplies, so remove any references to them from the PCIe and XUSB controller device tree nodes. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 542f51c07781..72c2dc3c14ea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -30,11 +30,8 @@ memory@80000000 { pcie@1003000 { status = "okay"; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; vddio-pex-ctl-supply = <&vdd_1v8>; pci@1,0 { @@ -446,11 +443,6 @@ usb@70090000 { avdd-usb-supply = <&vdd_3v3_sys>; dvddio-pex-supply = <&vdd_pex_1v05>; hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; status = "okay"; }; From patchwork Thu Dec 9 17:25:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=lr6+oavR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91Cv6rS5z9sR4 for ; Fri, 10 Dec 2021 04:26:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242916AbhLIR3w (ORCPT ); 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Thu, 09 Dec 2021 09:26:16 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 27/30] arm64: tegra: Add missing TSEC properties on Tegra210 Date: Thu, 9 Dec 2021 18:25:00 +0100 Message-Id: <20211209172503.617716-28-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Add missing interrupts, clocks, clock-names, reset and reset-names properties for the TSEC blocks found on Tegra210. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index af9237ad03c1..a49a12fd84b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -181,6 +181,12 @@ csi@838 { tsec@54100000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54100000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSEC>; + clock-names = "tsec"; + resets = <&tegra_car 83>; + reset-names = "tsec"; + status = "disabled"; }; dc@54200000 { @@ -283,6 +289,11 @@ nvenc@544c0000 { tsec@54500000 { compatible = "nvidia,tegra210-tsec"; reg = <0x0 0x54500000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_TSECB>; + clock-names = "tsec"; + resets = <&tegra_car 206>; + reset-names = "tsec"; status = "disabled"; }; From patchwork Thu Dec 9 17:25:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=guU+ZHoQ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91D20vk0z9sRK for ; Fri, 10 Dec 2021 04:26:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242923AbhLIR36 (ORCPT ); Thu, 9 Dec 2021 12:29:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242909AbhLIR3z (ORCPT ); Thu, 9 Dec 2021 12:29:55 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41BA1C0617A1 for ; Thu, 9 Dec 2021 09:26:21 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id p18so4780975wmq.5 for ; Thu, 09 Dec 2021 09:26:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kBEjgRxgfoRVXGZCM6MVItRDdpQixa9AaVYQQVghp+w=; b=guU+ZHoQ7Re5lG0VKZ8FrwhFceKaSwQfwJdyK5rtXe70+tAtRzKrz/eW+AFiDNaB5m jdNbHoTjBxPvunSqe8nXvLt6/aFDJ30UjnjjEra7wQZ+5om1r2nTD7WJDUTr2jPzccdc kiYnHSSESX1rNVrtHGxAcqFjPm06BuCXggUQNp/uz1IX5GnTIOth+az5ctx2IjfoNweK SgS8Cgl626TcvtJpEtFrzUiMTdkir0xj4SlePe16GHqY/v7ciEPk5dZ9LaElhhO6Lvh2 373QRHaa28mHWgaWAxKmBR/nzDqfmVYPitk7CQVIh+hfOh0PhxVXzoZ+S+Y9sFFg5c0y bknw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kBEjgRxgfoRVXGZCM6MVItRDdpQixa9AaVYQQVghp+w=; b=gjei7SG54fAzXxHZiCkqmaXM69PexX1/0TWMfoqG5PfItVX0egxyAHefBkWmB5yPf0 JkC374n9OJ6mNl/GgaRLVoAuwGEk+Fq0JNmwu0iNJ81vlIccjY8GiTza8erD8zURl7vr snVWyQzjpU8D36BboiZs4Qz7z8iVskWlQxbzI9QI2FViFojVPJ6Y9/bfv2EIO1MCkS3t j8VBtlko/3cQSdvxrJ86DLRQwcyUkYqfvA3RBKrxFd1qkoGpCjb5MuHSRP/vDz4mxuCP 5UzQyV7tlNCwU009Ls1xMqJpmqBhm5HDJXTHe06/C0K8tPH+fGBQ2CWnGvbCrMjgt/Jw gQHA== X-Gm-Message-State: AOAM531zCQchR3cYgChVJKbbNawx0hM9oFDxbTyId2Qw/wvR5CbS/Ff5 OMyGw6oNoU2hny4L5sjkOK7UlzhdLT5W+Q== X-Google-Smtp-Source: ABdhPJyDJHC2Uz8fpEOHw0ckHaTxmKX6wpnu9cvd4EWGDp7snTRDzxhRAK/9UXBb2nZbRSyXS7XX1Q== X-Received: by 2002:a1c:f609:: with SMTP id w9mr8772207wmc.99.1639070779860; Thu, 09 Dec 2021 09:26:19 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id w7sm279500wru.51.2021.12.09.09.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:19 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 28/30] arm64: tegra: Sort Tegra210 XUSB clocks correctly Date: Thu, 9 Dec 2021 18:25:01 +0100 Message-Id: <20211209172503.617716-29-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a49a12fd84b1..aa768ea108fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1026,8 +1026,8 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, <&tegra_car TEGRA210_CLK_PLL_U_480M>, @@ -1035,7 +1035,7 @@ usb@70090000 { <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; resets = <&tegra_car 89>, <&tegra_car 156>, From patchwork Thu Dec 9 17:25:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565982 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Kfq/iLJF; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91D15G0vz9sR4 for ; Fri, 10 Dec 2021 04:26:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242908AbhLIR36 (ORCPT ); Thu, 9 Dec 2021 12:29:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242923AbhLIR35 (ORCPT ); Thu, 9 Dec 2021 12:29:57 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFB83C061A72 for ; Thu, 9 Dec 2021 09:26:23 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id u17so10974016wrt.3 for ; Thu, 09 Dec 2021 09:26:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h0h66338u5hSxqQTPm/OSloK0s/WKr6FBpTI53AOt90=; b=Kfq/iLJFifc6+N7cac+YoXGag5MCo8ryyg/Lz+4gTHMK2jGGi6M6/X3s3bpmnCnMM1 NUcxtmEmn1vfTjtJISEec5ZaTMjowte07U0xUiGMTIQnoNmaWUB6QbW/+JNQmz2DaK1k lXJIQArX2CIYTGou9PfBihUHSyFEYkLpdp+B/4e4dWhynFC8ZOdupf6J3/aziZGGMBrT 6UJ8fYJJVXHcKo5C7Cxr3kAhcyD149O8xcZcr2qdw8m55X3fuMfggDxZqQxtlRD5LLvd q7yjm3fQqu0w7GDlovbRKHDwdvlkVy8RVu4OURAW19aCdpmV0efw0r1e9xaJXvQxNlAz c8PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h0h66338u5hSxqQTPm/OSloK0s/WKr6FBpTI53AOt90=; b=biH3+gsgTNlM1SKG4BobM0BDagSzntMCvhznewZguObHlIqxqTcF23PIVwf9UBOyVO L7WXIMl3StK4wseaxo/L6Mz3Lr9eVred4O5i8XX92olyVVbJNUW5XCnFmjU8N+Fc0+hl VW1IoRUN5K/btsXDJ5ObgJ+d1mtQgz+0OHnvg+/KVoHzvElVHAfQJowUHZ6P9Mr/lKJ8 OYF1etQKX7MZwsKq5dWmrMUXdcEjPlSDmHK5Wr4P3ThFJza1KpQfhCZIF1h/ZBlPY0pi vXw3aK2vJ/ciuYxiMVl5xxPwerjRuTl5Zm6ES8ZS9muwZQb5cp7Dsdz9M8x7Q1qEVBwL iOMA== X-Gm-Message-State: AOAM533Tt0TOstRNf8hR4JZ2oSlHCYDC4ZJVqepEJvj3BP5ukpXUpb3W AVOfqDophCylUtV9WfwNejw= X-Google-Smtp-Source: ABdhPJxpuQ0KpgReTM+uGi/YIBxAA4V4vJ6zvbTuOWc2mby/zla56MJgODQkCjuz7dxlgwcdW+fyeA== X-Received: by 2002:a05:6000:15c6:: with SMTP id y6mr8070376wry.422.1639070782294; Thu, 09 Dec 2021 09:26:22 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id z5sm11837844wmp.26.2021.12.09.09.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:21 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 29/30] arm64: tegra: Remove unused only-1-8-v properties Date: Thu, 9 Dec 2021 18:25:02 +0100 Message-Id: <20211209172503.617716-30-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The only-1-8-v property is not support by an DT schema, so drop it. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 - arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d3c936822186..d95a542c0bca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -11,7 +11,6 @@ mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts index b5d9a5526272..5804acfc428a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -26,7 +26,6 @@ mmc@3460000 { status = "okay"; bus-width = <8>; non-removable; - only-1-8-v; }; rtc@c2a0000 { From patchwork Thu Dec 9 17:25:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1565984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=idxzzZkm; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J91D52fxkz9sR4 for ; Fri, 10 Dec 2021 04:26:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242911AbhLIRaB (ORCPT ); Thu, 9 Dec 2021 12:30:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242909AbhLIRaA (ORCPT ); Thu, 9 Dec 2021 12:30:00 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EADCDC061746 for ; Thu, 9 Dec 2021 09:26:25 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id d9so10959494wrw.4 for ; Thu, 09 Dec 2021 09:26:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mMV1K9LSS8eWVfs7EIdhknisLwoEQBuheuCVW31krBk=; b=idxzzZkmXnBQc3b8sz2EY5ryPhYN76taYCJiT7dsC9kbHaKe0DiThUSBqdtwpUzeP4 onwCXeUefKU6HSP7Kea9qS+TEo9xQLI7ftpQ7XM692ruNAXvCdCGb9XEObz4CdLbZKVA i7v08EPXQMNTICM2pxx8KiJHFyx2JOe+rzLN+LhoJ4nnkWGo4UxFDFUyu1iU5SunklCj s2ZUOYRwCDAnzmWOWaFPJHAu37c0hbPTFevzb626Q8IFfp5JaWMlqCK6PcFDFV9AFhK2 tgJvR0CSP+g78ji4pTHXF9N9QDYwOUJFvQku+v/BU9ySaDLyWR6zfjMOELIN6MrvbJ+Q q2WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mMV1K9LSS8eWVfs7EIdhknisLwoEQBuheuCVW31krBk=; b=mHojxwKWPWdUpo6yasa/UPT36otYPh7nD+jycjdmdrmzhjasZZsXnKokKYkaYvIGri Gn3hnDOuli7t+Rsqh0bpOTPaXwjiBFMSFOTdpmAVz+SnnQabhNesHbS5/Wu6o7yHX0ou 9AMlwEj2VedZq0/cDu8gpXErXAMrjQCKEGtInMhZWLfXu0cP7VXUfVG+5I3p6sxCpub2 tgViVn4JWHQXPe7zZXWAyXZ1FdKfJ9VVNP39uqZXKDDjkDpFEHgSLc5kK/yek4B+KZht ShxER/I7kl/UzlHd5uYkigiNE8WNEPe4CFsui+uCfg4KyZuvdeqnfP1u/OUjHbRrXtZZ sLng== X-Gm-Message-State: AOAM5321vjJojOHNV/Jk+dHKFQqJfhMnqKlopOI+Ie02w8xHzPjZpL7f ZDkPkYMurFVk+5xoBTLPPWA= X-Google-Smtp-Source: ABdhPJzpRm3rY5r/pqw0G6NsCLB0Gmk2ICEx3jCsUrNaidavxGxAwusEfvOnuscgZbm80hgeqjGklQ== X-Received: by 2002:a05:6000:1201:: with SMTP id e1mr8345621wrx.298.1639070784504; Thu, 09 Dec 2021 09:26:24 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id m125sm9164732wmm.39.2021.12.09.09.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 09:26:23 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , linux-tegra@vger.kernel.org Subject: [PATCH 30/30] arm64: tegra: Rename Ethernet PHY nodes Date: Thu, 9 Dec 2021 18:25:03 +0100 Message-Id: <20211209172503.617716-31-thierry.reding@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211209172503.617716-1-thierry.reding@gmail.com> References: <20211209172503.617716-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Name the Ethernet PHY device tree nodes as expected by the DT schema. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 3d8878c0ec03..aff857df25cf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -44,7 +44,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 6cc51083adb7..4631504c3c7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -46,7 +46,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio_aon>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index ad217cac2b28..a7d7cfd66379 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -39,7 +39,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index f16b0aa8a374..0bd66f9c620b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -36,7 +36,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; interrupt-parent = <&gpio>;