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Thu, 9 Dec 2021 07:38:25 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 9 Dec 2021 07:38:25 +0000 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 8 Dec 2021 23:38:24 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v8 1/6] iommu/tegra-smmu: Rename struct iommu_group *group to *grp Date: Wed, 8 Dec 2021 23:38:17 -0800 Message-ID: <20211209073822.26728-2-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209073822.26728-1-nicolinc@nvidia.com> References: <20211209073822.26728-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 069d1c08-1175-4a67-856f-08d9bae6e553 X-MS-TrafficTypeDiagnostic: DM6PR12MB3082:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1775; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:29.7649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 069d1c08-1175-4a67-856f-08d9bae6e553 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.12];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3082 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org There are a few structs using "group" for their pointer instances. This gets confusing sometimes. The instance of struct iommu_group is used in local function with an alias "grp", which can separate it from others. So this patch simply renames "group" to "grp" as a cleanup. Acked-by: Thierry Reding Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 8e906504882d..fd9ef08cb7d9 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -24,7 +24,7 @@ struct tegra_smmu_group { struct list_head list; struct tegra_smmu *smmu; const struct tegra_smmu_group_soc *soc; - struct iommu_group *group; + struct iommu_group *grp; unsigned int swgroup; }; @@ -911,7 +911,7 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) /* Find existing iommu_group associating with swgroup or group_soc */ list_for_each_entry(group, &smmu->groups, list) if ((group->swgroup == swgroup) || (soc && group->soc == soc)) { - grp = iommu_group_ref_get(group->group); + grp = iommu_group_ref_get(group->grp); mutex_unlock(&smmu->lock); return grp; } @@ -928,23 +928,23 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) group->soc = soc; if (dev_is_pci(dev)) - group->group = pci_device_group(dev); + group->grp = pci_device_group(dev); else - group->group = generic_device_group(dev); + group->grp = generic_device_group(dev); - if (IS_ERR(group->group)) { + if (IS_ERR(group->grp)) { devm_kfree(smmu->dev, group); mutex_unlock(&smmu->lock); return NULL; } - iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release); + iommu_group_set_iommudata(group->grp, group, tegra_smmu_group_release); if (soc) - iommu_group_set_name(group->group, soc->name); + iommu_group_set_name(group->grp, soc->name); list_add_tail(&group->list, &smmu->groups); mutex_unlock(&smmu->lock); - return group->group; + return group->grp; } static int tegra_smmu_of_xlate(struct device *dev, From patchwork Thu Dec 9 07:38:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1565660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Wed, 8 Dec 2021 23:38:25 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v8 2/6] iommu/tegra-smmu: Rename tegra_smmu_find_group to tegra_smmu_find_group_soc Date: Wed, 8 Dec 2021 23:38:18 -0800 Message-ID: <20211209073822.26728-3-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209073822.26728-1-nicolinc@nvidia.com> References: <20211209073822.26728-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2bbf8b17-8b21-4337-cd7b-08d9bae6e6e8 X-MS-TrafficTypeDiagnostic: BN9PR12MB5066:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5+kxLd74LIZ3cSDu1jmXAPrVlU4gHSH24XX9d5Dg+hzDVf0Fu3PWuQwy7XCPOxGt3IUMeL312xKU9e2dVbWdR2wbODLnAGQ8bJcL/kW1dW9i9GCytmH4jZa5lviaDKVLUAk5AVDLnxzQ6xBFH5RLgRfmC6ChXnemyc3kMfn/48VMf4TcWL+wGcGjBcxT7QindO+8IOwkfCo2A6QzanKjH9P0P2O5ZAgys6vK8fKc8S3n6dcRa0ry49YfjyNoon3qLjAV55PMR306GnpczGnQtDgP0oPGe55+Ko/7NRWwG+FHEYm0iAhbxEihXzV/UcBvCABTxx+4/OZhl3GximTy4YynakiB443IQPbpqSDCuPM4pTxWlutT8kiDLGEYW81q34GuQn82KrR7JwjWuVniBnNvJzGPZzJ35oOsS52mRCjGVIUxA4NRyKitEqMvT+E0qEYtfrzZK6gGZoMuFt3lPLw8TUalNbORA9EFGQWinqqGr35PmQWypjQEBA/+eljvO8HZSKwL4ohq+plLIufscuNZO6+OSi5j4BBc0xPqL4H5rxGuzXwCDAeeJjkKIBf1mEu1/5VHR+UCs7gg8IoSxYUWNpVCaO2/DDgyb3nhWUPvGe1f4X4bw4vpH6NCA7IHgRnH0CyI+2b0mpnBEnLcmx2HuW2ES2sVHg/2heCsQlkxXmjmmbMMa5WhoN1gaMnT9sxPyooWJd4O5GjJH1KYCIxtqa2Ot6fwZSpiXBTmxYFvCsTIgnfssRSW4Vd3KdDTlrojEXs+9mw0fxK3ECLRFkmRDCubXh79D+1sZyB1szQ= X-Forefront-Antispam-Report: CIP:203.18.50.12;CTRY:HK;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:hkhybrid01.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(336012)(426003)(4326008)(2616005)(186003)(40460700001)(36756003)(70586007)(2906002)(8936002)(26005)(316002)(8676002)(70206006)(508600001)(86362001)(83380400001)(54906003)(110136005)(1076003)(47076005)(6666004)(36860700001)(5660300002)(7696005)(34070700002)(356005)(82310400004)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:32.1709 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2bbf8b17-8b21-4337-cd7b-08d9bae6e6e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.12];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5066 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The existing function tegra_smmu_find_group really finds group->soc pointer, so naming it "find_group" might not be clear by looking at it alone. This patch renames it to tegra_smmu_group_soc in order to disambiguate the use of "group" in this driver. Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index fd9ef08cb7d9..5628865c04b0 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -872,7 +872,7 @@ static struct iommu_device *tegra_smmu_probe_device(struct device *dev) static void tegra_smmu_release_device(struct device *dev) {} static const struct tegra_smmu_group_soc * -tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) +tegra_smmu_find_group_soc(struct tegra_smmu *smmu, unsigned int swgroup) { unsigned int i, j; @@ -904,7 +904,7 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) struct iommu_group *grp; /* Find group_soc associating with swgroup */ - soc = tegra_smmu_find_group(smmu, swgroup); + soc = tegra_smmu_find_group_soc(smmu, swgroup); mutex_lock(&smmu->lock); From patchwork Thu Dec 9 07:38:19 2021 Content-Type: text/plain; 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Thu, 9 Dec 2021 07:38:28 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 8 Dec 2021 23:38:26 -0800 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 8 Dec 2021 23:38:25 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v8 3/6] iommu/tegra-smmu: Rename struct tegra_smmu_swgroup *group to *swgrp Date: Wed, 8 Dec 2021 23:38:19 -0800 Message-ID: <20211209073822.26728-4-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209073822.26728-1-nicolinc@nvidia.com> References: <20211209073822.26728-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98e759fe-e4ff-4da6-f63f-08d9bae6e504 X-MS-TrafficTypeDiagnostic: DM6PR12MB2939:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:480; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:29.3055 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98e759fe-e4ff-4da6-f63f-08d9bae6e504 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.14];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2939 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org There are both tegra_smmu_swgroup and tegra_smmu_group structs using "group" for their pointer instances. This gets confusing to read the driver sometimes. So this patch renames "group" of struct tegra_smmu_swgroup to "swgrp" as a cleanup. Also renames its "find" function. Note that we already have "swgroup" being used for an unsigned int type variable that is inside struct tegra_smmu_swgroup, so it's not able to use "swgroup" but only something like "swgrp". Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 5628865c04b0..05a386036fce 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -336,35 +336,35 @@ static void tegra_smmu_domain_free(struct iommu_domain *domain) } static const struct tegra_smmu_swgroup * -tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) +tegra_smmu_find_swgrp(struct tegra_smmu *smmu, unsigned int swgroup) { - const struct tegra_smmu_swgroup *group = NULL; + const struct tegra_smmu_swgroup *swgrp = NULL; unsigned int i; for (i = 0; i < smmu->soc->num_swgroups; i++) { if (smmu->soc->swgroups[i].swgroup == swgroup) { - group = &smmu->soc->swgroups[i]; + swgrp = &smmu->soc->swgroups[i]; break; } } - return group; + return swgrp; } static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, unsigned int asid) { - const struct tegra_smmu_swgroup *group; + const struct tegra_smmu_swgroup *swgrp; unsigned int i; u32 value; - group = tegra_smmu_find_swgroup(smmu, swgroup); - if (group) { - value = smmu_readl(smmu, group->reg); + swgrp = tegra_smmu_find_swgrp(smmu, swgroup); + if (swgrp) { + value = smmu_readl(smmu, swgrp->reg); value &= ~SMMU_ASID_MASK; value |= SMMU_ASID_VALUE(asid); value |= SMMU_ASID_ENABLE; - smmu_writel(smmu, value, group->reg); + smmu_writel(smmu, value, swgrp->reg); } else { pr_warn("%s group from swgroup %u not found\n", __func__, swgroup); @@ -387,17 +387,17 @@ static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, unsigned int asid) { - const struct tegra_smmu_swgroup *group; + const struct tegra_smmu_swgroup *swgrp; unsigned int i; u32 value; - group = tegra_smmu_find_swgroup(smmu, swgroup); - if (group) { - value = smmu_readl(smmu, group->reg); + swgrp = tegra_smmu_find_swgrp(smmu, swgroup); + if (swgrp) { + value = smmu_readl(smmu, swgrp->reg); value &= ~SMMU_ASID_MASK; value |= SMMU_ASID_VALUE(asid); value &= ~SMMU_ASID_ENABLE; - smmu_writel(smmu, value, group->reg); + smmu_writel(smmu, value, swgrp->reg); } for (i = 0; i < smmu->soc->num_clients; i++) { @@ -1009,11 +1009,11 @@ static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) seq_printf(s, "------------------------\n"); for (i = 0; i < smmu->soc->num_swgroups; i++) { - const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; + const struct tegra_smmu_swgroup *swgrp = &smmu->soc->swgroups[i]; const char *status; unsigned int asid; - value = smmu_readl(smmu, group->reg); + value = smmu_readl(smmu, swgrp->reg); if (value & SMMU_ASID_ENABLE) status = "yes"; @@ -1022,7 +1022,7 @@ static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) asid = value & SMMU_ASID_MASK; - seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, + seq_printf(s, "%-9s %-7s %#04x\n", swgrp->name, status, asid); } From patchwork Thu Dec 9 07:38:20 2021 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:33.5771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1682f348-8c12-4e8a-9a71-08d9bae6e79b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.12];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3683 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch changes in struct tegra_smmu_group to use swgrp pointer instead of swgroup, as a preparational change for the "mappings" debugfs feature. Acked-by: Thierry Reding Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 05a386036fce..532c843eb631 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -24,8 +24,8 @@ struct tegra_smmu_group { struct list_head list; struct tegra_smmu *smmu; const struct tegra_smmu_group_soc *soc; + const struct tegra_smmu_swgroup *swgrp; struct iommu_group *grp; - unsigned int swgroup; }; struct tegra_smmu { @@ -899,18 +899,22 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct tegra_smmu *smmu = dev_iommu_priv_get(dev); const struct tegra_smmu_group_soc *soc; + const struct tegra_smmu_swgroup *swgrp; unsigned int swgroup = fwspec->ids[0]; struct tegra_smmu_group *group; struct iommu_group *grp; + /* Find swgrp according to the swgroup id */ + swgrp = tegra_smmu_find_swgrp(smmu, swgroup); + /* Find group_soc associating with swgroup */ soc = tegra_smmu_find_group_soc(smmu, swgroup); mutex_lock(&smmu->lock); - /* Find existing iommu_group associating with swgroup or group_soc */ + /* Find existing iommu_group associating with swgrp or group_soc */ list_for_each_entry(group, &smmu->groups, list) - if ((group->swgroup == swgroup) || (soc && group->soc == soc)) { + if ((swgrp && group->swgrp == swgrp) || (soc && group->soc == soc)) { grp = iommu_group_ref_get(group->grp); mutex_unlock(&smmu->lock); return grp; @@ -923,7 +927,7 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) } INIT_LIST_HEAD(&group->list); - group->swgroup = swgroup; + group->swgrp = swgrp; group->smmu = smmu; group->soc = soc; From patchwork Thu Dec 9 07:38:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1565659 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Wed, 8 Dec 2021 23:38:27 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v8 5/6] iommu/tegra-smmu: Attach as pointer to tegra_smmu_group Date: Wed, 8 Dec 2021 23:38:21 -0800 Message-ID: <20211209073822.26728-6-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209073822.26728-1-nicolinc@nvidia.com> References: <20211209073822.26728-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 72e1d09e-7795-40f3-6084-08d9bae6e592 X-MS-TrafficTypeDiagnostic: CH2PR12MB4086:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xxR4n76Bd5zopJuGlZuCVOayHOlQWRoxpTDWiStzfdDUHPWDpMYDtUq1O6EeT+aywGXP8+o7HuVBbizXbD2srIOWo1lH5bExIOM54HEjigfiupyzkp2Bn7OO3PxwXaKqxWvEqJAjEM+s++w/3FYh4UUQpFrsZm53KCUxe9HwPz+q2IRJlqOa3v1M5F226iQxlkz9RPkBL3ze2OKcfElIq5ZnlUyVSpmuSr9agMBIBz7OHJm9c9wKO6YLJ7ciAx45qKU6w5VNJbTwBBREaXJI8sAmdxePizcn2RerAR1mI6Zc+SDK1h8SRxKT4gmnGSury6QLj70yrAXhYA+nHbDu30be0A+KRBKmgWYS1z92zG2vizh4V1fTfG5lS1E1nLNdeCkH1MGqXoaMuwUDLMGKN381D+VD5bXAUHOQf+GMzVODnUMfwFUcxhlus7USEdIKJGKpDdouR18/f/CUmrBsc9QKkDnGvZzS6W/VbHtngwX4a5O+RlT0etWFMhcHdPfNdxgVXfc0Apn+wNhuy42xyIkxm2ufSOnA1aZM3ivSkv9K0KnyAQvGSPtFHu6Oad8Vslnt1q4uKKTYC5fNNiRfRQE0FiwJ0fzbsz3Tt6icXw9flSZf2HrkE2pe3Q84/HgZFTtrG5NZiVvhDlXHE31QtWXND05h+zZHTAmTssWnw1oQ1mg+59jCRlusuzOZkAMyafMjeMAn01CxekAKJehGaI953ijM2ayfJTZqfTaHoHWsEYs8xe9hoQOPkGVwobazi7VjIdf19oZURDfv8n6cjT9oJcygCHORagKz14qkwPg= X-Forefront-Antispam-Report: CIP:203.18.50.14;CTRY:HK;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:hkhybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(54906003)(110136005)(26005)(82310400004)(5660300002)(40460700001)(336012)(83380400001)(36756003)(2616005)(1076003)(70206006)(70586007)(356005)(47076005)(8676002)(186003)(316002)(4326008)(34070700002)(6666004)(2906002)(426003)(7636003)(8936002)(508600001)(86362001)(36860700001)(7696005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:30.2592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72e1d09e-7795-40f3-6084-08d9bae6e592 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.14];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4086 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This could ease driver to access corresponding as pointer when having tegra_smmu_group pointer only, which can help new mappings debugfs nodes. Also moving tegra_smmu_find_group_soc() upward, for using it in new tegra_smmu_attach_as(); and it's better to have all tegra_smmu_find_* functions together. Acked-by: Thierry Reding Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 96 +++++++++++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 532c843eb631..454504aa6602 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -25,6 +25,7 @@ struct tegra_smmu_group { struct tegra_smmu *smmu; const struct tegra_smmu_group_soc *soc; const struct tegra_smmu_swgroup *swgrp; + struct tegra_smmu_as *as; struct iommu_group *grp; }; @@ -351,6 +352,19 @@ tegra_smmu_find_swgrp(struct tegra_smmu *smmu, unsigned int swgroup) return swgrp; } +static const struct tegra_smmu_group_soc * +tegra_smmu_find_group_soc(struct tegra_smmu *smmu, unsigned int swgroup) +{ + unsigned int i, j; + + for (i = 0; i < smmu->soc->num_groups; i++) + for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) + if (smmu->soc->groups[i].swgroups[j] == swgroup) + return &smmu->soc->groups[i]; + + return NULL; +} + static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, unsigned int asid) { @@ -484,6 +498,59 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, mutex_unlock(&smmu->lock); } +static void tegra_smmu_attach_as(struct tegra_smmu *smmu, + struct tegra_smmu_as *as, + unsigned int swgroup) +{ + const struct tegra_smmu_swgroup *swgrp; + struct tegra_smmu_group *group; + + /* Find swgrp according to the swgroup id */ + swgrp = tegra_smmu_find_swgrp(smmu, swgroup); + if (!swgrp) + return; + + mutex_lock(&smmu->lock); + + list_for_each_entry(group, &smmu->groups, list) { + if (group->swgrp != swgrp) + continue; + if (group->as == as) + break; + + if (group->as) + dev_warn(smmu->dev, + "overwriting group->as for swgroup: %s\n", swgrp->name); + group->as = as; + break; + } + + mutex_unlock(&smmu->lock); +} + +static void tegra_smmu_detach_as(struct tegra_smmu *smmu, + unsigned int swgroup) +{ + const struct tegra_smmu_swgroup *swgrp; + struct tegra_smmu_group *group; + + /* Find swgrp according to the swgroup id */ + swgrp = tegra_smmu_find_swgrp(smmu, swgroup); + if (!swgrp) + return; + + mutex_lock(&smmu->lock); + + list_for_each_entry(group, &smmu->groups, list) { + if (group->swgrp != swgrp) + continue; + group->as = NULL; + break; + } + + mutex_unlock(&smmu->lock); +} + static int tegra_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { @@ -497,11 +564,15 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, return -ENOENT; for (index = 0; index < fwspec->num_ids; index++) { + unsigned int swgroup = fwspec->ids[index]; + err = tegra_smmu_as_prepare(smmu, as); if (err) goto disable; - tegra_smmu_enable(smmu, fwspec->ids[index], as->id); + tegra_smmu_attach_as(smmu, as, swgroup); + + tegra_smmu_enable(smmu, swgroup, as->id); } if (index == 0) @@ -511,7 +582,10 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, disable: while (index--) { - tegra_smmu_disable(smmu, fwspec->ids[index], as->id); + unsigned int swgroup = fwspec->ids[index]; + + tegra_smmu_disable(smmu, swgroup, as->id); + tegra_smmu_detach_as(smmu, swgroup); tegra_smmu_as_unprepare(smmu, as); } @@ -529,7 +603,10 @@ static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *de return; for (index = 0; index < fwspec->num_ids; index++) { - tegra_smmu_disable(smmu, fwspec->ids[index], as->id); + unsigned int swgroup = fwspec->ids[index]; + + tegra_smmu_disable(smmu, swgroup, as->id); + tegra_smmu_detach_as(smmu, swgroup); tegra_smmu_as_unprepare(smmu, as); } } @@ -871,19 +948,6 @@ static struct iommu_device *tegra_smmu_probe_device(struct device *dev) static void tegra_smmu_release_device(struct device *dev) {} -static const struct tegra_smmu_group_soc * -tegra_smmu_find_group_soc(struct tegra_smmu *smmu, unsigned int swgroup) -{ - unsigned int i, j; - - for (i = 0; i < smmu->soc->num_groups; i++) - for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) - if (smmu->soc->groups[i].swgroups[j] == swgroup) - return &smmu->soc->groups[i]; - - return NULL; -} - static void tegra_smmu_group_release(void *iommu_data) { struct tegra_smmu_group *group = iommu_data; From patchwork Thu Dec 9 07:38:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1565661 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=iH5NRE1E; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4J8m9r3n4sz9sRK for ; Thu, 9 Dec 2021 18:38:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233952AbhLIHmM (ORCPT ); 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Thu, 9 Dec 2021 07:38:30 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 9 Dec 2021 07:38:28 +0000 Received: from Asurada-Nvidia.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 8 Dec 2021 23:38:27 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH v8 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Date: Wed, 8 Dec 2021 23:38:22 -0800 Message-ID: <20211209073822.26728-7-nicolinc@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211209073822.26728-1-nicolinc@nvidia.com> References: <20211209073822.26728-1-nicolinc@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1825133c-c72f-4569-219a-08d9bae6e632 X-MS-TrafficTypeDiagnostic: DM6PR12MB4944:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:392; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2021 07:38:31.1457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1825133c-c72f-4569-219a-08d9bae6e632 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.13];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4944 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch dumps all active mapping entries from pagetable to a debugfs directory named "mappings". Part of this patch for listing all swgroup names in a group_soc is provided by Dmitry Osipenko Attaching an example: [SWGROUP: xusb_host] [as: (id: 5), (attr: R|W|-), (pd_dma: 0x0000000080005000)] { [index: 1023] 0xf0080007 (count: 52) { PTE RANGE | ATTR | PHYS | IOVA | SIZE [#913 , #913 ] | 0x7 | 0x0000000101fbe000 | 0xfff91000 | 0x1000 [#914 , #914 ] | 0x7 | 0x0000000101fbd000 | 0xfff92000 | 0x1000 [#915 , #915 ] | 0x7 | 0x0000000101fbc000 | 0xfff93000 | 0x1000 [#916 , #916 ] | 0x7 | 0x0000000101fbb000 | 0xfff94000 | 0x1000 [#921 , #921 ] | 0x7 | 0x00000000fcc02000 | 0xfff99000 | 0x1000 [#922 , #922 ] | 0x7 | 0x0000000101fb7000 | 0xfff9a000 | 0x1000 [#923 , #923 ] | 0x7 | 0x0000000101fb5000 | 0xfff9b000 | 0x1000 [#948 , #948 ] | 0x7 | 0x0000000101fb2000 | 0xfffb4000 | 0x1000 [#949 , #949 ] | 0x7 | 0x0000000101fb1000 | 0xfffb5000 | 0x1000 [#950 , #950 ] | 0x7 | 0x0000000101faf000 | 0xfffb6000 | 0x1000 [#951 , #951 ] | 0x7 | 0x0000000101fae000 | 0xfffb7000 | 0x1000 [#952 , #952 ] | 0x7 | 0x000000010263d000 | 0xfffb8000 | 0x1000 [#953 , #953 ] | 0x7 | 0x000000010263c000 | 0xfffb9000 | 0x1000 [#954 , #954 ] | 0x7 | 0x000000010263b000 | 0xfffba000 | 0x1000 [#955 , #955 ] | 0x7 | 0x000000010263a000 | 0xfffbb000 | 0x1000 [#956 , #956 ] | 0x7 | 0x0000000102639000 | 0xfffbc000 | 0x1000 [#957 , #957 ] | 0x7 | 0x0000000102638000 | 0xfffbd000 | 0x1000 [#958 , #958 ] | 0x7 | 0x0000000102637000 | 0xfffbe000 | 0x1000 [#959 , #959 ] | 0x7 | 0x0000000102636000 | 0xfffbf000 | 0x1000 [#960 , #992 ] | 0x7 | 0x0000000102613000 | 0xfffc0000 | 0x21000 } } Total PDEs: 1, total PTEs: 52 Note that the example above was output after I locally enabled IOMMU_DOMAIN_DMA, which is not merged to mainline yet due to a known framebuffer issue. Signed-off-by: Nicolin Chen --- drivers/iommu/tegra-smmu.c | 185 +++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 454504aa6602..cbd1a52f2a9f 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -47,6 +47,7 @@ struct tegra_smmu { struct list_head list; struct dentry *debugfs; + struct dentry *debugfs_mappings; struct iommu_device iommu; /* IOMMU Core code handle */ }; @@ -154,6 +155,9 @@ static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ SMMU_PDE_NONSECURE) +#define SMMU_PTE_ATTR (SMMU_PTE_READABLE | SMMU_PTE_WRITABLE | \ + SMMU_PTE_NONSECURE) +#define SMMU_PTE_ATTR_SHIFT 29 static unsigned int iova_pd_index(unsigned long iova) { @@ -165,6 +169,12 @@ static unsigned int iova_pt_index(unsigned long iova) return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); } +static unsigned long pd_pt_index_iova(unsigned int pd_index, unsigned int pt_index) +{ + return (pd_index & (SMMU_NUM_PDE - 1)) << SMMU_PDE_SHIFT | + (pt_index & (SMMU_NUM_PTE - 1)) << SMMU_PTE_SHIFT; +} + static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) { addr >>= 12; @@ -498,6 +508,156 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, mutex_unlock(&smmu->lock); } +static int tegra_smmu_debugfs_mappings_show(struct seq_file *s, void *data) +{ + struct tegra_smmu_group *group = s->private; + const struct tegra_smmu_group_soc *soc; + const struct tegra_smmu_swgroup *swgrp; + struct tegra_smmu_as *as; + struct tegra_smmu *smmu; + unsigned int pd_index; + unsigned int pt_index; + unsigned long flags; + u64 pte_count = 0; + u32 pde_count = 0; + u32 *pd, val; + + if (!group || !group->as || !group->swgrp) + return 0; + + swgrp = group->swgrp; + smmu = group->smmu; + soc = group->soc; + as = group->as; + + mutex_lock(&smmu->lock); + + val = smmu_readl(smmu, swgrp->reg); + if (!(val & SMMU_ASID_ENABLE)) + goto unlock; + + pd = page_address(as->pd); + if (!pd) + goto unlock; + + seq_puts(s, "[SWGROUP: "); + /* List all the swgroup names in the same group_soc */ + if (soc) { + bool first_swgroup = true; + unsigned int i; + + for (i = 0; i < soc->num_swgroups; i++) { + swgrp = tegra_smmu_find_swgrp(smmu, soc->swgroups[i]); + if (WARN_ON(!swgrp)) + goto unlock; + + val = smmu_readl(smmu, swgrp->reg); + if (!(val & SMMU_ASID_ENABLE)) + continue; + + if (WARN_ON((val & SMMU_ASID_MASK) != as->id)) + continue; + + if (first_swgroup) + first_swgroup = false; + else + seq_puts(s, ", "); + + seq_printf(s, "%s", swgrp->name); + } + } else { + WARN_ON((val & SMMU_ASID_MASK) != as->id); + seq_printf(s, "%s", swgrp->name); + } + seq_puts(s, "] "); + + seq_printf(s, "[as: (id: %d), ", as->id); + seq_printf(s, "(attr: %c|%c|%c), ", + as->attr & SMMU_PD_READABLE ? 'R' : '-', + as->attr & SMMU_PD_WRITABLE ? 'W' : '-', + as->attr & SMMU_PD_NONSECURE ? '-' : 'S'); + seq_printf(s, "(pd_dma: %pad)]\n", &as->pd_dma); + seq_puts(s, "{\n"); + + spin_lock_irqsave(&as->lock, flags); + + for (pd_index = 0; pd_index < SMMU_NUM_PDE; pd_index++) { + struct page *pt_page; + unsigned int i; + u32 *addr; + + /* An empty PDE should not have a pte use count */ + WARN_ON_ONCE(!pd[pd_index] ^ !as->count[pd_index]); + + /* Skip this empty PDE */ + if (!pd[pd_index]) + continue; + + pde_count++; + pte_count += as->count[pd_index]; + seq_printf(s, "\t[index: %u] 0x%x (count: %d)\n", + pd_index, pd[pd_index], as->count[pd_index]); + pt_page = as->pts[pd_index]; + addr = page_address(pt_page); + + seq_puts(s, "\t{\n"); + seq_printf(s, "\t\t%-14s | %-4s | %-10s%s | %-10s | %-11s\n", + "PTE RANGE", "ATTR", + "PHYS", sizeof(phys_addr_t) > 4 ? " " : "", + "IOVA", "SIZE"); + for (pt_index = 0; pt_index < SMMU_NUM_PTE; pt_index += i) { + size_t size = SMMU_SIZE_PT; + dma_addr_t iova; + phys_addr_t pa; + + i = 1; + + if (!addr[pt_index]) + continue; + + iova = pd_pt_index_iova(pd_index, pt_index); + pa = SMMU_PFN_PHYS(addr[pt_index] & ~SMMU_PTE_ATTR); + + /* Check contiguous mappings and increase size */ + while (pt_index + i < SMMU_NUM_PTE) { + dma_addr_t next_iova; + phys_addr_t next_pa; + + if (!addr[pt_index + i]) + break; + + next_iova = pd_pt_index_iova(pd_index, pt_index + i); + next_pa = SMMU_PFN_PHYS(addr[pt_index + i] & ~SMMU_PTE_ATTR); + + /* Break at the end of a linear mapping */ + if ((next_iova - iova != SMMU_SIZE_PT * i) || + (next_pa - pa != SMMU_SIZE_PT * i)) + break; + + i++; + } + + seq_printf(s, "\t\t[#%-4u, #%-4u] | 0x%-2x | %pa | 0x%-8x | 0x%-9zx\n", + pt_index, pt_index + i - 1, + addr[pt_index] >> SMMU_PTE_ATTR_SHIFT, + &pa, (u32)iova, size * i); + } + seq_puts(s, "\t}\n"); + } + + spin_unlock_irqrestore(&as->lock, flags); + + seq_puts(s, "}\n"); + seq_printf(s, "Total PDEs: %u, total PTEs: %llu\n ", pde_count, pte_count); + +unlock: + mutex_unlock(&smmu->lock); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(tegra_smmu_debugfs_mappings); + static void tegra_smmu_attach_as(struct tegra_smmu *smmu, struct tegra_smmu_as *as, unsigned int swgroup) @@ -522,6 +682,20 @@ static void tegra_smmu_attach_as(struct tegra_smmu *smmu, dev_warn(smmu->dev, "overwriting group->as for swgroup: %s\n", swgrp->name); group->as = as; + + if (smmu->debugfs_mappings) { + const char *name; + + if (group->soc) + name = group->soc->name; + else + name = group->swgrp->name; + + debugfs_create_file(name, 0444, + smmu->debugfs_mappings, group, + &tegra_smmu_debugfs_mappings_fops); + } + break; } @@ -545,6 +719,15 @@ static void tegra_smmu_detach_as(struct tegra_smmu *smmu, if (group->swgrp != swgrp) continue; group->as = NULL; + + if (smmu->debugfs_mappings) { + struct dentry *d; + + d = debugfs_lookup(group->swgrp->name, + smmu->debugfs_mappings); + debugfs_remove(d); + } + break; } @@ -1137,6 +1320,8 @@ static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) &tegra_smmu_swgroups_fops); debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, &tegra_smmu_clients_fops); + + smmu->debugfs_mappings = debugfs_create_dir("mappings", smmu->debugfs); } static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu)