From patchwork Fri Nov 26 10:42:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560026 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=db0BMoOr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rvw0qwnz9t54 for ; Fri, 26 Nov 2021 21:44:12 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3DA9983776; Fri, 26 Nov 2021 11:44:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="db0BMoOr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 84B4483799; Fri, 26 Nov 2021 11:43:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 13BA583744 for ; Fri, 26 Nov 2021 11:43:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 6C7A360F12; Fri, 26 Nov 2021 10:43:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923419; bh=sXmgxgHo95TX6JUsd+5kA1+eOXiGKf3R282Vww3l8oc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=db0BMoOr9UraydZmAXUZEROxqsHLLe6NQh8/rr961o2Hb+rxZa/iKpuA7Cf90SyX2 Jyp/3ZDrc/B0DJ/1OHRsAFXC7rWZy4mWO/cLdTT+PeAogoxqlQlVGyTxXMeRQ3X4nt pFDmRL5fS6DpS5ws5hbePYUdwXfs6jCtdlxhqQngd2VwxdYaVqNovQuS6ABo4Ht547 A8Sqb14DcPmDgvzBUClo2DC8MQ9lNZPAo0f76ks1cmWZmH6nf9Q7d/J9PkSy/i6OJ3 4XxPbferDV5Z/b3xzuTZ8rz/7Cc+sOzZzQROv60JIzDQlPKO4O8v6qmSfhQvLwyK6Y XaGy9EiyfhFjQ== Received: by pali.im (Postfix) id A4E2CEF1; Fri, 26 Nov 2021 11:43:37 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Daniel Schwierzeck , Heiko Schocher , Marek Vasut , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Huan Wang , Angelo Dureghello Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 01/12] pci: Add standard PCI Config Address macros Date: Fri, 26 Nov 2021 11:42:41 +0100 Message-Id: <20211126104252.5443-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Lot of PCI and PCIe controllers are using standard Config Address for PCI Configuration Mechanism #1 or its extended version. So add PCI_CONF1_ADDRESS() and PCI_CONF1_EXT_ADDRESS() macros into U-Boot's pci.h header file which can be suitable for most PCI and PCIe controller drivers. Drivers do not have to invent their own macros and can use these new U-Boot macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- include/pci.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/include/pci.h b/include/pci.h index 6c1094d72998..0ea41a7e1ba2 100644 --- a/include/pci.h +++ b/include/pci.h @@ -522,6 +522,51 @@ #include +/* + * Config Address for PCI Configuration Mechanism #1 + * + * See PCI Local Bus Specification, Revision 3.0, + * Section 3.2.2.3.2, Figure 3-2, p. 50. + */ + +#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ +#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ +#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ + +#define PCI_CONF1_BUS_MASK 0xff +#define PCI_CONF1_DEV_MASK 0x1f +#define PCI_CONF1_FUNC_MASK 0x7 +#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ + +#define PCI_CONF1_ENABLE BIT(31) +#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) +#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) +#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) +#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) + +#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ENABLE | \ + PCI_CONF1_BUS(bus) | \ + PCI_CONF1_DEV(dev) | \ + PCI_CONF1_FUNC(func) | \ + PCI_CONF1_REG(reg)) + +/* + * Extension of PCI Config Address for accessing extended PCIe registers + * + * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs + * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address + * are used for specifying additional 4 high bits of PCI Express register. + */ + +#define PCI_CONF1_EXT_REG_SHIFT 16 +#define PCI_CONF1_EXT_REG_MASK 0xf00 +#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) + +#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ + (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ + PCI_CONF1_EXT_REG(reg)) + /* * Enhanced Configuration Access Mechanism (ECAM) * From patchwork Fri Nov 26 10:42:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560029 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=AimgS1MU; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rwq1Ym1z9t54 for ; Fri, 26 Nov 2021 21:44:59 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2362A83173; Fri, 26 Nov 2021 11:44:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="AimgS1MU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F0CF683768; Fri, 26 Nov 2021 11:43:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 23C3583762 for ; Fri, 26 Nov 2021 11:43:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 913BB60F6B; Fri, 26 Nov 2021 10:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923420; bh=kKlw0IgBa5T3L3OxyBxoFTVAmgXnbUQH/qr2EWqtSec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AimgS1MU2vRXU0qXiGcHQf7oL0fSINYVejZRSoFwiEfoyptMDRqjWptYMBQLpwdGH GVKBxUKNweWmNWiU/PgiSprXO1y0WY5npo9FjZ9if815HZRCmr5qqCpYcECRdOoSzx pydf0T6q6PECWjF/mjWs0r3Pc7JjnPI67uV28ycjH7RyuPVzPUD2iPM/Qw7A9X90/0 OtbHgxd7SXJ2ua6mPFa08rSCuGlbfVErKVuZ9M6fw6fgxsOzHhL6tfZveB1OCn8dqa 9MZkutAGt2T6Ovhns0tj6wM5gRBC8jah1Hh00G4oRHGwuRstFhktOkX4Vqv2dUoy6b SC1zJZx/F3+6w== Received: by pali.im (Postfix) id B27F0EF6; Fri, 26 Nov 2021 11:43:38 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Daniel Schwierzeck Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 02/12] pci: gt64120: Use PCI_CONF1_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:42 +0100 Message-Id: <20211126104252.5443-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI gt64120 driver uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS() and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_gt64120.c | 7 ++----- include/gt64120.h | 12 ------------ 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c index 153c65b119a4..2c2a80eeaa06 100644 --- a/drivers/pci/pci_gt64120.c +++ b/drivers/pci/pci_gt64120.c @@ -48,7 +48,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt, { unsigned int bus = PCI_BUS(bdf); unsigned int dev = PCI_DEV(bdf); - unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + unsigned int func = PCI_FUNC(bdf); u32 intr; u32 addr; u32 val; @@ -65,10 +65,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt, /* Clear cause register bits */ writel(~GT_INTRCAUSE_ABORT_BITS, >->regs->intrcause); - addr = GT_PCI0_CFGADDR_CONFIGEN_BIT; - addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF; - addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF; - addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF; + addr = PCI_CONF1_ADDRESS(bus, dev, func, where); /* Setup address */ writel(addr, >->regs->pci0_cfgaddr); diff --git a/include/gt64120.h b/include/gt64120.h index 0b577f3f44b9..b58afe3c4afe 100644 --- a/include/gt64120.h +++ b/include/gt64120.h @@ -491,18 +491,6 @@ #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - #define GT_PCI0_CMD_MBYTESWAP_SHF 0 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK From patchwork Fri Nov 26 10:42:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560027 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=YBt8rEit; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rwB4fL8z9t54 for ; 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Fri, 26 Nov 2021 11:43:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 1F85360ED3; Fri, 26 Nov 2021 10:43:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923420; bh=g5VISYc4K+SkLGRUS/dWZaZ6W9IVEofYLdOTsLCOHcs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YBt8rEit8W9StE8+ePG01neXIOxGcCM/bbTCQchkMHwnHXJ1ZV0fGwztq2rePa5zx QIceomCGge4xdfi3CU1r7dwh/zPmpzhgzzUWR1JEPvh48Py6kaCkrXB0Z3q8CAZuH+ u7Yn1kwh/jfoOFIzK+nhmO4VC/7jvR73pZUHChXoqnCvmVJ3/tSgv9ywDHSvub6Wwa rX7CJKYBr1NrQAZDibaRQ/SHND0wr/vv+3HOWiH3xIofEot2k8sRXB4BhwXbyDlYsn 4ThxdzLMNPN5uKuFUBjCpvbSELnRFQ0OYhWdPlDhwrb+RivFKoEIeWPCZiqU98TUCF ScnAMQnOge4xQ== Received: by pali.im (Postfix) id D52F15B2; Fri, 26 Nov 2021 11:43:39 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Heiko Schocher Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 03/12] pci: mpc85xx: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:43 +0100 Message-Id: <20211126104252.5443-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI mpc85xx driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_mpc85xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 574cb784a893..1e180ee289b0 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -23,7 +23,7 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size); @@ -38,7 +38,7 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, struct mpc85xx_pci_priv *priv = dev_get_priv(dev); u32 addr; - addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size)); From patchwork Fri Nov 26 10:42:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560028 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=q08ZPFgw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rwW0dyRz9t54 for ; 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Fri, 26 Nov 2021 11:43:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 1E77F61108; Fri, 26 Nov 2021 10:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923421; bh=Kmg6B+7m/H+YE8dP2THVIooKvJKsy126d+CKWaBc224=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q08ZPFgwuIIEdDEsSAT3nxC96PLNlR/A4L1K03yps8PIlJD/w73Q1rByharJzELOs 3BMYsROjTbnFUT0hCkD5voQW3KIgbRB0adH4mz5/16zrpAV4s4VVWxT8sFAYEHe2JK jmsLcxJ3J0znn40Rb3w0WGMJqkMdn4rjc4IW5Ee3qEdcmtdsTLQEpktb+u0xmoyJXp FCorR7FTRQx4bB+93hjPulG35cYuHsVYatsdD1PR1TUeDFhav3fWF02+ekVpSe/omn CHG5bP/tewvavgavYjEysx49rLPepOgi67+T+77T2yOV0g4pY8vPrPAakRrgWLNvDT nIp2Zp2KFzSNw== Received: by pali.im (Postfix) id D6D8E5B2; Fri, 26 Nov 2021 11:43:40 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Daniel Schwierzeck Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 04/12] pci: msc01: Use PCI_CONF1_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:44 +0100 Message-Id: <20211126104252.5443-5-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI msc01 driver uses standard format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_msc01.c | 7 ++----- include/msc01.h | 9 --------- 2 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c index 2f1b688fc321..8d363d60498b 100644 --- a/drivers/pci/pci_msc01.c +++ b/drivers/pci/pci_msc01.c @@ -34,16 +34,13 @@ static int msc01_config_access(struct msc01_pci_controller *msc01, void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS; unsigned int bus = PCI_BUS(bdf); unsigned int dev = PCI_DEV(bdf); - unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + unsigned int func = PCI_FUNC(bdf); /* clear abort status */ __raw_writel(aborts, intstat); /* setup address */ - __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | - (dev << MSC01_PCI_CFGADDR_DNUM_SHF) | - (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) | - ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), + __raw_writel((PCI_CONF1_ADDRESS(bus, dev, func, where) & ~PCI_CONF1_ENABLE), msc01->base + MSC01_PCI_CFGADDR_OFS); /* perform access */ diff --git a/include/msc01.h b/include/msc01.h index ec18a724eb93..20158123494a 100644 --- a/include/msc01.h +++ b/include/msc01.h @@ -71,15 +71,6 @@ #define MSC01_PCI_INTSTAT_MA_SHF 7 #define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) -#define MSC01_PCI_CFGADDR_BNUM_SHF 16 -#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) -#define MSC01_PCI_CFGADDR_DNUM_SHF 11 -#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) -#define MSC01_PCI_CFGADDR_FNUM_SHF 8 -#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) -#define MSC01_PCI_CFGADDR_RNUM_SHF 2 -#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) - #define MSC01_PCI_HEAD0_VENDORID_SHF 0 #define MSC01_PCI_HEAD0_DEVICEID_SHF 16 From patchwork Fri Nov 26 10:42:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560030 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=tw7uhkjl; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rx06V16z9t54 for ; Fri, 26 Nov 2021 21:45:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1CF7E83773; Fri, 26 Nov 2021 11:44:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; 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Fri, 26 Nov 2021 10:43:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923422; bh=FeCT/StserbE06co3BtaNeOsZqi3gCsIjaso5PHQabM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tw7uhkjlR4bCkC9BN20fFpcvrFZJAYUf9ybLrdGJ+HlQ9r64pQDVrYK7x2Rahg+cl P+f4LcO81wMDb6Uj3JO67cjqrB/Rvtybvji7Tr88AL7TJprbA+QdtQR+0/ToYFJ1Xi rpVJQPyZzM7z6DvxsADuTkhS4Nzh8E6LPBOeSk7aa5F1qcwmXN/9A6JiXPiihGYscv KeloR4hA2ykwrkRmG02k4Pg1T2MHpdTf+T/Dl4J/5M3C/rjBTjLWNikjtn7wyc5nt2 zXp9fVrDjI15mjkrSvGpVR6Wf5hHkDn4iKKZ7ycKPP1wS/A9WKnE1Xo8GB4hkrRXuM Q9nAQKXwdJkPA== Received: by pali.im (Postfix) id E24EC5B2; Fri, 26 Nov 2021 11:43:41 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 05/12] pci: mvebu: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:45 +0100 Message-Id: <20211126104252.5443-6-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI mvebu driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_mvebu.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 14cd82db6ff8..aa0d6bd5162c 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -48,15 +48,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN BIT(31) -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) -#define PCIE_CONF_ADDR(b, d, f, reg) \ - (PCIE_CONF_BUS(b) | PCIE_CONF_DEV(d) | \ - PCIE_CONF_FUNC(f) | PCIE_CONF_REG(reg) | \ - PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_MASK_OFF 0x1910 #define PCIE_MASK_ENABLE_INTS (0xf << 24) @@ -188,9 +179,9 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, * secondary bus with device number 1. */ if (busno == pcie->first_busno) - addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset); + addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else - addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); + addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); /* write address */ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF); @@ -286,9 +277,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, * secondary bus with device number 1. */ if (busno == pcie->first_busno) - addr = PCIE_CONF_ADDR(pcie->sec_busno, 1, 0, offset); + addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); else - addr = PCIE_CONF_ADDR(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); + addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); /* write address */ writel(addr, pcie->base + PCIE_CONF_ADDR_OFF); From patchwork Fri Nov 26 10:42:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560032 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=ZKOoXWOz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rxS1k6zz9t54 for ; Fri, 26 Nov 2021 21:45:32 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1696C83777; Fri, 26 Nov 2021 11:44:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; 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Fri, 26 Nov 2021 10:43:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923423; bh=slPoCbI3tMG4qZqoM323Dn/X82/Ep1JHwrPXQQNLA4I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZKOoXWOzdpJJqhQKbOLWDNEu8LlRt63jQnm+HkkuwaFs1Ap6OvkcMRkPN+8cH/Tf6 kVDRUc0ZzaLiMigNzRIVSKska8V+G02Bkq+P9HWydtMFjbhi94XHKTu4+VftLDDOOA P7grqi2cra7BeFIxncYCgpqfk2xthogm71OtWonuyeXMraYc2kOLQuJIWscMKugk+B Wwivh2BiUqutJhe+LTbU6qYveaOdUYTD7WQO4QdlgYBPIww9FDVyfXhaMGUE7iyJbw 8tl7ygsy64TJWHI18Rds1MczCftkdGX8+DHMjnFnsLiF7ozI1TQJ5A0NY/w105nvkP JVtxqXuvR7NHw== Received: by pali.im (Postfix) id E2F725B2; Fri, 26 Nov 2021 11:43:42 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 06/12] pci: tegra: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:46 +0100 Message-Id: <20211126104252.5443-7-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI tegra driver uses extended format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address function. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_tegra.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 9cb4414836f8..fc05ee00f1fc 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -275,13 +275,6 @@ static void rp_writel(struct tegra_pcie_port *port, unsigned long value, writel(value, port->regs.start + offset); } -static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where) -{ - return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) | - (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) | - (where & 0xfc); -} - static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, int where, unsigned long *address) { @@ -305,7 +298,9 @@ static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, return -EFAULT; #endif - *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); + *address = pcie->cs.start + + (PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf), where) & ~PCI_CONF1_ENABLE); return 0; } } From patchwork Fri Nov 26 10:42:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560031 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=sQ5UusSh; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rxC3MMwz9t54 for ; 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Fri, 26 Nov 2021 11:43:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 2A884601FF; Fri, 26 Nov 2021 10:43:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923424; bh=DhqDhSEAtAktGbfUyfQPHcr3Zjv1hnGnj2xmu+v3P+I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sQ5UusShxqCODAXnycGWGMlh8KvABEWl8joLkLHGQk549x/fZWAF7Z/fKQvtgHZvO IaUyx5kRXW4TdJw9RJfU0Uu/Wl2+MsCsPawrIb0CBSIKx/x23Nsi3PyKRsbUcN3Yb7 E/Zd1l8Yrn2F7bKmX8Cf2jhObP1ud78W1/PlqCkm+g6C2FHYwKiYxC3ON8QH/m1kjU mWUdN95WgaaZmO3Vjo2kczWrtS4om2ahNZDnxn3gkZL0HLIxj3Yy/LXds4f9r6LA0l q7Q5HCXbElCQuEsPoxN8d9gMxvokUfSkSxe1I/bDG3/R3iU8IMS29mLyuDUKJ8RNG5 OX2CLbkdSBu/A== Received: by pali.im (Postfix) id E1F325B2; Fri, 26 Nov 2021 11:43:43 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 07/12] pci: fsl: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:47 +0100 Message-Id: <20211126104252.5443-8-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI fsl driver uses extended format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pcie_fsl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 3c2a2a476111..cc6efdd5b464 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -58,8 +58,9 @@ static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0); - val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), + PCI_DEV(bdf), PCI_FUNC(bdf), + offset); out_be32(®s->cfg_addr, val); sync(); @@ -94,8 +95,9 @@ static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, if (fsl_pcie_addr_valid(pcie, bdf)) return 0; - bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0); - val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus), + PCI_DEV(bdf), PCI_FUNC(bdf), + offset); out_be32(®s->cfg_addr, val); sync(); From patchwork Fri Nov 26 10:42:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560034 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=LwI7MBab; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rxv0S2Cz9t54 for ; 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Fri, 26 Nov 2021 11:43:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 32145601FF; Fri, 26 Nov 2021 10:43:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923425; bh=nJxZby4mqF/bY0UBq/5uGCvzV0IQ/meXFEMVW8gYecc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LwI7MBabEE1z6FPfJ58cU/1kx3aGHflxf2XT8t0PmQI6ivR3A3tPCcM5/hQm+Z6Cd h3Iaq5sP1f7o1zzXI6F+iB3C3/gdVHVo1x9YoQ9bB/Z4mJWeb/ibGgQnPX64dwGfrV uasE08l2VSKBqVB8bmE/FgcxbbWJEOyNltw7IErWoBHV75SFynqmjYKoJ2OLxoX3BB qjxmBVK7lpjpiqrhq381Q9zf6js9e5QAIqBd1UWeLqlxm8/W2Y1SZY4WeKydWSNcCM DfQsS3lKKT++0O5Tg1hNWrnxKw7lE5TrIbL4oDUNa/PpeEGC2Lkevw9uoOGYTr2PFc dBy6sS6EYc8oQ== Received: by pali.im (Postfix) id E8E745B2; Fri, 26 Nov 2021 11:43:44 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 08/12] pci: mediatek: Use PCI_CONF1_EXT_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:48 +0100 Message-Id: <20211126104252.5443-9-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI mediatek driver uses extended format of Config Address for PCI Configuration Mechanism #1 but with cleared Enable bit. So use new U-Boot macro PCI_CONF1_EXT_ADDRESS() with clearing PCI_CONF1_ENABLE bit and remove old custom driver address macros. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pcie_mediatek.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c index f5556713878f..051a3bc96935 100644 --- a/drivers/pci/pcie_mediatek.c +++ b/drivers/pci/pcie_mediatek.c @@ -41,10 +41,6 @@ #define PCIE_BAR_ENABLE BIT(0) #define PCIE_REVISION_ID BIT(0) #define PCIE_CLASS_CODE (0x60400 << 8) -#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ - ((((regn) >> 8) & GENMASK(3, 0)) << 24)) -#define PCIE_CONF_ADDR(regn, bdf) \ - (PCIE_CONF_REG(regn) | (bdf)) /* MediaTek specific configuration registers */ #define PCIE_FTS_NUM 0x70c @@ -147,8 +143,11 @@ static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { struct mtk_pcie *pcie = dev_get_priv(udev); + u32 val; - writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), + PCI_FUNC(bdf), offset) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); return 0; @@ -330,7 +329,6 @@ static void mtk_pcie_port_free(struct mtk_pcie_port *port) static int mtk_pcie_startup_port(struct mtk_pcie_port *port) { struct mtk_pcie *pcie = port->pcie; - u32 slot = PCI_DEV(port->slot << 11); u32 val; int err; @@ -357,13 +355,14 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); /* configure FC credit */ - writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), - pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FC_CREDIT) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK, PCIE_FC_CREDIT_VAL(0x806c)); /* configure RC FTS number to 250 when it leaves L0s */ - writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + val = PCI_CONF1_EXT_ADDRESS(0, port->slot, 0, PCIE_FTS_NUM) & ~PCI_CONF1_ENABLE; + writel(val, pcie->base + PCIE_CFG_ADDR); clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK, PCIE_FTS_NUM_L0(0x50)); From patchwork Fri Nov 26 10:42:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560033 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=jS+RYx8n; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0rxg2lgBz9t54 for ; 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Fri, 26 Nov 2021 11:43:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 4486260F12; Fri, 26 Nov 2021 10:43:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923426; bh=O/x2LZnh5jzoCPy9kpjreqvP3oB4lc4XiXvILzA8wG8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jS+RYx8nwkzhSNotzOKr/6dis1q+SpT+TrGE7ZaGgFjTl1RuIoR9Ao+z5jClGbbDi S/PEfIoQL0ppWadQuCruDTklJvx2Kh2ynAwhSqv/JoY9Ly/MtCep1+/wqGmOWToVwZ HtF0aCiPvKJzjk6l+aITcMtlbOxezIjxzWzidqv5bCyoWA//LyR0lmPCMbLxHgcACt PArrcJ4qBFlpKcaT/+4DBf+2wo3K6xCtHYDvpBU0tiwWpXTaOJZsZOsJrQ3FZ9PNE3 caa1L5xhGwFYUF/vzi96K0OjQ9lQlQ/FzQtJYUz+pkqQ6y5p0qyI+u0x9S8T2pcefi zswE6Z4EMueJg== Received: by pali.im (Postfix) id 07A1D5B2; Fri, 26 Nov 2021 11:43:46 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 09/12] pci: sh7780: Use PCI_CONF1_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:49 +0100 Message-Id: <20211126104252.5443-10-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean PCI sh7780 driver uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/pci/pci_sh7780.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c index 06d711a6cb9e..7533286c0156 100644 --- a/drivers/pci/pci_sh7780.c +++ b/drivers/pci/pci_sh7780.c @@ -34,9 +34,9 @@ int pci_sh4_read_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 *value) { - u32 par_data = 0x80000000 | dev; + u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); + p4_out(par_data, SH7780_PCIPAR); *value = p4_in(SH7780_PCIPDR); return 0; @@ -45,9 +45,9 @@ int pci_sh4_read_config_dword(struct pci_controller *hose, int pci_sh4_write_config_dword(struct pci_controller *hose, pci_dev_t dev, int offset, u32 value) { - u32 par_data = 0x80000000 | dev; + u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR); + p4_out(par_data, SH7780_PCIPAR); p4_out(value, SH7780_PCIPDR); return 0; } From patchwork Fri Nov 26 10:42:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560035 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=oqSpDkFX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0ry73YZqz9t54 for ; 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So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- arch/x86/cpu/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index d4f9290ca73b..8a992ed82339 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -20,7 +20,7 @@ int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { - outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); switch (size) { case PCI_SIZE_8: *valuep = inb(PCI_REG_DATA + (offset & 3)); @@ -39,7 +39,7 @@ int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { - outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); switch (size) { case PCI_SIZE_8: outb(value, PCI_REG_DATA + (offset & 3)); From patchwork Fri Nov 26 10:42:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560036 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=lzAi4mNP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0ryL60SVz9t54 for ; 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Fri, 26 Nov 2021 11:43:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 73C6B61041; Fri, 26 Nov 2021 10:43:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923428; bh=x+oqKHUZ/4/NbXqaZi7CnDukEkp+bNcXQSX1pun//mY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lzAi4mNPG+bm6io/PFJzIlFkPObGNH9T/+mfjMuh6VOXx2nJWtN331tW/7wc//Ez3 T+SkIJCj/gTuI7jd5HLBANcn++TYYn2T5hl4OOzjlxzYxgk2Dh29m+j+3NSOZSNJQ6 lFsVJbwlxx2RGXw3hZx1AI8/Vbkhl8jj4OGXQ2EFznmpQ6BDggjHWtVDAPwjvO48ba UHPb4La0ch7ReVe7nx4z+LtDq7U3hOAkkA3CFTzkrZyaiQZEvuw0kUO29U3GzjR9rt sHRuvURUd5r7THsfahrdyvTaKx0vTEdy7/KmbpH9h65LXA99NZVsAiD1TBSNupldXY gz5Jy8IQg29IQ== Received: by pali.im (Postfix) id 36BA95B2; Fri, 26 Nov 2021 11:43:48 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Huan Wang , Angelo Dureghello Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 11/12] m68k: mcf5445x: pci: Use PCI_CONF1_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:51 +0100 Message-Id: <20211126104252.5443-12-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean mcf5445x platform uses standard format of Config Address for PCI Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS(). Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- arch/m68k/cpu/mcf5445x/pci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c index af02c4934c97..d487468d0bfa 100644 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ b/arch/m68k/cpu/mcf5445x/pci.c @@ -26,12 +26,11 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, type val) \ { \ - u32 addr = 0; \ - u16 cfg_type = 0; \ - addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + u32 addr = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), \ + PCI_FUNC(dev), offset); \ out_be32(hose->cfg_addr, addr); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ - out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + out_be32(hose->cfg_addr, addr & ~PCI_CONF1_ENABLE); \ return 0; \ } From patchwork Fri Nov 26 10:42:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1560037 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=HGqXjFvW; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J0ryZ2htGz9t54 for ; Fri, 26 Nov 2021 21:46:30 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7CCE683742; Fri, 26 Nov 2021 11:45:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="HGqXjFvW"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 054AB837AC; Fri, 26 Nov 2021 11:45:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 18A0883791 for ; Fri, 26 Nov 2021 11:43:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: by mail.kernel.org (Postfix) with ESMTPSA id 93371601FF; Fri, 26 Nov 2021 10:43:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1637923429; bh=74eWCgN5T4Yl3fKoWewg3psvvemyA9QXqrP3VzGK3Rs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HGqXjFvW7Pg83Kni7R0af/Z8jLYrN1kBnAEpp7NQxfTjAAwd36P0U5S40Sf9/t3au cJJhSR4xcKK/lRg64eNDNCc5SGwnNNEst93Qh/KXeV+I6aPZAuVJheoujqsznoni6X Ut/6t3LPMbdeuEsFYwU4lOmFU93iZK/rK3qQNDt8Uv0xz3Ssg8XirN03XcYJ1MQNMQ /W6whFouttJxA2BsD39FJEit+BCMH6W9umAzlccSPPCn3E1WyvN1cHLkH4ocQIyxRu nzMTwx7LZ/bG0R2SDin3d84o9cOBxO6UwkLnaMpwwwcuaY9fAUosdXJ04bN7LJiBdN iHltge8gT+dmA== Received: by pali.im (Postfix) id 552385B2; Fri, 26 Nov 2021 11:43:49 +0100 (CET) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Stefan Roese , Simon Glass , Bin Meng , Marek Vasut Cc: u-boot@lists.denx.de Subject: [PATCH u-boot-next 12/12] pci: sh7751: Fix access to config space via PCI_CONF1_ADDRESS() macro Date: Fri, 26 Nov 2021 11:42:52 +0100 Message-Id: <20211126104252.5443-13-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211126104252.5443-1-pali@kernel.org> References: <20211126104252.5443-1-pali@kernel.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean sh7751 platform uses standard format of Config Address for PCI Configuration Mechanism #1. Commit 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") which did conversion of PCI sh7751 driver to DM, broke access to config space as that commit somehow swapped device and function bits in config address. Fix all these issues by using new U-Boot macro PCI_CONF1_ADDRESS() which calculates Config Address correctly. Also remove nonsense function sh7751_pci_addr_valid() which was introduced in commit 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") probably due to workarounded issues with mixing/swapping device and function bits of config address which probably resulted in non-working access to some devices. With correct composing of config address there should not be such issue anymore. Signed-off-by: Pali Rohár Fixes: 72c2f4acd76f ("pci: sh7751: Convert to DM and DT probing") Cc: Marek Vasut Reviewed-by: Simon Glass --- drivers/pci/pci_sh7751.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index e110550c71c8..d514c040344c 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -74,33 +74,13 @@ #define p4_in(addr) (*addr) #define p4_out(data, addr) (*addr) = (data) -static int sh7751_pci_addr_valid(pci_dev_t d, uint offset) -{ - if (PCI_FUNC(d)) - return -EINVAL; - - return 0; -} - -static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset) -{ - return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3); -} - static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf, uint offset, ulong *value, enum pci_size_t size) { u32 addr, reg; - int ret; - ret = sh7751_pci_addr_valid(bdf, offset); - if (ret) { - *value = pci_get_ff(size); - return 0; - } - - addr = get_bus_address(dev, bdf, offset); + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); p4_out(addr, SH7751_PCIPAR); reg = p4_in(SH7751_PCIPDR); *value = pci_conv_32_to_size(reg, offset, size); @@ -113,13 +93,8 @@ static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf, enum pci_size_t size) { u32 addr, reg, old; - int ret; - - ret = sh7751_pci_addr_valid(bdf, offset); - if (ret) - return ret; - addr = get_bus_address(dev, bdf, offset); + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); p4_out(addr, SH7751_PCIPAR); old = p4_in(SH7751_PCIPDR); reg = pci_conv_size_to_32(old, value, offset, size);