From patchwork Wed Feb 7 15:14:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 870412 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-472757-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="GMWXU6HR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zc4f92V4sz9s1h for ; Thu, 8 Feb 2018 02:15:58 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=GaeOg s0KTc8NWkL1R3P1moMChDvSTPLXAiMXDuo0dAwczB8uP6nErrxWNzOcJKThMjEjO agUI+aBG10Iz3EIWUVIhRzEDMq41kzCPs5YkqqeK0svKnY+sIEv0hPLhd2DO49QJ wMO5deZKPGGhTeNHlwf6uIFR52uMymsnTd9I9E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:reply-to:to:cc:content-type:date:mime-version :content-transfer-encoding:message-id; s=default; bh=h7Xq9EDotcL RvIPySdihCwt0JuY=; b=GMWXU6HRUrUlOMsXn2Al735AeGCR00A+FzGEBLsHSIV jx/fbYXM7hEf2gaHNpNYIDBTnuOVeZ1jRM91jLL4Pf25EFvq4MMpN9TvrlfQD1lo tTkO+UouHmTnJGJMsXvf/R5abY0fIFfKcjI+bML+hSpahilRmPpv0Szk0f3ZOfJ8 = Received: (qmail 125505 invoked by alias); 7 Feb 2018 15:15:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 124506 invoked by uid 89); 7 Feb 2018 15:15:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Feb 2018 15:15:20 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w17FE1HN013450 for ; Wed, 7 Feb 2018 10:15:06 -0500 Received: from e13.ny.us.ibm.com (e13.ny.us.ibm.com [129.33.205.203]) by mx0a-001b2d01.pphosted.com with ESMTP id 2g03p30vq9-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 07 Feb 2018 10:15:05 -0500 Received: from localhost by e13.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 7 Feb 2018 10:15:02 -0500 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w17FF1Wi40894514; Wed, 7 Feb 2018 15:15:01 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 13BC0AE04B; Wed, 7 Feb 2018 10:16:20 -0500 (EST) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id B8943AE060; Wed, 7 Feb 2018 10:16:19 -0500 (EST) Subject: [PATCH, rs6000] PR84220 fix altivec_vec_sld and vec_sldw intrinsic definitions From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool , David Edelsohn , Bill Schmidt , Peter Bergner Date: Wed, 07 Feb 2018 09:14:59 -0600 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18020715-0008-0000-0000-000002CE041E X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008491; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000248; SDB=6.00986285; UDB=6.00500522; IPR=6.00765649; BA=6.00005819; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019424; XFM=3.00000015; UTC=2018-02-07 15:15:03 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020715-0009-0000-0000-0000382E2D18 Message-Id: <1518016499.11602.261.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-07_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802070192 X-IsSubscribed: yes Hi, Our VEC_SLD definitions were mistakenly allowing the third argument to be of an invalid type, triggering an ICE (on invalid code) later in the build process. This fixes those definitions. The nearby VEC_SLDW definitions have the same issue, those have been fixed as part of this patch too. Testcases have been added to ensure we generate the 'invalid intrinsic' message as is appropriate, instead of ICEing. Giving proper credit, this was found by Peter Bergner while working a different issue. :-) Sniff-tests passed on P8. Doing larger reg-test across power systems now. OK for trunk? And,.. do we want this one backported too? Thanks, -Will [gcc] 2018-02-07 Will Schmidt PR target/84220 * config/rs6000/rs6000-c.c: Update definitions for ALTIVEC_BUILTIN_VEC_SLD and ALTIVEC_BUILTIN_VEC_SLDW. [testsuite] 2018-02-07 Will Schmidt PR target/84220 * gcc.target/powerpc/pr84220-1.c: New test. * gcc.target/powerpc/pr84220-2.c: New test. * gcc.target/powerpc/pr84220-sldw.c: New test. diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index a68be51..26f9990 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -3654,39 +3654,39 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, @@ -4152,29 +4152,29 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { ~RS6000_BTI_unsigned_V16QI }, { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_NOT_OPAQUE }, + RS6000_BTI_INTSI }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-1.c b/gcc/testsuite/gcc.target/powerpc/pr84220-1.c new file mode 100644 index 0000000..f2454d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-1.c @@ -0,0 +1,95 @@ +/* PR target/84220 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +typedef vector bool char vbc_t; +typedef vector signed char vsc_t; +typedef vector unsigned char vuc_t; +typedef vector bool int vbi_t; +typedef vector signed int vsi_t; +typedef vector unsigned int vui_t; +typedef vector pixel vp_t; +typedef vector bool short vbs_t; +typedef vector signed short vss_t; +typedef vector unsigned short vus_t; +typedef vector float vf_t; + +void +test_vbc ( vbc_t v1, vbc_t v2, vbc_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vbi ( vbi_t v1, vbi_t v2, vbi_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vui ( vui_t v1, vui_t v2, vui_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vp ( vp_t v1, vp_t v2, vp_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vbs ( vbs_t v1, vbs_t v2, vbs_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vss ( vss_t v1, vss_t v2, vss_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vus ( vus_t v1, vus_t v2, vus_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vf ( vf_t v1, vf_t v2, vf_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-2.c b/gcc/testsuite/gcc.target/powerpc/pr84220-2.c new file mode 100644 index 0000000..1e8a965 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-2.c @@ -0,0 +1,40 @@ +/* PR target/84220 */ +/* Same as pr84220-1.c , with p8vector requirement for long long and double types. */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-maltivec -mpower8-vector" } */ + +#include + +typedef vector bool long long vbl_t; +typedef vector signed long long vsl_t; +typedef vector unsigned long long vul_t; +typedef vector double vd_t; + +void +test_vbl ( vbl_t v1, vbl_t v2, vbl_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vul ( vul_t v1, vul_t v2, vul_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} + +void +test_vd ( vd_t v1, vd_t v2, vd_t v3 ) \ +{ + __builtin_vec_sld(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + __builtin_vec_sld(v1, v2, 3); +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c new file mode 100644 index 0000000..0f50837 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sldw.c @@ -0,0 +1,78 @@ +/* PR target/84220 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +#include + +typedef vector bool char vbc_t; +typedef vector signed char vsc_t; +typedef vector unsigned char vuc_t; +typedef vector bool int vbi_t; +typedef vector signed int vsi_t; +typedef vector unsigned int vui_t; +typedef vector pixel vp_t; +typedef vector bool short vbs_t; +typedef vector signed short vss_t; +typedef vector unsigned short vus_t; +typedef vector float vf_t; +typedef vector bool long long vbl_t; +typedef vector signed long long vsl_t; +typedef vector unsigned long long vul_t; +typedef vector double vd_t; + +void +test_vsc ( vsc_t v1, vsc_t v2, vsc_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vuc ( vuc_t v1, vuc_t v2, vuc_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vsi ( vsi_t v1, vsi_t v2, vsi_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vui ( vui_t v1, vui_t v2, vui_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vsl ( vsl_t v1, vsl_t v2, vsl_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vul ( vul_t v1, vul_t v2, vul_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vss ( vss_t v1, vss_t v2, vss_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +} + +void +test_vus ( vus_t v1, vus_t v2, vus_t v3 ) \ +{ + vec_sldw(v1, v2, v3); /* { dg-error "invalid parameter combination for AltiVec intrinsic" } */ + vec_sldw(v1, v2, 3); +}