From patchwork Tue Sep 12 16:05:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 812946 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xs8yV6ng6z9s7g for ; Wed, 13 Sep 2017 02:14:58 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P4bFe7yo"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xs8yV5RLfzDrVm for ; Wed, 13 Sep 2017 02:14:58 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P4bFe7yo"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::22f; helo=mail-pf0-x22f.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P4bFe7yo"; dkim-atps=neutral Received: from mail-pf0-x22f.google.com (mail-pf0-x22f.google.com [IPv6:2607:f8b0:400e:c00::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xs8mN1ZhBzDrKC; Wed, 13 Sep 2017 02:06:12 +1000 (AEST) Received: by mail-pf0-x22f.google.com with SMTP id e199so19326065pfh.3; Tue, 12 Sep 2017 09:06:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mOg1qj3bHDzh6CsPalbmPZHFLiCIq2yv9R+jBz7JQ80=; b=P4bFe7yodi5eA+GhX7CaXrqUiJnLv4n5UJJfdmfDPacf/wMdvyOTsgd9r/DlcpxcKV gzaoeKezuuWZi3fyN1puv+vDsrrmg2yNEx6rdqCvLRuBCtw5b4tFc3gL2mTbgkVoWH06 NOWXzWArqKdT4U4MM4X5eOc13k4Wf/o4usPCv7UNs3uafv1NMRWRypXlayOiiR4EZpPX k6xzVLA8Z36sJnpQtHlySUQJD25kM3hQ/pBoU1XVwD10ooKqzjyGRzlmGfUD+7yg/V9z oZ3Vzg6tSYKEuDroUzeh1LW0Za90th3p2Du8TF04RmbAd1B2VFPZ50juplgWFdPBIPxH u26Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mOg1qj3bHDzh6CsPalbmPZHFLiCIq2yv9R+jBz7JQ80=; b=gURPCzvNmnU5UJgMb6Dkc5G63bpcQrD316iGgdNM1Rpur5rsUfb/gbTSVJwzyB8ILB ffMYw96dLIxr3S+RRpiG2hatFKzwFy/D8783G4VrKBjM8Wb2S9CDqRh1ClhH7cWz2jtg S7gdhE3wvXMb6Fi1Mf49N0pc2ewL6EdyFrmyvQibbNDDd+eGkqNbHi/a7C2U/9oRbBA4 jcO2XhZ1Y6reo86KRIvS+jcJhSDYZtExERZ/LKnyMKiiX7JLjcQhAfo2sp1i0bMpIPCO dsqffWfhvPvcm1gQrOdHbP2m9dEoxWaj9ywJQx05evxKgGwZ7Bw040Qlc0WII8aiMKzd 0tXA== X-Gm-Message-State: AHPjjUjoDA8+7JMcDXY0a7PaLGczkeBGFx+ABCDCbSnzdnvA2plF4g90 Gt8lQtxyjXJSsJ9S X-Google-Smtp-Source: AOwi7QDNDB7PtPQGbLP3cneimoCd1OBQcWdan4kzLiYZrqdFt1LgtPKSrTXi2HhQU8cXRFIdsSEH2w== X-Received: by 10.101.78.12 with SMTP id r12mr2321412pgt.289.1505232370114; Tue, 12 Sep 2017 09:06:10 -0700 (PDT) Received: from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202]) by smtp.gmail.com with ESMTPSA id q67sm21517424pfg.37.2017.09.12.09.06.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 09:06:09 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org, skiboot@lists.ozlabs.org Subject: [RFC PATCH 1/2] core: implement OPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms Date: Wed, 13 Sep 2017 02:05:52 +1000 Message-Id: <20170912160553.13422-2-npiggin@gmail.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170912160553.13422-1-npiggin@gmail.com> References: <20170912160553.13422-1-npiggin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin , Alistair Popple Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This implements a way to raise system reset interrupts on other cores. This has not yet been tested on DD2 or with deeper sleep states. --- core/Makefile.inc | 1 + core/sreset.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++++ hw/xscom.c | 2 + include/skiboot.h | 3 + platforms/mambo/mambo.c | 3 +- 5 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 core/sreset.c diff --git a/core/Makefile.inc b/core/Makefile.inc index f2de2f64..16204978 100644 --- a/core/Makefile.inc +++ b/core/Makefile.inc @@ -9,6 +9,7 @@ CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o +CORE_OBJS += sreset.o ifeq ($(SKIBOOT_GCOV),1) CORE_OBJS += gcov-profiling.o diff --git a/core/sreset.c b/core/sreset.c new file mode 100644 index 00000000..ff20fe71 --- /dev/null +++ b/core/sreset.c @@ -0,0 +1,237 @@ +/* Copyright 2017 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define P9_RAS_STATUS 0x10a02 +#define P9_RSTAT_QUIESCED(t) PPC_BITMASK(0 + 8*(t), 3 + 8*(t)) +#define P9_RAS_MODEREG 0x10a9d +#define P9_DIRECT_CONTROLS 0x10a9c +#define P9_DCTL_STOP(t) PPC_BIT(7 + 8*(t)) +#define P9_DCTL_CONT(t) PPC_BIT(6 + 8*(t)) +#define P9_DCTL_SRESET(t) PPC_BIT(4 + 8*(t)) +#define P9_DCTL_PWR(t) PPC_BIT(32 + 8*(t)) + +#define P9_CORE_THREAD_STATE 0x10ab3 +#define P9_CTS_STOP(t) PPC_BIT(56 + (t)) + +#define PPM_GPMMR 0xf0100 +#define PPM_SPWKUP_OTR 0xf010a +#define SPECIAL_WKUP_DONE PPC_BIT(1) + + +static int core_set_special_wakeup(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t swake_addr; + uint32_t gpmmr_addr; + uint64_t val; + int i; + + swake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR); + gpmmr_addr = XSCOM_ADDR_P9_EC(core_id, PPM_GPMMR); + + xscom_read(chip_id, swake_addr, &val); + if (xscom_write(chip_id, swake_addr, PPC_BIT(0))) { + prlog(PR_WARNING, "SRESET: Unable to write SPWKUP_OTR register\n"); + return OPAL_HARDWARE; + } + xscom_read(chip_id, swake_addr, &val); + + for (i = 0; i < 100; i++) { + if (xscom_read(chip_id, gpmmr_addr, &val)) { + prlog(PR_WARNING, "SRESET: Unable to read GPMMR register\n"); + return OPAL_HARDWARE; + } + if (val & SPECIAL_WKUP_DONE) + return 0; + + time_wait_us(1); + } + + xscom_read(chip_id, swake_addr, &val); + xscom_write(chip_id, swake_addr, 0); + xscom_read(chip_id, swake_addr, &val); + + prlog(PR_WARNING, "SRESET: Special wakeup mode could not be set.\n"); + return OPAL_HARDWARE; +} + +static void core_clear_special_wakeup(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t swake_addr; + uint64_t val; + + swake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR); + + /* De-assert special wakeup bit */ + xscom_read(chip_id, swake_addr, &val); + xscom_write(chip_id, swake_addr, 0); + xscom_read(chip_id, swake_addr, &val); +} + +static int thread_quiesced(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t ras_addr; + uint64_t ras_status; + + ras_addr = XSCOM_ADDR_P9_EC(core_id, P9_RAS_STATUS); + if (xscom_read(chip_id, ras_addr, &ras_status)) { + prlog(PR_WARNING, "SRESET: Unable to read status register\n"); + return OPAL_HARDWARE; + } + + if ((ras_status & P9_RSTAT_QUIESCED(thread_id)) + == P9_RSTAT_QUIESCED(thread_id)) + return 1; + + return 0; +} + +static int stop_thread(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t dctl_addr; + int i; + + dctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS); + + xscom_write(chip_id, dctl_addr, P9_DCTL_STOP(thread_id)); + + for (i = 0; i < 100; i++) { + int rc = thread_quiesced(cpu); + if (rc < 0) + break; + if (rc) + return 0; + } + + xscom_write(chip_id, dctl_addr, P9_DCTL_CONT(thread_id)); + prlog(PR_WARNING, "SRESET: Could not quiesce thread\n"); + return OPAL_HARDWARE; +} + +static int sreset_thread(struct cpu_thread *cpu) +{ + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint32_t thread_id = pir_to_thread_id(cpu->pir); + uint32_t dctl_addr; + uint32_t cts_addr; + uint64_t cts_val; + + dctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS); + cts_addr = XSCOM_ADDR_P9_EC(core_id, P9_CORE_THREAD_STATE); + + if (xscom_read(chip_id, cts_addr, &cts_val)) { + prlog(PR_WARNING, "SRESET: Unable to read CORE_THREAD_STATE register\n"); + return OPAL_HARDWARE; + } + if (!(cts_val & P9_CTS_STOP(thread_id))) { + /* Clear SRR1[46:47] */ + if (xscom_write(chip_id, dctl_addr, P9_DCTL_PWR(thread_id))) { + prlog(PR_WARNING, "SRESET: Unable to set power saving mode\n"); + return OPAL_HARDWARE; + } + } + + if (xscom_write(chip_id, dctl_addr, P9_DCTL_SRESET(thread_id))) { + prlog(PR_WARNING, "SRESET: Unable to write DIRECT_CONTROLS register\n"); + return OPAL_HARDWARE; + } + + return 0; +} + +// static struct lock sreset_lock = LOCK_UNLOCKED; + +static int64_t sreset_cpu(struct cpu_thread *cpu) +{ + int rc; + + if (this_cpu() == cpu) { + prlog(PR_WARNING, "SRESET: Unable to reset self\n"); + return OPAL_UNSUPPORTED; + } + if (this_cpu()->primary == cpu->primary) { + prlog(PR_WARNING, "SRESET: Unable to reset threads on same core\n"); + return OPAL_PARTIAL; + } + + rc = thread_quiesced(cpu); + if (rc < 0) + return rc; + if (rc) { + prlog(PR_WARNING, "SRESET: Thread is quiesced already\n"); + return OPAL_WRONG_STATE; + } + + rc = core_set_special_wakeup(cpu); + if (rc) + return rc; + + rc = stop_thread(cpu); + if (rc) { + core_clear_special_wakeup(cpu); + return rc; + } + + rc = sreset_thread(cpu); + + core_clear_special_wakeup(cpu); + + return 0; +} + +int64_t signal_system_reset(int cpu_nr) +{ + struct cpu_thread *cpu; + + if (proc_gen != proc_gen_p9) + return OPAL_UNSUPPORTED; + + /* Reset a single CPU */ + if (cpu_nr >= 0) { + cpu = find_cpu_by_server(cpu_nr); + if (!cpu) { + printf("SRESET: could not find cpu by server %d\n", cpu_nr); + return OPAL_PARAMETER; + } + return sreset_cpu(cpu); + } + printf("SRESET: unsupported %d\n", cpu_nr); + return OPAL_PARTIAL; +} diff --git a/hw/xscom.c b/hw/xscom.c index 7bd78bf9..f3e04291 100644 --- a/hw/xscom.c +++ b/hw/xscom.c @@ -705,6 +705,8 @@ static void xscom_init_chip_info(struct proc_chip *chip) printf("P9 DD%i.%i%d detected\n", 0xf & (chip->ec_level >> 4), chip->ec_level & 0xf, rev); chip->ec_rev = rev; + + opal_register(OPAL_SIGNAL_SYSTEM_RESET, signal_system_reset, 1); } } diff --git a/include/skiboot.h b/include/skiboot.h index 4b7d5197..37fd774f 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -198,6 +198,9 @@ extern char __sym_map_end[]; extern unsigned long get_symbol(unsigned long addr, char **sym, char **sym_end); +/* System reset */ +extern int64_t signal_system_reset(int cpu_nr); + /* Fast reboot support */ extern void disable_fast_reboot(const char *reason); extern void fast_reboot(void); diff --git a/platforms/mambo/mambo.c b/platforms/mambo/mambo.c index cb6e103c..e306ba5c 100644 --- a/platforms/mambo/mambo.c +++ b/platforms/mambo/mambo.c @@ -259,7 +259,8 @@ static int64_t mambo_signal_system_reset(int32_t cpu_nr) static void mambo_sreset_init(void) { - opal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1); + if (0) + opal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1); } static void mambo_platform_init(void) From patchwork Tue Sep 12 16:05:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 812947 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xs9183hK2z9s7f for ; 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[203.219.56.202]) by smtp.gmail.com with ESMTPSA id q67sm21517424pfg.37.2017.09.12.09.06.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 09:06:13 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org, skiboot@lists.ozlabs.org Subject: [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs with OPAL_SIGNAL_SYSTEM_RESET Date: Wed, 13 Sep 2017 02:05:53 +1000 Message-Id: <20170912160553.13422-3-npiggin@gmail.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170912160553.13422-1-npiggin@gmail.com> References: <20170912160553.13422-1-npiggin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin , Alistair Popple Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" There are two complications. The first is that sreset from stop states come in with SRR1 set to do a powersave wakeup, with an sreset reason encoded. The second is that threads on the same core can't be signalled directly so we must designate a bounce CPU to reflect the IPI back. --- arch/powerpc/include/asm/opal-api.h | 1 + arch/powerpc/include/asm/opal.h | 2 + arch/powerpc/kernel/irq.c | 13 +++ arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + arch/powerpc/platforms/powernv/powernv.h | 1 + arch/powerpc/platforms/powernv/setup.c | 3 + arch/powerpc/platforms/powernv/smp.c | 111 +++++++++++++++++++++++++ 7 files changed, 132 insertions(+) diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h index 450a60b81d2a..bd9d1f2b3584 100644 --- a/arch/powerpc/include/asm/opal-api.h +++ b/arch/powerpc/include/asm/opal-api.h @@ -188,6 +188,7 @@ #define OPAL_XIVE_DUMP 142 #define OPAL_XIVE_RESERVED3 143 #define OPAL_XIVE_RESERVED4 144 +#define OPAL_SIGNAL_SYSTEM_RESET 145 #define OPAL_NPU_INIT_CONTEXT 146 #define OPAL_NPU_DESTROY_CONTEXT 147 #define OPAL_NPU_MAP_LPAR 148 diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h index 726c23304a57..7d7613c49f2b 100644 --- a/arch/powerpc/include/asm/opal.h +++ b/arch/powerpc/include/asm/opal.h @@ -281,6 +281,8 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr); int opal_set_power_shift_ratio(u32 handle, int token, u32 psr); int opal_sensor_group_clear(u32 group_hndl, int token); +int64_t opal_signal_system_reset(int32_t cpu); + /* Internal functions */ extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data); diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 4e65bf82f5e0..3276e05cb53f 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -407,10 +407,23 @@ static const u8 srr1_to_lazyirq[0x10] = { PACA_IRQ_HMI, 0, 0, 0, 0, 0 }; +static noinline void system_reset(void) +{ + struct pt_regs regs; + ppc_save_regs(®s); + + get_paca()->in_nmi = 1; + system_reset_exception(®s); + get_paca()->in_nmi = 0; +} + void irq_set_pending_from_srr1(unsigned long srr1) { unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18; + if (unlikely(idx == 2 || idx == 4)) + system_reset(); + /* * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0, * so this can be called unconditionally with srr1 wake reason. diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S index 8c1ede2d3f7e..37cd170201a2 100644 --- a/arch/powerpc/platforms/powernv/opal-wrappers.S +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S @@ -307,6 +307,7 @@ OPAL_CALL(opal_xive_get_vp_info, OPAL_XIVE_GET_VP_INFO); OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO); OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC); OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP); +OPAL_CALL(opal_signal_system_reset, OPAL_SIGNAL_SYSTEM_RESET); OPAL_CALL(opal_npu_init_context, OPAL_NPU_INIT_CONTEXT); OPAL_CALL(opal_npu_destroy_context, OPAL_NPU_DESTROY_CONTEXT); OPAL_CALL(opal_npu_map_lpar, OPAL_NPU_MAP_LPAR); diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h index a159d48573d7..49add2037e0d 100644 --- a/arch/powerpc/platforms/powernv/powernv.h +++ b/arch/powerpc/platforms/powernv/powernv.h @@ -3,6 +3,7 @@ #ifdef CONFIG_SMP extern void pnv_smp_init(void); +extern int pnv_system_reset_exception(struct pt_regs *regs); #else static inline void pnv_smp_init(void) { } #endif diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c index 897aa1400eb8..4fdaa1d7c4cd 100644 --- a/arch/powerpc/platforms/powernv/setup.c +++ b/arch/powerpc/platforms/powernv/setup.c @@ -282,6 +282,9 @@ static void __init pnv_setup_machdep_opal(void) ppc_md.restart = pnv_restart; pm_power_off = pnv_power_off; ppc_md.halt = pnv_halt; +#ifdef CONFIG_SMP + ppc_md.system_reset_exception = pnv_system_reset_exception; +#endif ppc_md.machine_check_exception = opal_machine_check; ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; ppc_md.hmi_exception_early = opal_hmi_exception_early; diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c index c17f81e433f7..45b1c191e3c8 100644 --- a/arch/powerpc/platforms/powernv/smp.c +++ b/arch/powerpc/platforms/powernv/smp.c @@ -290,6 +290,112 @@ static void __init pnv_smp_probe(void) } } +static int nmi_ipi_bounce_cpu; +static int nmi_ipi_bounce_cpu_done; +static int nmi_ipi_bounce_target_core; +static int nmi_ipi_bounce_target_exclude; + +int pnv_system_reset_exception(struct pt_regs *regs) +{ + smp_mb(); + if (nmi_ipi_bounce_cpu == smp_processor_id()) { + int64_t rc; + int c; + + nmi_ipi_bounce_cpu = -1; + smp_mb(); + for_each_online_cpu(c) { + if (!cpumask_test_cpu(c, cpu_sibling_mask(nmi_ipi_bounce_target_core))) + continue; + if (c == nmi_ipi_bounce_target_exclude) + continue; + rc = opal_signal_system_reset(get_hard_smp_processor_id(c)); + if (rc != OPAL_SUCCESS) { + nmi_ipi_bounce_cpu_done = -1; + return 1; + } + } + nmi_ipi_bounce_cpu_done = 1; + } + + if (smp_handle_nmi_ipi(regs)) + return 1; + return 0; +} + +static int pnv_cause_nmi_ipi(int cpu) +{ + int64_t rc; + + if (cpu >= 0) { + rc = opal_signal_system_reset(get_hard_smp_processor_id(cpu)); + if (rc == OPAL_SUCCESS) + return 1; + return 0; + } else { + /* + * Test bounce behavior with broadcast IPI. + */ + rc = OPAL_PARTIAL; + } + if (rc == OPAL_PARTIAL) { + int c; + + /* + * Some platforms can not send NMI to sibling threads in + * the same core. We can designate one inter-core target + * to bounce NMIs back to our sibling threads. + */ + + if (cpu >= 0) { + /* + * Don't support bouncing unicast NMIs yet (because + * that would have to raise an NMI on an unrelated + * CPU. Revisit this if callers start using unicast. + */ + printk("CPU:%d pnv_cause_nmi_ipi can not bounce unicast IPIs!\n", smp_processor_id()); + return 0; + } + + nmi_ipi_bounce_cpu = -1; + nmi_ipi_bounce_cpu_done = 0; + nmi_ipi_bounce_target_core = -1; + nmi_ipi_bounce_target_exclude = -1; + + for_each_online_cpu(c) { + if (cpumask_test_cpu(c, cpu_sibling_mask(smp_processor_id()))) + continue; + + if (nmi_ipi_bounce_cpu == -1) { + nmi_ipi_bounce_cpu = c; + nmi_ipi_bounce_target_core = smp_processor_id(); + if (cpu == NMI_IPI_ALL_OTHERS) + nmi_ipi_bounce_target_exclude = smp_processor_id(); + smp_mb(); + } else { + rc = opal_signal_system_reset(get_hard_smp_processor_id(c)); + if (rc != OPAL_SUCCESS) + return 0; + } + } + + if (nmi_ipi_bounce_cpu == -1) + return 0; /* could not find a bouncer */ + + rc = opal_signal_system_reset(get_hard_smp_processor_id(nmi_ipi_bounce_cpu)); + if (rc != OPAL_SUCCESS) + return 0; + + while (!nmi_ipi_bounce_cpu_done) + cpu_relax(); + + if (nmi_ipi_bounce_cpu_done == 1) + return 1; /* bounce worked */ + } + + return 0; +} + static struct smp_ops_t pnv_smp_ops = { .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ .cause_ipi = NULL, /* Filled at runtime by pnv_smp_probe() */ @@ -308,6 +414,11 @@ static struct smp_ops_t pnv_smp_ops = { /* This is called very early during platform setup_arch */ void __init pnv_smp_init(void) { + if (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET)) { + printk("OPAL_SIGNAL_SYSTEM_RESET available\n"); + pnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi; + } else + printk("OPAL_SIGNAL_SYSTEM_RESET NOT available\n"); smp_ops = &pnv_smp_ops; #ifdef CONFIG_HOTPLUG_CPU