From patchwork Tue Nov 2 16:56:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549857 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20210112.gappssmtp.com header.i=@sartura-hr.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=jhu6aCoe; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HkGKP1Kgtz9sS8 for ; Wed, 3 Nov 2021 03:57:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbhKBQ7m (ORCPT ); Tue, 2 Nov 2021 12:59:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbhKBQ7l (ORCPT ); Tue, 2 Nov 2021 12:59:41 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EF71C0613B9 for ; Tue, 2 Nov 2021 09:57:06 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id m14so132890edd.0 for ; Tue, 02 Nov 2021 09:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rCu1OGKsqLNAMoqhoi0VbX309V/fJGalAsnrlUQrsDo=; b=jhu6aCoeAMLlRocldjYOcix0kXuZl4gF71djpFefPdNOQGs30if/nnpDdlta5lT1tK zA4ndWgiL7ifZJNHiMTU8lS3fqxHSZVeWUdYATfxTKNZMY7yJTyorp7FCYwkJAICszxB aBh3pZLPuD4FI4gO8tPbzWMkbcRo0Ao3EMD36Lt+G8wk9EmRpJ2MshD3T8c/9BcTBZzA WbrXYBvSWfIId4REndbN+/IWwa8P9+BhBB6kEnwzkmmmFjMiNaKTOKU5TCCzqi1oXkns YbMD7HmFic111lZjl8nMX0xSyj9Rloq2sIZfaWIGYWiHqPtvjz08pOJU1ModxmApv/dV oxbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=rCu1OGKsqLNAMoqhoi0VbX309V/fJGalAsnrlUQrsDo=; b=pNKwUPZdjYDH7PvubRVINYaLtPOI5Tl6xYO26gDRTPWih32u24BUeG8WEhywIsSiiZ PmkdxOrS/tQYyoVH8vvUPSioIAiqzfIltpdxnzIVOIMOEWIXkJE0kFPaJd3zH6cVBAiS kBr2niWvkdR5mpCtnbJCbkvbw46VNSVG9A97liTykSrRsB1UeuEzfTSu2tWCdkgk/SEV gnYPU7d9Qq3v93Ck3BjDQNCoUP27foyFU/hFHYgm0KYZ4NaljhEDpORTAc8KRbPwDzm1 3MvlLy/jTaHAzeYHQb45fvqFH6ihhw0b5G4H1ppdMyiFELKbrLDjWEhsXf/79jN0g/09 DqVg== X-Gm-Message-State: AOAM530FZ/MkSRrfa463c9T0FbCRT8oL2V409hgmTIRQLlWEtux5AOIU gVtyA9v1/SboPwEgahmeZQPmgw== X-Google-Smtp-Source: ABdhPJzTosDjNnPa+McFAm74Eaoj7BA3wjXHP3B/EHUfYt66n/QukfZLd9zrH9DUO8kLXNhJ9WyyYA== X-Received: by 2002:a17:907:3f83:: with SMTP id hr3mr46861059ejc.555.1635872224732; Tue, 02 Nov 2021 09:57:04 -0700 (PDT) Received: from fedora.. (cpezg-94-253-144-183-cbl.xnet.hr. [94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:04 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 1/6] mfd: simple-mfd-i2c: Add Delta TN48M CPLD support Date: Tue, 2 Nov 2021 17:56:52 +0100 Message-Id: <20211102165657.3428995-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Delta TN48M switches have a Lattice CPLD that serves multiple purposes including being a GPIO expander. So, lets use the simple I2C MFD driver to provide the MFD core. Also add a virtual symbol which pulls in the simple-mfd-i2c driver and provide a common symbol on which the subdevice drivers can depend on. Signed-off-by: Robert Marko Acked-for-MFD-by: Lee Jones --- Changes in v2: * Drop the custom MFD driver and header * Use simple I2C MFD driver --- drivers/mfd/Kconfig | 10 ++++++++++ drivers/mfd/simple-mfd-i2c.c | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ad15be6b86bc..3701657e831d 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -297,6 +297,16 @@ config MFD_ASIC3 This driver supports the ASIC3 multifunction chip found on many PDAs (mainly iPAQ and HTC based ones) +config MFD_TN48M_CPLD + tristate "Delta Networks TN48M switch CPLD driver" + depends on I2C + select MFD_SIMPLE_MFD_I2C + help + Select this option to enable support for Delta Networks TN48M switch + CPLD. It consists of reset and GPIO drivers. CPLD provides GPIOS-s + for the SFP slots as well as power supply related information. + SFP support depends on the GPIO driver being selected. + config PMIC_DA903X bool "Dialog Semiconductor DA9030/DA9034 PMIC Support" depends on I2C=y diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c index 87f684cff9a1..af8e91781417 100644 --- a/drivers/mfd/simple-mfd-i2c.c +++ b/drivers/mfd/simple-mfd-i2c.c @@ -39,6 +39,7 @@ static int simple_mfd_i2c_probe(struct i2c_client *i2c) static const struct of_device_id simple_mfd_i2c_of_match[] = { { .compatible = "kontron,sl28cpld" }, + { .compatible = "delta,tn48m-cpld" }, {} }; MODULE_DEVICE_TABLE(of, simple_mfd_i2c_of_match); From patchwork Tue Nov 2 16:56:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20210112.gappssmtp.com header.i=@sartura-hr.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=q7Uubr8O; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HkGKP6y9jz9sS8 for ; Wed, 3 Nov 2021 03:57:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234954AbhKBQ7s (ORCPT ); Tue, 2 Nov 2021 12:59:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234618AbhKBQ7n (ORCPT ); Tue, 2 Nov 2021 12:59:43 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B737DC0613F5 for ; Tue, 2 Nov 2021 09:57:07 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id f4so20152961edx.12 for ; Tue, 02 Nov 2021 09:57:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bJLBhHUS7qs9PSWzH59G7r313Yc/Cs8WjA0pjPpGbiE=; b=q7Uubr8OR4gWKbQqnqZs0imaFVtJrf+yggtGL2n6cEVh/wzwEjrcYM3sNQyqx5yLeC EGfDz0bW/FSGX7z//LJkIdVCwJtf8chZs+p39Kfnbui6fZUi60k3wtz+XuW8VFV4E6X2 cpvGJBaZPhuqvyD+YVHSOLCFJ+u2Y2UIzPYG3WntZsmH+P6EorVG0BYyN7XUwB3/G65+ rix985e6xnl5bnDeb2KnwDmTxglXW8CdET9e4MV+jomKiVRc5YmUKWDjf6pCoIe0/2wV vTJ2W+W+ZYsq6eZVbrNcrgqu9/Nradiws7/SxD9xKiUCmfxXp0DvWu9ovRObFwAvsWtN sbmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bJLBhHUS7qs9PSWzH59G7r313Yc/Cs8WjA0pjPpGbiE=; b=HEGOdsaGAOsfZ9ulrTbGsnLqb0Lo6ek6+XbB7IF1P1eUh39pVfqZNZFJ9WPC1tGgGw oiiIwmrp7P7/b5bEEB8O9seO9bvnt+YH78h0aOPt2ux3W8/tpU+FfFoLcqBiJai0ix+/ u0Qu58T654SZ30Cf6Ve9lHYXMAD94s64ylhf0dS2LR7k9GT2mDHIUlNavKy1kUlBfQUj GW6ma2WqFc6KBVfwjIo0mJiCA7cko7ou/I0xhOQtxM3Hjd+8SNAXsZgc0aec9P7tQA74 CPFac8nMKatqE+NRDF/0+AI51po3/Bh1cnq5LoqfmNfWuc1TSHVNr5s5kEBcx9MXuhd4 0A5Q== X-Gm-Message-State: AOAM533DcfuFUJ89oXAGfFQA1n+gALH5mfrmg26DR/8jgRLZ59Rdgb41 GffwzQBWDQqJhr/uqJB17vznFQ== X-Google-Smtp-Source: ABdhPJwiUeHAzZB3F9+g/QU/T6b56+4C/vPdgbNry+/IWlB1K1L+R7QCPpNymiHYNqnSToCwLOm6Fw== X-Received: by 2002:a05:6402:5189:: with SMTP id q9mr50720480edd.94.1635872226310; Tue, 02 Nov 2021 09:57:06 -0700 (PDT) Received: from fedora.. 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[94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:05 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 2/6] gpio: Add Delta TN48M CPLD GPIO driver Date: Tue, 2 Nov 2021 17:56:53 +0100 Message-Id: <20211102165657.3428995-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102165657.3428995-1-robert.marko@sartura.hr> References: <20211102165657.3428995-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Delta TN48M switch has an onboard Lattice CPLD that is used as a GPIO expander. The CPLD provides 12 pins in total on the TN48M, but on more advanced switch models it provides up to 192 pins, so the driver is extendable to support more switches. Signed-off-by: Robert Marko --- Changes in v7: * Change compatibles, reduce their number * Rework the driver to be easily extendible to support more devices * Use match data to populate configuration * Drop reviews and ACK-s as the driver changed Changes in v6: * Drop unused header * Return the return value of device_property_read_u32() instead of a hardcoded return Changes in v2: * Rewrite to use simple I2C MFD and GPIO regmap * Drop DT bindings for pin numbering --- drivers/gpio/Kconfig | 12 +++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-tn48m.c | 100 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/gpio/gpio-tn48m.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fab571016adf..5ccdf0636fad 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1344,6 +1344,18 @@ config GPIO_TIMBERDALE help Add support for the GPIO IP in the timberdale FPGA. +config GPIO_TN48M_CPLD + tristate "Delta Networks TN48M switch CPLD GPIO driver" + depends on MFD_TN48M_CPLD + select GPIO_REGMAP + help + This enables support for the GPIOs found on the Delta + Networks TN48M switch CPLD. + They are used for inputs and outputs on the SFP slots. + + This driver can also be built as a module. If so, the + module will be called gpio-tn48m. + config GPIO_TPS65086 tristate "TI TPS65086 GPO" depends on MFD_TPS65086 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 32a32659866a..93abc7461e45 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -148,6 +148,7 @@ obj-$(CONFIG_GPIO_TEGRA186) += gpio-tegra186.o obj-$(CONFIG_GPIO_TEGRA) += gpio-tegra.o obj-$(CONFIG_GPIO_THUNDERX) += gpio-thunderx.o obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o +obj-$(CONFIG_GPIO_TN48M_CPLD) += gpio-tn48m.o obj-$(CONFIG_GPIO_TPIC2810) += gpio-tpic2810.o obj-$(CONFIG_GPIO_TPS65086) += gpio-tps65086.o obj-$(CONFIG_GPIO_TPS65218) += gpio-tps65218.o diff --git a/drivers/gpio/gpio-tn48m.c b/drivers/gpio/gpio-tn48m.c new file mode 100644 index 000000000000..08909555e73d --- /dev/null +++ b/drivers/gpio/gpio-tn48m.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Delta TN48M CPLD GPIO driver + * + * Copyright (C) 2021 Sartura Ltd. + * + * Author: Robert Marko + */ + +#include +#include +#include +#include +#include +#include +#include + +enum tn48m_gpio_type { + TN48M_GP0 = 1, + TN48M_GPI, +}; + +struct tn48m_gpio_config { + int ngpio; + int ngpio_per_reg; + enum tn48m_gpio_type type; +}; + +static const struct tn48m_gpio_config tn48m_gpo_config = { + .ngpio = 4, + .ngpio_per_reg = 4, + .type = TN48M_GP0, +}; + +static const struct tn48m_gpio_config tn48m_gpi_config = { + .ngpio = 4, + .ngpio_per_reg = 4, + .type = TN48M_GPI, +}; + +static int tn48m_gpio_probe(struct platform_device *pdev) +{ + const struct tn48m_gpio_config *gpio_config = NULL; + struct gpio_regmap_config config = {0}; + struct regmap *regmap; + u32 base; + int ret; + + if (!pdev->dev.parent) + return -ENODEV; + + gpio_config = device_get_match_data(&pdev->dev); + if (!gpio_config) + return -ENODEV; + + ret = device_property_read_u32(&pdev->dev, "reg", &base); + if (ret) + return ret; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + config.regmap = regmap; + config.parent = &pdev->dev; + config.ngpio = gpio_config->ngpio; + config.ngpio_per_reg = gpio_config->ngpio_per_reg; + switch (gpio_config->type) { + case TN48M_GP0: + config.reg_set_base = base; + break; + case TN48M_GPI: + config.reg_dat_base = base; + break; + default: + return -EINVAL; + } + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config)); +} + +static const struct of_device_id tn48m_gpio_of_match[] = { + { .compatible = "delta,tn48m-gpo", .data = &tn48m_gpo_config }, + { .compatible = "delta,tn48m-gpi", .data = &tn48m_gpi_config }, + { } +}; +MODULE_DEVICE_TABLE(of, tn48m_gpio_of_match); + +static struct platform_driver tn48m_gpio_driver = { + .driver = { + .name = "delta-tn48m-gpio", + .of_match_table = tn48m_gpio_of_match, + }, + .probe = tn48m_gpio_probe, +}; +module_platform_driver(tn48m_gpio_driver); + +MODULE_AUTHOR("Robert Marko "); +MODULE_DESCRIPTION("Delta TN48M CPLD GPIO driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Nov 2 16:56:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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(cpezg-94-253-144-183-cbl.xnet.hr. [94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:07 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 3/6] dt-bindings: reset: Add Delta TN48M Date: Tue, 2 Nov 2021 17:56:54 +0100 Message-Id: <20211102165657.3428995-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102165657.3428995-1-robert.marko@sartura.hr> References: <20211102165657.3428995-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add header for the Delta TN48M CPLD provided resets. Signed-off-by: Robert Marko --- include/dt-bindings/reset/delta,tn48m-reset.h | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/dt-bindings/reset/delta,tn48m-reset.h diff --git a/include/dt-bindings/reset/delta,tn48m-reset.h b/include/dt-bindings/reset/delta,tn48m-reset.h new file mode 100644 index 000000000000..d4e9ed12de3e --- /dev/null +++ b/include/dt-bindings/reset/delta,tn48m-reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Delta TN48M CPLD GPIO driver + * + * Copyright (C) 2021 Sartura Ltd. + * + * Author: Robert Marko + */ + +#ifndef _DT_BINDINGS_RESET_TN48M_H +#define _DT_BINDINGS_RESET_TN48M_H + +#define CPU_88F7040_RESET 0 +#define CPU_88F6820_RESET 1 +#define MAC_98DX3265_RESET 2 +#define PHY_88E1680_RESET 3 +#define PHY_88E1512_RESET 4 +#define POE_RESET 5 + +#endif /* _DT_BINDINGS_RESET_TN48M_H */ From patchwork Tue Nov 2 16:56:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549864 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20210112.gappssmtp.com header.i=@sartura-hr.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=LzZBDppf; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HkGKb616fz9sS8 for ; Wed, 3 Nov 2021 03:57:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235026AbhKBQ74 (ORCPT ); Tue, 2 Nov 2021 12:59:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234926AbhKBQ7r (ORCPT ); Tue, 2 Nov 2021 12:59:47 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEA79C06120E for ; Tue, 2 Nov 2021 09:57:10 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id o8so6419212edc.3 for ; Tue, 02 Nov 2021 09:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rDDYTDspgp8Ul44UQDWDHvvXMcABRbKOgmSpNamD6mw=; b=LzZBDppf8fqM2ASseGTdwJ3XSlXUWIc5Ygovur1SMCJPuLPJKWPpNHKTbvBkr2Tv3l rsOX1qwNzjg0l0G6KCgWO+d70lldFWxtF88FDX2OHS6mNJCKQughC7F1GOuPjubGT7aE yCouxeMt+jfuquesK4NAcTvPbY9QzwSjpE0H+ULo7idOiruM25pBmpcpdX4K2NRfyx7D yivMHQSD6xyGooCwZb3VnjZ/ZqibE5FyGXodeStiE6kGLn1xxxddA/yRph+dkO8Moyth BC7ODvMlFHZHB3vEToquufbvzhbtcfZbToM38MGjyELkhjH6nEQt0oVbREgMDPJV64XK lEUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rDDYTDspgp8Ul44UQDWDHvvXMcABRbKOgmSpNamD6mw=; b=pdzk1Kjp8iYDMUvkkS8CFhciiOK78i0BRV7he8H1buMMAHrYXXCy3lZmB4P5mhSzPC ACut9HhkMuP8hj9JFBoRYZhCpzsvAMvt8CV3S8oSnRZ5SaQ7reRm+Obn39wi1EiSvb3N qXF2rvV7ECakqbTWz3nOtgl5I6c5gzi8p5uupPx4qFIQD3SJGIXeCViv21wrwGA5D4WJ /wGNjBG2tv9ZEdB0wKPz+H6aYKnZxdRpaPBggXz/kQaY2JKBz2ND62iCphsztu0IweTY Wx+CcP750b1RfFkwmht+9wajubT8z9XTcI8Wi2z5GmI6IXoLjmrosaBv54cbUvKDjWlJ 6Mrw== X-Gm-Message-State: AOAM531VI3vrFZ9zy2yBSiMt4CLDiOLvQpimlQ9Rv5Xr5zUhFmZga+10 RPdb+oag6PjaqqnG2IZAoaeXNQ== X-Google-Smtp-Source: ABdhPJzgAdAimWe6gdDH3/qbllQkSMNCek73zZknfI2crIypdTw1VLgIr8YIRNKHewfLykaIfB4Log== X-Received: by 2002:a05:6402:26d3:: with SMTP id x19mr17104215edd.279.1635872229377; Tue, 02 Nov 2021 09:57:09 -0700 (PDT) Received: from fedora.. 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[94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:09 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 4/6] reset: Add Delta TN48M CPLD reset controller Date: Tue, 2 Nov 2021 17:56:55 +0100 Message-Id: <20211102165657.3428995-4-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102165657.3428995-1-robert.marko@sartura.hr> References: <20211102165657.3428995-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Delta TN48M CPLD exposes resets for the following: * 88F7040 SoC * 88F6820 SoC * 98DX3265 switch MAC-s * 88E1680 PHY-s * 88E1512 PHY * PoE PSE controller Controller supports only self clearing resets. Signed-off-by: Robert Marko Reviewed-by: Philipp Zabel --- Changes in v5: * Allow COMPILE_TEST as well * Default to MFD_TN48M_CPLD Changes in v4: * Drop assert and deassert as only self-clearing resets are support by the HW * Make sure that reset is cleared before returning from reset. --- drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-tn48m.c | 128 ++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/reset/reset-tn48m.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5656cac04b4c..e76aba5f4c84 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -243,6 +243,16 @@ config RESET_TI_SYSCON you wish to use the reset framework for such memory-mapped devices, say Y here. Otherwise, say N. +config RESET_TN48M_CPLD + tristate "Delta Networks TN48M switch CPLD reset controller" + depends on MFD_TN48M_CPLD || COMPILE_TEST + default MFD_TN48M_CPLD + help + This enables the reset controller driver for the Delta TN48M CPLD. + It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X + switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and + Microchip PD69200 PoE PSE controller. + config RESET_UNIPHIER tristate "Reset controller driver for UniPhier SoCs" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ea8b8d9ca565..79beab92324f 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o +obj-$(CONFIG_RESET_TN48M_CPLD) += reset-tn48m.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o diff --git a/drivers/reset/reset-tn48m.c b/drivers/reset/reset-tn48m.c new file mode 100644 index 000000000000..8b58685f4043 --- /dev/null +++ b/drivers/reset/reset-tn48m.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Delta TN48M CPLD reset driver + * + * Copyright (C) 2021 Sartura Ltd. + * + * Author: Robert Marko + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TN48M_RESET_REG 0x10 + +#define TN48M_RESET_TIMEOUT 125000 +#define TN48M_RESET_SLEEP 10 + +struct tn48_reset_map { + u8 bit; +}; + +struct tn48_reset_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const struct tn48_reset_map tn48m_resets[] = { + [CPU_88F7040_RESET] = {0}, + [CPU_88F6820_RESET] = {1}, + [MAC_98DX3265_RESET] = {2}, + [PHY_88E1680_RESET] = {4}, + [PHY_88E1512_RESET] = {6}, + [POE_RESET] = {7}, +}; + +static inline struct tn48_reset_data *to_tn48_reset_data( + struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct tn48_reset_data, rcdev); +} + +static int tn48m_control_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct tn48_reset_data *data = to_tn48_reset_data(rcdev); + unsigned int val; + + regmap_update_bits(data->regmap, TN48M_RESET_REG, + BIT(tn48m_resets[id].bit), 0); + + return regmap_read_poll_timeout(data->regmap, + TN48M_RESET_REG, + val, + val & BIT(tn48m_resets[id].bit), + TN48M_RESET_SLEEP, + TN48M_RESET_TIMEOUT); +} + +static int tn48m_control_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct tn48_reset_data *data = to_tn48_reset_data(rcdev); + unsigned int regval; + int ret; + + ret = regmap_read(data->regmap, TN48M_RESET_REG, ®val); + if (ret < 0) + return ret; + + if (BIT(tn48m_resets[id].bit) & regval) + return 0; + else + return 1; +} + +static const struct reset_control_ops tn48_reset_ops = { + .reset = tn48m_control_reset, + .status = tn48m_control_status, +}; + +static int tn48m_reset_probe(struct platform_device *pdev) +{ + struct tn48_reset_data *data; + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap = regmap; + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &tn48_reset_ops; + data->rcdev.nr_resets = ARRAY_SIZE(tn48m_resets); + data->rcdev.of_node = pdev->dev.of_node; + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static const struct of_device_id tn48m_reset_of_match[] = { + { .compatible = "delta,tn48m-reset", }, + { } +}; +MODULE_DEVICE_TABLE(of, tn48m_reset_of_match); + +static struct platform_driver tn48m_reset_driver = { + .driver = { + .name = "delta-tn48m-reset", + .of_match_table = tn48m_reset_of_match, + }, + .probe = tn48m_reset_probe, +}; +module_platform_driver(tn48m_reset_driver); + +MODULE_AUTHOR("Robert Marko "); +MODULE_DESCRIPTION("Delta TN48M CPLD reset driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Nov 2 16:56:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20210112.gappssmtp.com header.i=@sartura-hr.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=py6HTfCT; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; 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(cpezg-94-253-144-183-cbl.xnet.hr. [94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:10 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 5/6] dt-bindings: mfd: Add Delta TN48M CPLD drivers bindings Date: Tue, 2 Nov 2021 17:56:56 +0100 Message-Id: <20211102165657.3428995-5-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102165657.3428995-1-robert.marko@sartura.hr> References: <20211102165657.3428995-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding documents for the Delta TN48M CPLD drivers. Signed-off-by: Robert Marko --- Changes in v7: * Update bindings to reflect driver updates Changes in v3: * Include bindings for reset driver Changes in v2: * Implement MFD as a simple I2C MFD * Add GPIO bindings as separate --- .../bindings/gpio/delta,tn48m-gpio.yaml | 39 ++++++++ .../bindings/mfd/delta,tn48m-cpld.yaml | 90 +++++++++++++++++++ .../bindings/reset/delta,tn48m-reset.yaml | 35 ++++++++ 3 files changed, 164 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml create mode 100644 Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml create mode 100644 Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml diff --git a/Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml b/Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml new file mode 100644 index 000000000000..e3e668a12091 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/delta,tn48m-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Delta Networks TN48M CPLD GPIO controller + +maintainers: + - Robert Marko + +description: | + This module is part of the Delta TN48M multi-function device. For more + details see ../mfd/delta,tn48m-cpld.yaml. + + Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander. + It provides 12 pins in total, they are input-only or ouput-only type. + +properties: + compatible: + enum: + - delta,tn48m-gpo + - delta,tn48m-gpi + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml b/Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml new file mode 100644 index 000000000000..f6967c1f6235 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Delta Networks TN48M CPLD controller + +maintainers: + - Robert Marko + +description: | + Lattice CPLD onboard the TN48M switches is used for system + management. + + It provides information about the hardware model, revision, + PSU status etc. + + It is also being used as a GPIO expander and reset controller + for the switch MAC-s and other peripherals. + +properties: + compatible: + const: delta,tn48m-cpld + + reg: + description: + I2C device address. + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +patternProperties: + "^gpio(@[0-9a-f]+)?$": + $ref: ../gpio/delta,tn48m-gpio.yaml + + "^reset-controller?$": + $ref: ../reset/delta,tn48m-reset.yaml + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cpld@41 { + compatible = "delta,tn48m-cpld"; + reg = <0x41>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@31 { + compatible = "delta,tn48m-gpo"; + reg = <0x31>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@3a { + compatible = "delta,tn48m-gpi"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@40 { + compatible = "delta,tn48m-gpi"; + reg = <0x40>; + gpio-controller; + #gpio-cells = <2>; + }; + + reset-controller { + compatible = "delta,tn48m-reset"; + #reset-cells = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml b/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml new file mode 100644 index 000000000000..0e5ee8decc0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/delta,tn48m-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Delta Networks TN48M CPLD reset controller + +maintainers: + - Robert Marko + +description: | + This module is part of the Delta TN48M multi-function device. For more + details see ../mfd/delta,tn48m-cpld.yaml. + + Reset controller modules provides resets for the following: + * 88F7040 SoC + * 88F6820 SoC + * 98DX3265 switch MAC-s + * 88E1680 PHY-s + * 88E1512 PHY + * PoE PSE controller + +properties: + compatible: + const: delta,tn48m-reset + + "#reset-cells": + const: 1 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false From patchwork Tue Nov 2 16:56:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1549862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20210112.gappssmtp.com header.i=@sartura-hr.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=K6Z/WKIn; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HkGKW3Wn6z9sS8 for ; Wed, 3 Nov 2021 03:57:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235003AbhKBQ7u (ORCPT ); Tue, 2 Nov 2021 12:59:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234981AbhKBQ7t (ORCPT ); Tue, 2 Nov 2021 12:59:49 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E199C061205 for ; Tue, 2 Nov 2021 09:57:14 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id r4so77526986edi.5 for ; Tue, 02 Nov 2021 09:57:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6adjk580AwBpX7D5EH7ECcA7MO/6lGH/OQuhWqLcWr0=; b=K6Z/WKIntLo8Wvu+jh8QfHtlz8BLZ31gcoWCgFijcbtgYPcYb7dAyofL/41MK+4MjU 9MnOo10fLpohPUZ6KCegL7XXRZKRlZLqX5J+tV8ZOKonZdnsWYuFL1GC8D0Ss/pB0YS5 TGUJDX6GEvXd7eIKLzq1yary9suq+4WrsCoeRfZnyEN7OyFS93pedB865UiV4ocDnXf4 h83NV+9+YXg5VleOOt06S/1glBKbZTQg48CpM6UvXWTq8oXh2vTAtgz2gRVRqLSmaXGe tRvjwOMx8olYEFpywPjJe9iX1hyP7Gcc2NKrcL+AUskYay105/OtwwpacJ5yH2JuWsHb aPgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6adjk580AwBpX7D5EH7ECcA7MO/6lGH/OQuhWqLcWr0=; b=p8HhPl7k1l08T8We3ppyysuG8+KO+kRJNPxvcX+RzIufcPr77qJ97P57dyZgsqX6Lm OnxExAyEcSk2SZTRLOcX8186uEMOJfCKG3FsDYUox4PvifFAkLkPRZd8MZ+i+MBo375Y QefQcz8BAVCOLaSp22/7liIE2uMIqDE4ivAloRyBTlY5oTlYN+B3qRKxIpG4X7WUMP8H SyeS5DMW+0Z1zlqYPOfdg3nk4kQD70i+H/QH8o4Yi9TiqGD1eGAY2vAyGeCsgR4INO04 Pq0oST3Oh2MD3n1zynxGDh54JifY0kum2dl1I0guO/cJrEexY26JacfMNi4JlbS+/XZB 3vYQ== X-Gm-Message-State: AOAM5330z+Ae0t4/LWWGApAd0yrNhFSk5TvsaekhwcpRbgtEGRAKNLRA 038cgf6DEEZ5wlbY3tqmIXfYxA== X-Google-Smtp-Source: ABdhPJy6cjSJNjn5rlsfGyomk3ptapZR6gmYMZ24mKVLvqJAdJ4U5YL6IdSvUqhvB/V6H/A9culDmw== X-Received: by 2002:a17:907:6d82:: with SMTP id sb2mr28178851ejc.440.1635872232620; Tue, 02 Nov 2021 09:57:12 -0700 (PDT) Received: from fedora.. (cpezg-94-253-144-183-cbl.xnet.hr. [94.253.144.183]) by smtp.googlemail.com with ESMTPSA id i22sm10816297edu.93.2021.11.02.09.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 09:57:12 -0700 (PDT) From: Robert Marko To: linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, lee.jones@linaro.org, p.zabel@pengutronix.de, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andrew@lunn.ch, andy.shevchenko@gmail.com Cc: Robert Marko Subject: [PATCH v7 6/6] MAINTAINERS: Add Delta Networks TN48M CPLD drivers Date: Tue, 2 Nov 2021 17:56:57 +0100 Message-Id: <20211102165657.3428995-6-robert.marko@sartura.hr> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102165657.3428995-1-robert.marko@sartura.hr> References: <20211102165657.3428995-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add maintainers entry for the Delta Networks TN48M CPLD MFD drivers. Signed-off-by: Robert Marko --- Changes in v3: * Add reset driver documentation Changes in v2: * Drop no more existing files --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d7b4f32875a9..92747bfc01db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5289,6 +5289,15 @@ S: Maintained F: Documentation/hwmon/dps920ab.rst F: drivers/hwmon/pmbus/dps920ab.c +DELTA NETWORKS TN48M CPLD DRIVERS +M: Robert Marko +S: Maintained +F: Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml +F: Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml +F: Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml +F: drivers/gpio/gpio-tn48m.c +F: include/dt-bindings/reset/delta,tn48m-reset.h + DENALI NAND DRIVER L: linux-mtd@lists.infradead.org S: Orphan