From patchwork Thu Oct 28 21:08:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547681 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=e4pYxWbE; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJ966MW0z9sRN for ; Fri, 29 Oct 2021 08:09:45 +1100 (AEDT) Received: from localhost ([::1]:41124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgCec-0006XS-O0 for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 17:09:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgCdp-0006WH-RB for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:08:54 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:43611) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgCdo-0004Qo-9t for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:08:53 -0400 Received: by mail-wr1-x42c.google.com with SMTP id p14so12414863wrd.10 for ; Thu, 28 Oct 2021 14:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P7XKV6+WQA6BTxZieVUejrAJ7DYt4kC6mGO6YlEwHeg=; b=e4pYxWbE322RZWlKCmEwIBH+286edAKgidoIC9OP/V8PPHlvFqgbk4AbUaket2qvk4 XgFe+0sY5bwws2SIoTyzm+OprJj9C8Fk2uudhCTL5QTpxjefRk1qbFuUCALRe3YQnoaM Sy5fEh41YEiuluVljWKCbX3VHQhCIJDiv8PfFvDCQG1qa4ZSTRaIs85fPtA6QREDi6nd Gu/tDKfxy26z0VKrSdPg/2Eo0ug7wZtG2OpGYBi2qL5EkqiD/SE5KmYf+uDHPg/jLUy6 GaAQZRYAFZ0tZtDsTSgE5xftKGs8xBb/KrmZhrS/+3n3M7mWhhXS70Qn7ZE66fSiX2uQ tN6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=P7XKV6+WQA6BTxZieVUejrAJ7DYt4kC6mGO6YlEwHeg=; b=ZDO0MFPn5+WLCaHajYf8mTDdTZAOlqr4i5QUS++DbHVN5YwE0aYV5jxxReBR+uRCYQ seapiRvSLXTaObo5IsoL6frfQgGdtc6hH57+l982T0rIfDKkt/fJLGYZ9D/lwWNxSwaj 1SU1H/WC5YK7710kuzLWyLztQ7z9BVsVLT5XKPORqp0XqDKfFEPgZYvmReHckzoybFGh bZyBvnOWmJKWX0a9E6yTvmg/+V8etSYaa89WgjnJ5B2mAybzEVVhHi4fRt4Sux5EIJm9 FU/Ox2kXrDMU+kOJSjAodOnmVigyXwiJZOQ6YQdqeVqTceUm2TYiLHjoP/qNxytQUlxP eEWA== X-Gm-Message-State: AOAM530/uZzIbFAa/8Tbv7IYjGPkZHHoaj09QqrtD1IXORNdYP//VmCX A87NG8otCR3Lf+4mAXuoGxOEXIruO20= X-Google-Smtp-Source: ABdhPJwyXF2XAdoPgskpyWstAy0Cjb3n+wS2ZLW15xdMRLEKwu5dWF+4PqsGo89ME9gfq6LlYUalYg== X-Received: by 2002:a05:6000:187:: with SMTP id p7mr9262119wrx.404.1635455330460; Thu, 28 Oct 2021 14:08:50 -0700 (PDT) Received: from x1w.redhat.com (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id l124sm7627355wml.8.2021.10.28.14.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:08:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 01/32] target/mips: Fix MSA MADDV.B opcode Date: Thu, 28 Oct 2021 23:08:12 +0200 Message-Id: <20211028210843.2120802-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.") Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_helper.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index e40c1b70575..d978909527f 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -3231,22 +3231,22 @@ void helper_msa_maddv_b(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->b[0] = msa_maddv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]); - pwd->b[1] = msa_maddv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]); - pwd->b[2] = msa_maddv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]); - pwd->b[3] = msa_maddv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]); - pwd->b[4] = msa_maddv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]); - pwd->b[5] = msa_maddv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]); - pwd->b[6] = msa_maddv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]); - pwd->b[7] = msa_maddv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]); - pwd->b[8] = msa_maddv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]); - pwd->b[9] = msa_maddv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]); - pwd->b[10] = msa_maddv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]); - pwd->b[11] = msa_maddv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]); - pwd->b[12] = msa_maddv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]); - pwd->b[13] = msa_maddv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]); - pwd->b[14] = msa_maddv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]); - pwd->b[15] = msa_maddv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]); + pwd->b[0] = msa_maddv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]); + pwd->b[1] = msa_maddv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]); + pwd->b[2] = msa_maddv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]); + pwd->b[3] = msa_maddv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]); + pwd->b[4] = msa_maddv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]); + pwd->b[5] = msa_maddv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]); + pwd->b[6] = msa_maddv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]); + pwd->b[7] = msa_maddv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]); + pwd->b[8] = msa_maddv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]); + pwd->b[9] = msa_maddv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]); + pwd->b[10] = msa_maddv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]); + pwd->b[11] = msa_maddv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]); + pwd->b[12] = msa_maddv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]); + pwd->b[13] = msa_maddv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]); + pwd->b[14] = msa_maddv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]); + pwd->b[15] = msa_maddv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]); } void helper_msa_maddv_h(CPUMIPSState *env, From patchwork Thu Oct 28 21:08:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id e9sm3983785wrn.2.2021.10.28.14.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:08:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 02/32] target/mips: Fix MSA MSUBV.B opcode Date: Thu, 28 Oct 2021 23:08:13 +0200 Message-Id: <20211028210843.2120802-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.") Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_helper.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index d978909527f..5667b1f0a15 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -3303,22 +3303,22 @@ void helper_msa_msubv_b(CPUMIPSState *env, wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - pwd->b[0] = msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]); - pwd->b[1] = msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]); - pwd->b[2] = msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]); - pwd->b[3] = msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]); - pwd->b[4] = msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]); - pwd->b[5] = msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]); - pwd->b[6] = msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]); - pwd->b[7] = msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]); - pwd->b[8] = msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]); - pwd->b[9] = msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]); - pwd->b[10] = msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10]); - pwd->b[11] = msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11]); - pwd->b[12] = msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12]); - pwd->b[13] = msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13]); - pwd->b[14] = msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14]); - pwd->b[15] = msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15]); + pwd->b[0] = msa_msubv_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]); + pwd->b[1] = msa_msubv_df(DF_BYTE, pwd->b[1], pws->b[1], pwt->b[1]); + pwd->b[2] = msa_msubv_df(DF_BYTE, pwd->b[2], pws->b[2], pwt->b[2]); + pwd->b[3] = msa_msubv_df(DF_BYTE, pwd->b[3], pws->b[3], pwt->b[3]); + pwd->b[4] = msa_msubv_df(DF_BYTE, pwd->b[4], pws->b[4], pwt->b[4]); + pwd->b[5] = msa_msubv_df(DF_BYTE, pwd->b[5], pws->b[5], pwt->b[5]); + pwd->b[6] = msa_msubv_df(DF_BYTE, pwd->b[6], pws->b[6], pwt->b[6]); + pwd->b[7] = msa_msubv_df(DF_BYTE, pwd->b[7], pws->b[7], pwt->b[7]); + pwd->b[8] = msa_msubv_df(DF_BYTE, pwd->b[8], pws->b[8], pwt->b[8]); + pwd->b[9] = msa_msubv_df(DF_BYTE, pwd->b[9], pws->b[9], pwt->b[9]); + pwd->b[10] = msa_msubv_df(DF_BYTE, pwd->b[10], pws->b[10], pwt->b[10]); + pwd->b[11] = msa_msubv_df(DF_BYTE, pwd->b[11], pws->b[11], pwt->b[11]); + pwd->b[12] = msa_msubv_df(DF_BYTE, pwd->b[12], pws->b[12], pwt->b[12]); + pwd->b[13] = msa_msubv_df(DF_BYTE, pwd->b[13], pws->b[13], pwt->b[13]); + pwd->b[14] = msa_msubv_df(DF_BYTE, pwd->b[14], pws->b[14], pwt->b[14]); + pwd->b[15] = msa_msubv_df(DF_BYTE, pwd->b[15], pws->b[15], pwt->b[15]); } void helper_msa_msubv_h(CPUMIPSState *env, From patchwork Thu Oct 28 21:08:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id u15sm3692579wmq.12.2021.10.28.14.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Date: Thu, 28 Oct 2021 23:08:14 +0200 Message-Id: <20211028210843.2120802-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The following commits added various user-mode tests for various MSA instructions: - 0fdd986a6c8 ("Add tests for MSA integer add instructions") - 1be82d89011 ("Add tests for MSA integer average instructions") - 1d336c87a3c ("Add tests for MSA bit set instructions") - 1e6bea794c8 ("Add tests for MSA integer max/min instructions") - 2a367db039f ("Add tests for MSA pack instructions") - 3d9569b8550 ("Add tests for MSA move instructions") - 4b302ce90db ("Add tests for MSA integer multiply instructions") - 520e210c0aa ("Add tests for MSA integer compare instructions") - 53e116fed6d ("Add tests for MSA integer subtract instructions") - 666952ea7c1 ("Add tests for MSA bit move instructions") - 72f463bc080 ("Add tests for MSA integer divide instructions") - 8598f5fac1c ("Add tests for MSA FP max/min instructions") - 99d423e576a ("Add tests for MSA shift instructions") - a8f91dd9fd0 ("Add tests for MSA integer dot product instructions") - b62592ab655 ("Add tests for MSA bit counting instructions") - ba632924450 ("Add tests for MSA logic instructions") - fc76f486677 ("Add tests for MSA interleave instructions") Cover them in the buildsys machinery so they are run automatically when calling 'make check-tcg'. Start running them on the mips64el target. Cc: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- Notes: - I am using $wilcard because because the test files are in multiple directories ($MSA_TEST_CLASS). - mips32 tests are disabled because the Debian toolchain produces: /usr/mips-linux-gnu/include/gnu/stubs.h:17:11: fatal error: gnu/stubs-o32_hard_2008.h: No such file or directory # include ^~~~~~~~~~~~~~~~~~~~~~~~~~~ --- tests/tcg/mips/ase-msa.mak | 30 ++++++++++++++++++++++++++++++ MAINTAINERS | 1 + tests/tcg/mips/Makefile.target | 5 +++++ tests/tcg/mips64/Makefile.target | 9 +++++++++ tests/tcg/mips64el/Makefile.target | 12 ++++++++++++ tests/tcg/mipsel/Makefile.target | 9 +++++++++ 6 files changed, 66 insertions(+) create mode 100644 tests/tcg/mips/ase-msa.mak create mode 100644 tests/tcg/mips64/Makefile.target create mode 100644 tests/tcg/mips64el/Makefile.target create mode 100644 tests/tcg/mipsel/Makefile.target diff --git a/tests/tcg/mips/ase-msa.mak b/tests/tcg/mips/ase-msa.mak new file mode 100644 index 00000000000..be1ba967a5b --- /dev/null +++ b/tests/tcg/mips/ase-msa.mak @@ -0,0 +1,30 @@ +# -*- Mode: makefile -*- +# +# MIPS MSA specific TCG tests +# +# Copyright (c) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later + +MSA_DIR = $(SRC_PATH)/tests/tcg/mips/user/ase/msa + +MSA_TEST_CLASS = bit-count bit-move bit-set fixed-multiply \ + float-max-min int-add int-average int-compare int-divide \ + int-dot-product interleave int-max-min int-modulo \ + int-multiply int-subtract logic move pack shift + +MSA_TEST_SRCS = $(foreach class,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(class)/*.c)) + +MSA_TESTS = $(patsubst %.c,%,$(notdir $(MSA_TEST_SRCS))) + +$(MSA_TESTS): CFLAGS+=-mmsa $(MSA_CFLAGS) +$(MSA_TESTS): %: $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/%.c)) + $(CC) -static $(CFLAGS) -o $@ \ + $(foreach CLASS,$(MSA_TEST_CLASS),$(wildcard $(MSA_DIR)/$(CLASS)/$@.c)) + +$(foreach test,$(MSA_TESTS),run-$(test)): QEMU_OPTS += -cpu $(MSA_CPU) + +# FIXME: These tests fail when using plugins +ifneq ($(CONFIG_PLUGIN),y) +TESTS += $(MSA_TESTS) +endif diff --git a/MAINTAINERS b/MAINTAINERS index 894dc431052..0a1475a6e83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3112,6 +3112,7 @@ R: Jiaxun Yang R: Aleksandar Rikalo S: Odd Fixes F: tcg/mips/ +F: tests/tcg/mips* PPC TCG target M: Richard Henderson diff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target index 1a994d5525e..fc54f144f37 100644 --- a/tests/tcg/mips/Makefile.target +++ b/tests/tcg/mips/Makefile.target @@ -17,3 +17,8 @@ TESTS += $(MIPS_TESTS) hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -mabi=32 hello-mips: LDFLAGS+=-nostdlib endif + +# FIXME enable MSA tests +#MSA_CFLAGS=-march=mips32r5 -mnan=2008 +#MSA_CPU=P5600 +#include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target new file mode 100644 index 00000000000..d876b92f219 --- /dev/null +++ b/tests/tcg/mips64/Makefile.target @@ -0,0 +1,9 @@ +# -*- Mode: makefile -*- +# +# mips64el specific TCG tests +# +# Copyright (c) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# 64-bit MSA is tested on little-endian target diff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target new file mode 100644 index 00000000000..87c0d6dce18 --- /dev/null +++ b/tests/tcg/mips64el/Makefile.target @@ -0,0 +1,12 @@ +# -*- Mode: makefile -*- +# +# mips64el specific TCG tests +# +# Copyright (c) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# MSA +MSA_CFLAGS=-march=mips64r5 -mnan=legacy +MSA_CPU=Loongson-3A4000 +include $(SRC_PATH)/tests/tcg/mips/ase-msa.mak diff --git a/tests/tcg/mipsel/Makefile.target b/tests/tcg/mipsel/Makefile.target new file mode 100644 index 00000000000..c8acacb4497 --- /dev/null +++ b/tests/tcg/mipsel/Makefile.target @@ -0,0 +1,9 @@ +# -*- Mode: makefile -*- +# +# mipsel specific TCG tests +# +# Copyright (c) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# 32-bit MSA is tested on big-endian target From patchwork Thu Oct 28 21:08:15 2021 Content-Type: text/plain; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p1sm7339858wmq.23.2021.10.28.14.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 04/32] target/mips: Use dup_const() to simplify Date: Thu, 28 Oct 2021 23:08:15 +0200 Message-Id: <20211028210843.2120802-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The dup_const() helper makes the code easier to follow, use it. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v3: Fix eval_big --- target/mips/tcg/msa_translate.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 3ef912da6b8..6fefb06da7c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -313,28 +313,11 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, { /* generates tcg ops to check if any element is 0 */ /* Note this function only works with MSA_WRLEN = 128 */ - uint64_t eval_zero_or_big = 0; - uint64_t eval_big = 0; + uint64_t eval_zero_or_big = dup_const(df, 1); + uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); - switch (df) { - case DF_BYTE: - eval_zero_or_big = 0x0101010101010101ULL; - eval_big = 0x8080808080808080ULL; - break; - case DF_HALF: - eval_zero_or_big = 0x0001000100010001ULL; - eval_big = 0x8000800080008000ULL; - break; - case DF_WORD: - eval_zero_or_big = 0x0000000100000001ULL; - eval_big = 0x8000000080000000ULL; - break; - case DF_DOUBLE: - eval_zero_or_big = 0x0000000000000001ULL; - eval_big = 0x8000000000000000ULL; - break; - } + tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); tcg_gen_andi_i64(t0, t0, eval_big); From patchwork Thu Oct 28 21:08:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=XwQQx1TD; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJGC1qb2z9sRN for ; Fri, 29 Oct 2021 08:14:11 +1100 (AEDT) Received: from localhost ([::1]:49520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgCiu-00041f-Uo for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 17:14:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgCe9-0006kj-Js for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:13 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgCe7-0004Wi-NC for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:13 -0400 Received: by mail-wr1-x436.google.com with SMTP id i5so4794432wrb.2 for ; Thu, 28 Oct 2021 14:09:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YAKg+J+/v36lzQhjd3D8tkZ+FOwUKvRjy9noDtRnWEA=; b=XwQQx1TDvgMuRglgi7abeLDaVeCCMmlk0jccUvA8TSnmm9FHvBzosstCUHpFYfFNR3 1MTDlHpKywGVCtwmlHvmlReJpnITFPHqRhXs2XA/prczRP1luVYYcLgcwQvtwjfPY8sj eawORhqhpFoLpa8XYc6br9tITBg7SIgt0OjFEHGkkAExaAcA6aOfPOEKXN1WfeYes/KI j7Z0OMyt0FiP3ZJ+pQX2gC9Q/SEzx2v4ABn6djmzQG42Ls9GVEuCGErxmX7yjL6qUiYo U9PPbfUT4kvSQlYYH4o/W/XdeIsvMS0gEn6xziGgNBMjw/IUO5DJr3iLxvyPsSsuL8nO ocww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YAKg+J+/v36lzQhjd3D8tkZ+FOwUKvRjy9noDtRnWEA=; b=UI3Dt53h2jdpCUWbJ+esFVcmCUYZOA+fv40m4Rs2y9Poy6c9y7vxPpf/pg79sHMxgc 8JRZXaByb5fXf5q1hnKV62r5Qg6KmaKnm9eq9q/Cled5iiNfbfIoRdqQOy28b58H4FeU vF+Li+8JlZa2Kl2HqaEdv101qWvebYQ4xXFT3QzDae6dh3cVlE2VLWH3UKOPyMy+8QJu 1QiDxDdhckAHCqbzbrQFjg4UFgFmgZe5bJnPepopYNAO5Lu7o5fPvG4NkzGJXQZZfisH aarObvq35vlA+n2jDinKNJyGrxBbFCbdCMFEjkSX1cPi0gxVjtj1gcZmaam2TL1345hJ Dewg== X-Gm-Message-State: AOAM532qnrr95/JSnknlFe9NEbZRqZnCTT9l8A3DJbENjDvqfgx7yCel egWihyclAEBYzS+SE0Rv2EzIug7AvQw= X-Google-Smtp-Source: ABdhPJz61yIdg0/AD5SLpJIUYcyyh6VsisNtGN2A4x8hzDmpgrnwUHz+oubSIIUXAmZuTKkChkw5hw== X-Received: by 2002:a5d:6d0a:: with SMTP id e10mr8631741wrq.348.1635455350281; Thu, 28 Oct 2021 14:09:10 -0700 (PDT) Received: from x1w.redhat.com (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id k63sm7300090wme.22.2021.10.28.14.09.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 05/32] target/mips: Have check_msa_access() return a boolean Date: Thu, 28 Oct 2021 23:08:16 +0200 Message-Id: <20211028210843.2120802-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Have check_msa_access() return a boolean value so we can return early if MSA is not enabled (the instruction got decoded properly, but we raised an exception). Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211027180730.1551932-6-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 6fefb06da7c..242d6ccf669 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -293,19 +293,24 @@ void msa_translate_init(void) } } -static inline int check_msa_access(DisasContext *ctx) +/* + * Check if MSA is enabled. + * This function is always called with MSA available. + * If MSA is disabled, raise an exception. + */ +static inline bool check_msa_enabled(DisasContext *ctx) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { gen_reserved_instruction(ctx); - return 0; + return false; } if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { generate_exception_end(ctx, EXCP_MSADIS); - return 0; + return false; } - return 1; + return true; } static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, @@ -337,7 +342,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) { TCGv_i64 t0; - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -369,7 +376,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) { - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -2141,7 +2150,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode = ctx->opcode; - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } switch (MASK_MSA_MINOR(opcode)) { case OPC_MSA_I8_00: From patchwork Thu Oct 28 21:08:17 2021 Content-Type: text/plain; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p12sm4339207wrr.67.2021.10.28.14.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Date: Thu, 28 Oct 2021 23:08:17 +0200 Message-Id: <20211028210843.2120802-7-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Replace magic DataFormat value by the corresponding enum from CPUMIPSMSADataFormat. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 242d6ccf669..e4bf42530fc 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -1789,10 +1789,10 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_MULR_Q_df: case OPC_MADDR_Q_df: case OPC_MSUBR_Q_df: - tdf = tcg_constant_i32(df + 1); + tdf = tcg_constant_i32(DF_HALF + df); break; default: - tdf = tcg_constant_i32(df + 2); + tdf = tcg_constant_i32(DF_WORD + df); break; } @@ -2021,7 +2021,7 @@ static void gen_msa_2rf(DisasContext *ctx) TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); /* adjust df value for floating-point instruction */ - TCGv_i32 tdf = tcg_constant_i32(df + 2); + TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df); switch (MASK_MSA_2RF(ctx->opcode)) { case OPC_FCLASS_df: From patchwork Thu Oct 28 21:08:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=ea5rJn+P; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJSH11Zgz9sRN for ; Fri, 29 Oct 2021 08:22:53 +1100 (AEDT) Received: from localhost ([::1]:38098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgCrK-00072O-F7 for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 17:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgCeI-00076S-UW for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:22 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:44808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgCeH-0004qj-7Z for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:22 -0400 Received: by mail-wr1-x42f.google.com with SMTP id d13so12444368wrf.11 for ; Thu, 28 Oct 2021 14:09:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SIs60s0fc+p1xM+8sNRwlUl7N9HesUDIt6LmbgzPTmA=; b=ea5rJn+P3jldjts1MJFBybJqoG5V5p61g5vq5SewXRStbUwUd+sMRiXLljE7C8GIXO 97bWXv6be2hnxarepshcbH+7AwQgsdYzyCJMQeQo5cAo0vUGWRogxGTSukOR5ai7QqEQ ECv9ao4Olux45XVuSxxjReFxhxdZfB2fUmFF9snHPE8gSW8ntnWZB5sNmj+gzSB1Yck4 IRB29oR9QfhHdBEKfeNGiI0iGfZyW7VTia85KpI/2AKt+msmfhmHoffHwRBKnRt2VX5v 30mSiXfcGqvfjPJuVE9dP3AhDWcs074zrsm5TbmSxQOFkilxLisfTRrjt61N+shBnykW Bx1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SIs60s0fc+p1xM+8sNRwlUl7N9HesUDIt6LmbgzPTmA=; b=RTcE8fqCDuIwuLiS0+RO2wyU10gfPYc1sUz8oVTDFs9h0N11Sr53aMJcgncSpY7Hqq RURM1KND2+l+BPzuMwu/36V5DhrjFUAhiw9q8lg97xfgd1KFpGXd6B2t2C4TU4xAz6cS X7V0LrjGc5P/inzOvOdJV7D1xWExzfwlhhAhKAgWMJvgxJijZIFgoCL4UPowKa400EL1 mq25uxcbjozSj2Vak2o0BpcMQGYxUhvtDNoZyR13cemAGt0sB60X8XGldJP4F1HUN3u3 pXjgHzUDBe1qwgWf4nemYiIAJ+ypom0dGpaxSsO8tyNRmrQ7wQwho3JLdMlufvyPVDED GHkg== X-Gm-Message-State: AOAM533NRHeL3ZrK45AoQ/mB/B6hZ6RXMHkp/fMmXJKNa+znrhZm4h/N iCnQtWkP2Iq95KIVepcohX3DMJVrfJE= X-Google-Smtp-Source: ABdhPJw1wVdnpVsD5gd0dk52nbeYiabWMLxncwtJsAjbAtyHfBxqWGQPiq2z1/WJkIoRowLC7IZ0MA== X-Received: by 2002:adf:f210:: with SMTP id p16mr8466356wro.61.1635455359662; Thu, 28 Oct 2021 14:09:19 -0700 (PDT) Received: from x1w.redhat.com (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id u10sm5326753wrs.5.2021.10.28.14.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Date: Thu, 28 Oct 2021 23:08:18 +0200 Message-Id: <20211028210843.2120802-8-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3) and @bz_df -> @bz (generic @bz). Since we modify &msa_bz, re-align its arguments, so the other structures added in the following commits stay visually aligned. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 15 +++++++-------- target/mips/tcg/msa_translate.c | 20 ++++++++++---------- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 74d99f6862c..56419a24eb9 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,19 +13,18 @@ &r rs rt rd sa -&msa_bz df wt s16 +&msa_bz df wt sa @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r -@bz ...... ... .. wt:5 s16:16 &msa_bz df=3 -@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz +@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 +@bz ...... ... df:2 wt:5 sa:16 &msa_bz LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa -BZ_V 010001 01011 ..... ................ @bz -BNZ_V 010001 01111 ..... ................ @bz - -BZ_x 010001 110 .. ..... ................ @bz_df -BNZ_x 010001 111 .. ..... ................ @bz_df +BZ_V 010001 01011 ..... ................ @bz_v +BNZ_V 010001 01111 ..... ................ @bz_v +BZ 010001 110 .. ..... ................ @bz +BNZ 010001 111 .. ..... ................ @bz MSA 011110 -------------------------- diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index e4bf42530fc..e1d90fbde25 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -338,7 +338,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, tcg_temp_free_i64(t1); } -static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) { TCGv_i64 t0; @@ -356,7 +356,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) tcg_gen_trunc_i64_tl(bcond, t0); tcg_temp_free_i64(t0); - ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; + ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; ctx->hflags |= MIPS_HFLAG_BC; ctx->hflags |= MIPS_HFLAG_BDS32; @@ -366,15 +366,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); + return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); } static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); + return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); } -static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) { if (!check_msa_enabled(ctx)) { return true; @@ -387,21 +387,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); - ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4; + ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; ctx->hflags |= MIPS_HFLAG_BC; ctx->hflags |= MIPS_HFLAG_BDS32; return true; } -static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); + return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); } -static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) { - return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); + return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); } static void gen_msa_i8(DisasContext *ctx) From patchwork Thu Oct 28 21:08:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547699 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=TQXbW6DV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJXf37LXz9sRN for ; Fri, 29 Oct 2021 08:26:42 +1100 (AEDT) Received: from localhost ([::1]:46474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgCv2-0004j3-7A for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 17:26:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgCeO-0007RB-Hy for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:28 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:35659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgCeM-0004yz-4o for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:09:28 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 207-20020a1c04d8000000b0033123de3425so197988wme.0 for ; Thu, 28 Oct 2021 14:09:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=44+0BdbNYoS9vGV6dypVqoCubvCqjI18YnDpGXWrlyU=; b=TQXbW6DVkKsBX+zAaEepO5Su9U0DFbqUXz1AfhJCyefcYdn0e7agqJOC+xic6quS19 4F3I0I2qiJx7vb8Re8/3ZdiJW6du4Bq8aLvl8SuLIu7IxItpovF2pMK25xYOJ4HRvC5a 4J+28B8G+3ktgTDZrQPqEsVjQmCoGDmo0C0+X0SA6fT+Ri2ucBFs+frIcL9/6NYjVCvM qk8+fisp6AXx9bJ/46cmlKMyJ8gHybOXEsmEL5djC7I4W0svaimqZDE5Sa6yUYghWs35 jDBkGv5bb6CTn65mXryb69r5YmnuE3El5itHqoh9y4j1BOa6c+B56+M4sQD+Gjzvide0 3ZPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=44+0BdbNYoS9vGV6dypVqoCubvCqjI18YnDpGXWrlyU=; b=F9tJguN5zU8ET05mByw0/vu47dEwUtcDTJCYZ1wR8yTUZixTKEQwt1WI+gE3svpnoW 3apx1ZFMMDzYAHnSWKuCBLTGeanvuxql7D6/VmWvN3M6RKUUjRANLpWCqZREPu0562zI Kzz9Kt39qY/jhOuN3ob7fO++GYI20PFYVH30R6rmBy5HX1xgad6zkMVbL+S4GEY9Drp8 Mv4FTOfEHjTizQvJOiUimsVKHBEuxQO9Xst4J3gScLrduXTbBEftiLzmEUTHBvb4+7iP TuLVx+KIR3OtDoVFKdQzT4od2zCKsBIsNYUqgbbnUoy+aDv7Bt76tL2iIL9kjSUwiqBd RXPw== X-Gm-Message-State: AOAM5338k5Vv1TV+IdLrmwbpPjVJi5AaaCkecTZmxncFRgCumcPPDuej Kk5uH4jdoSm1a9+Z9BPhJmNgIlvWgS4= X-Google-Smtp-Source: ABdhPJx1ZK+BYAlwHH8ZJlzTvjDeVWRyWBtPkGq69dCHynDGtfw0Ye6fvPgw+hO34VgQ7K93hydEEw== X-Received: by 2002:a7b:ce94:: with SMTP id q20mr7006142wmj.34.1635455364540; Thu, 28 Oct 2021 14:09:24 -0700 (PDT) Received: from x1w.redhat.com (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id o11sm6221125wry.0.2021.10.28.14.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 08/32] target/mips: Convert MSA LDI opcode to decodetree Date: Thu, 28 Oct 2021 23:08:19 +0200 Message-Id: <20211028210843.2120802-9-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the LDI opcode (Immediate Load) to decodetree. Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211027180730.1551932-6-f4bug@amsat.org> --- target/mips/tcg/msa.decode | 8 +++++++- target/mips/tcg/msa_translate.c | 22 ++++++++++++++-------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 56419a24eb9..bdfe5a24cb3 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -14,10 +14,12 @@ &r rs rt rd sa &msa_bz df wt sa +&msa_ldi df wd sa @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -27,4 +29,8 @@ BNZ_V 010001 01111 ..... ................ @bz_v BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz -MSA 011110 -------------------------- +{ + LDI 011110 110 .. .......... ..... 000111 @ldi + + MSA 011110 -------------------------- +} diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index e1d90fbde25..ff78359597f 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -70,7 +70,6 @@ enum { OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07, OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06, OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df = (0x6 << 23) | OPC_MSA_I5_07, /* I8 instruction */ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, @@ -513,13 +512,6 @@ static void gen_msa_i5(DisasContext *ctx) case OPC_CLEI_U_df: gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); break; - case OPC_LDI_df: - { - int32_t s10 = sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -532,6 +524,20 @@ static void gen_msa_i5(DisasContext *ctx) tcg_temp_free_i32(timm); } +static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_ldi_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->sa)); + + return true; +} + static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) From patchwork Thu Oct 28 21:08:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id l6sm3427805wmq.17.2021.10.28.14.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 09/32] target/mips: Convert MSA I5 instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:20 +0200 Message-Id: <20211028210843.2120802-10-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- v3: Renamed &msa_i5 -> &msa_i --- target/mips/tcg/msa.decode | 16 +++++ target/mips/tcg/msa_translate.c | 102 ++++++++------------------------ 2 files changed, 41 insertions(+), 77 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bdfe5a24cb3..cd2b618684a 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -15,10 +15,13 @@ &msa_bz df wt sa &msa_ldi df wd sa +&msa_i df wd ws sa @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i +@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi LSA 000000 ..... ..... ..... 000 .. 000101 @lsa @@ -30,6 +33,19 @@ BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz { + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 + SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 + MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 + MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 + MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 + MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 + + CEQI 011110 000 .. ..... ..... ..... 000111 @s5 + CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 + CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 + CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 + CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 + LDI 011110 110 .. .......... ..... 000111 @ldi MSA 011110 -------------------------- diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index ff78359597f..13e7317d3d8 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,8 +27,6 @@ enum { OPC_MSA_I8_00 = 0x00 | OPC_MSA, OPC_MSA_I8_01 = 0x01 | OPC_MSA, OPC_MSA_I8_02 = 0x02 | OPC_MSA, - OPC_MSA_I5_06 = 0x06 | OPC_MSA, - OPC_MSA_I5_07 = 0x07 | OPC_MSA, OPC_MSA_BIT_09 = 0x09 | OPC_MSA, OPC_MSA_BIT_0A = 0x0A | OPC_MSA, OPC_MSA_3R_0D = 0x0D | OPC_MSA, @@ -58,19 +56,6 @@ enum { }; enum { - /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */ - OPC_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07, - /* I8 instruction */ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01, @@ -312,6 +297,8 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } +typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -461,69 +448,34 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } -static void gen_msa_i5(DisasContext *ctx) +static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, + gen_helper_piiii *gen_msa_i5) { -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 = extract32(ctx->opcode, 16, 5); - - TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2)); - TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5)); - TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5)); - TCGv_i32 timm = tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); - - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); + gen_msa_i5(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; } +TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); +TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); +TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); +TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); +TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); +TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); +TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); +TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); +TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); +TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); +TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); + static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) { if (!check_msa_enabled(ctx)) { @@ -2166,10 +2118,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: gen_msa_bit(ctx); From patchwork Thu Oct 28 21:08:21 2021 Content-Type: text/plain; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id a4sm3274401wmb.39.2021.10.28.14.09.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 10/32] target/mips: Convert MSA BIT instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:21 +0200 Message-Id: <20211028210843.2120802-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v3: - Renamed &msa_i5 -> &msa_i - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 19 ++++ target/mips/tcg/msa_translate.c | 179 +++++++++++++++----------------- 2 files changed, 101 insertions(+), 97 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index cd2b618684a..3d6c6faf688 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -16,6 +16,10 @@ &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa +&msa_bit df wd ws m + +%bit_df 16:7 !function=bit_df +%bit_m 16:7 !function=bit_m @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @@ -23,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi +@bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa @@ -48,5 +53,19 @@ BNZ 010001 111 .. ..... ................ @bz LDI 011110 110 .. .......... ..... 000111 @ldi + SLLI 011110 000 ....... ..... ..... 001001 @bit + SRAI 011110 001 ....... ..... ..... 001001 @bit + SRLI 011110 010 ....... ..... ..... 001001 @bit + BCLRI 011110 011 ....... ..... ..... 001001 @bit + BSETI 011110 100 ....... ..... ..... 001001 @bit + BNEGI 011110 101 ....... ..... ..... 001001 @bit + BINSLI 011110 110 ....... ..... ..... 001001 @bit + BINSRI 011110 111 ....... ..... ..... 001001 @bit + + SAT_S 011110 000 ....... ..... ..... 001010 @bit + SAT_U 011110 001 ....... ..... ..... 001010 @bit + SRARI 011110 010 ....... ..... ..... 001010 @bit + SRLRI 011110 011 ....... ..... ..... 001010 @bit + MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 13e7317d3d8..cd86d6cc5c0 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,9 @@ #include "fpu_helper.h" #include "internal.h" +static int bit_m(DisasContext *ctx, int x); +static int bit_df(DisasContext *ctx, int x); + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" @@ -27,8 +30,6 @@ enum { OPC_MSA_I8_00 = 0x00 | OPC_MSA, OPC_MSA_I8_01 = 0x01 | OPC_MSA, OPC_MSA_I8_02 = 0x02 | OPC_MSA, - OPC_MSA_BIT_09 = 0x09 | OPC_MSA, - OPC_MSA_BIT_0A = 0x0A | OPC_MSA, OPC_MSA_3R_0D = 0x0D | OPC_MSA, OPC_MSA_3R_0E = 0x0E | OPC_MSA, OPC_MSA_3R_0F = 0x0F | OPC_MSA, @@ -222,20 +223,6 @@ enum { OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) = _B _H _W _D */ - OPC_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09, }; static const char msaregnames[][6] = { @@ -257,6 +244,59 @@ static const char msaregnames[][6] = { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; +/* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ +struct dfe { + int start; + int length; + uint32_t mask; +}; + +/* + * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). + * Returns the immediate value, or -1 if the format does not match. + */ +static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) +{ + for (unsigned i = 0; i < 4; i++) { + if (extract32(x, s->start, s->length) == s->mask) { + return extract32(x, 0, s->start); + } + } + return -1; +} + +/* + * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). + * Returns the DataField, or -1 if the format does not match. + */ +static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) +{ + for (unsigned i = 0; i < 4; i++) { + if (extract32(x, s->start, s->length) == s->mask) { + return i; + } + } + return -1; +} + +static const struct dfe df_bit[] = { + /* Table 3.28 BIT Instruction Format */ + [DF_BYTE] = {3, 4, 0b1110}, + [DF_HALF] = {4, 3, 0b110}, + [DF_WORD] = {5, 2, 0b10}, + [DF_DOUBLE] = {6, 1, 0b0} +}; + +static int bit_m(DisasContext *ctx, int x) +{ + return df_extract_val(ctx, x, df_bit); +} + +static int bit_df(DisasContext *ctx, int x) +{ + return df_extract_df(ctx, x, df_bit); +} + static TCGv_i64 msa_wr_d[64]; void msa_translate_init(void) @@ -490,90 +530,39 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) return true; } -static void gen_msa_bit(DisasContext *ctx) +static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, + gen_helper_piiii *gen_msa_bit) { -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm = (ctx->opcode >> 16) & 0x7f; - uint32_t df = 0, m = 0; - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) == 0x00) { - m = dfm & 0x3f; - df = DF_DOUBLE; - } else if ((dfm & 0x60) == 0x40) { - m = dfm & 0x1f; - df = DF_WORD; - } else if ((dfm & 0x70) == 0x60) { - m = dfm & 0x0f; - df = DF_HALF; - } else if ((dfm & 0x78) == 0x70) { - m = dfm & 0x7; - df = DF_BYTE; - } else { - gen_reserved_instruction(ctx); - return; + if (a->df < 0) { + return false; } - tdf = tcg_const_i32(df); - tm = tcg_const_i32(m); - twd = tcg_const_i32(wd); - tws = tcg_const_i32(ws); - - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_bit(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->m)); + + return true; } +TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); +TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); +TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); +TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); +TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); +TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); +TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); +TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); +TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); +TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); +TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -2118,10 +2107,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_I8_02: gen_msa_i8(ctx); break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: From patchwork Thu Oct 28 21:08:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n9sm3728728wmq.6.2021.10.28.14.09.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 11/32] target/mips: Convert MSA SHF opcode to decodetree Date: Thu, 28 Oct 2021 23:08:22 +0200 Message-Id: <20211028210843.2120802-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- v3: - Renamed &msa_i8 -> &msa_i - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 36 +++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 3d6c6faf688..8e887f54ad5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -26,6 +26,7 @@ @bz ...... ... df:2 wt:5 sa:16 &msa_bz @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i +@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m @@ -38,6 +39,8 @@ BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz { + SHF 011110 .. ........ ..... ..... 000010 @i8_df + ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index cd86d6cc5c0..c776735f7c6 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -60,13 +60,10 @@ enum { /* I8 instruction */ OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B = (0x0 << 24) | OPC_MSA_I8_02, OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00, OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H = (0x1 << 24) | OPC_MSA_I8_02, OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00, OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W = (0x2 << 24) | OPC_MSA_I8_02, OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00, /* VEC/2R/2RF instruction */ @@ -463,20 +460,6 @@ static void gen_msa_i8(DisasContext *ctx) case OPC_BSELI_B: gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df = (ctx->opcode >> 24) & 0x3; - if (df == DF_DOUBLE) { - gen_reserved_instruction(ctx); - } else { - TCGv_i32 tdf = tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -488,6 +471,25 @@ static void gen_msa_i8(DisasContext *ctx) tcg_temp_free_i32(ti8); } +static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) +{ + if (a->df == DF_DOUBLE) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_shf_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; +} + static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, gen_helper_piiii *gen_msa_i5) { From patchwork Thu Oct 28 21:08:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p11sm8178667wmi.0.2021.10.28.14.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 12/32] target/mips: Convert MSA I8 instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:23 +0200 Message-Id: <20211028210843.2120802-13-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: - Renamed &msa_i8 -> &msa_i - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 8 ++++ target/mips/tcg/msa_translate.c | 75 +++++++++------------------------ 2 files changed, 27 insertions(+), 56 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 8e887f54ad5..24847599a05 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i +@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_i df=0 @ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldi @bit ...... ... ....... ws:5 wd:5 ...... &msa_bit df=%bit_df m=%bit_m @@ -39,6 +40,13 @@ BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz { + ANDI 011110 00 ........ ..... ..... 000000 @i8 + ORI 011110 01 ........ ..... ..... 000000 @i8 + NORI 011110 10 ........ ..... ..... 000000 @i8 + XORI 011110 11 ........ ..... ..... 000000 @i8 + BMNZI 011110 00 ........ ..... ..... 000001 @i8 + BMZI 011110 01 ........ ..... ..... 000001 @i8 + BSELI 011110 10 ........ ..... ..... 000001 @i8 SHF 011110 .. ........ ..... ..... 000010 @i8_df ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index c776735f7c6..8fc02bd5e24 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -27,9 +27,6 @@ static int bit_df(DisasContext *ctx, int x); #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { - OPC_MSA_I8_00 = 0x00 | OPC_MSA, - OPC_MSA_I8_01 = 0x01 | OPC_MSA, - OPC_MSA_I8_02 = 0x02 | OPC_MSA, OPC_MSA_3R_0D = 0x0D | OPC_MSA, OPC_MSA_3R_0E = 0x0E | OPC_MSA, OPC_MSA_3R_0F = 0x0F | OPC_MSA, @@ -57,15 +54,6 @@ enum { }; enum { - /* I8 instruction */ - OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01, - OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01, - OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01, - OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00, - /* VEC/2R/2RF instruction */ OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC, @@ -334,6 +322,7 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } +typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, @@ -427,50 +416,29 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); } -static void gen_msa_i8(DisasContext *ctx) +static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, + gen_helper_piii *gen_msa_i8) { -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 = (ctx->opcode >> 16) & 0xff; - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 ti8 = tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); + gen_msa_i8(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->sa)); + + return true; } +TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); +TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); +TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); +TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); +TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); +TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); +TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); + static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) { if (a->df == DF_DOUBLE) { @@ -2104,11 +2072,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) } switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: From patchwork Thu Oct 28 21:08:24 2021 Content-Type: text/plain; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id k15sm3974336wrx.13.2021.10.28.14.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 13/32] target/mips: Convert MSA load/store instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:24 +0200 Message-Id: <20211028210843.2120802-14-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert load/store instructions to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211027180730.1551932-14-f4bug@amsat.org> --- v3: - Renamed &msa_ldst -> &msa_i - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 4 ++ target/mips/tcg/msa_translate.c | 91 ++++++++++++--------------------- 2 files changed, 36 insertions(+), 59 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 24847599a05..0aeb83d5c5b 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -22,6 +22,7 @@ %bit_m 16:7 !function=bit_m @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -78,5 +79,8 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + LD 011110 .......... ..... ..... 1000 .. @ldst + ST 011110 .......... ..... ..... 1001 .. @ldst + MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 8fc02bd5e24..53cafe53f14 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -41,16 +41,6 @@ enum { OPC_MSA_3RF_1B = 0x1B | OPC_MSA, OPC_MSA_3RF_1C = 0x1C | OPC_MSA, OPC_MSA_VEC = 0x1E | OPC_MSA, - - /* MI10 instruction */ - OPC_LD_B = (0x20) | OPC_MSA, - OPC_LD_H = (0x21) | OPC_MSA, - OPC_LD_W = (0x22) | OPC_MSA, - OPC_LD_D = (0x23) | OPC_MSA, - OPC_ST_B = (0x24) | OPC_MSA, - OPC_ST_H = (0x25) | OPC_MSA, - OPC_ST_W = (0x26) | OPC_MSA, - OPC_ST_D = (0x27) | OPC_MSA, }; enum { @@ -322,9 +312,19 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } +typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); +#define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ + static gen_helper_p##TYPE * const NAME##_tab[4] = { \ + gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ + }; \ + TRANS(NAME, trans_func, NAME##_tab[a->df]) + +#define TRANS_DF_iv(NAME, trans_func, gen_func) \ + TRANS_DF_x(iv, NAME, trans_func, gen_func) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -2094,55 +2094,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_VEC: gen_msa_vec(ctx); break; - case OPC_LD_B: - case OPC_LD_H: - case OPC_LD_W: - case OPC_LD_D: - case OPC_ST_B: - case OPC_ST_H: - case OPC_ST_W: - case OPC_ST_D: - { - int32_t s10 = sextract32(ctx->opcode, 16, 10); - uint8_t rs = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - uint8_t df = (ctx->opcode >> 0) & 0x3; - - TCGv_i32 twd = tcg_const_i32(wd); - TCGv taddr = tcg_temp_new(); - gen_base_offset_addr(ctx, taddr, rs, s10 << df); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_LD_B: - gen_helper_msa_ld_b(cpu_env, twd, taddr); - break; - case OPC_LD_H: - gen_helper_msa_ld_h(cpu_env, twd, taddr); - break; - case OPC_LD_W: - gen_helper_msa_ld_w(cpu_env, twd, taddr); - break; - case OPC_LD_D: - gen_helper_msa_ld_d(cpu_env, twd, taddr); - break; - case OPC_ST_B: - gen_helper_msa_st_b(cpu_env, twd, taddr); - break; - case OPC_ST_H: - gen_helper_msa_st_h(cpu_env, twd, taddr); - break; - case OPC_ST_W: - gen_helper_msa_st_w(cpu_env, twd, taddr); - break; - case OPC_ST_D: - gen_helper_msa_st_d(cpu_env, twd, taddr); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free(taddr); - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -2152,6 +2103,28 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } +static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, + gen_helper_piv *gen_msa_ldst) +{ + TCGv taddr; + + if (!check_msa_enabled(ctx)) { + return true; + } + + taddr = tcg_temp_new(); + + gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); + gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); + + tcg_temp_free(taddr); + + return true; +} + +TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); +TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); + static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); From patchwork Thu Oct 28 21:08:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id k22sm4065224wrd.59.2021.10.28.14.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 14/32] target/mips: Convert MSA 2RF instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:25 +0200 Message-Id: <20211028210843.2120802-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: - Add plus_2(), extract DF in decoder - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 20 ++++++ target/mips/tcg/msa_translate.c | 118 +++++++++----------------------- 2 files changed, 53 insertions(+), 85 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0aeb83d5c5b..33288b50355 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -13,6 +13,7 @@ &r rs rt rd sa +&msa_r df wd ws wt &msa_bz df wt sa &msa_ldi df wd sa &msa_i df wd ws sa @@ -20,11 +21,13 @@ %bit_df 16:7 !function=bit_df %bit_m 16:7 !function=bit_m +%2r_df_w 16:1 !function=plus_2 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -79,6 +82,23 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + FCLASS 011110 110010000 . ..... ..... 011110 @2rf + FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf + FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf + FSQRT 011110 110010011 . ..... ..... 011110 @2rf + FRSQRT 011110 110010100 . ..... ..... 011110 @2rf + FRCP 011110 110010101 . ..... ..... 011110 @2rf + FRINT 011110 110010110 . ..... ..... 011110 @2rf + FLOG2 011110 110010111 . ..... ..... 011110 @2rf + FEXUPL 011110 110011000 . ..... ..... 011110 @2rf + FEXUPR 011110 110011001 . ..... ..... 011110 @2rf + FFQL 011110 110011010 . ..... ..... 011110 @2rf + FFQR 011110 110011011 . ..... ..... 011110 @2rf + FTINT_S 011110 110011100 . ..... ..... 011110 @2rf + FTINT_U 011110 110011101 . ..... ..... 011110 @2rf + FFINT_S 011110 110011110 . ..... ..... 011110 @2rf + FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 53cafe53f14..477eba49ac4 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); +static inline int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" @@ -44,7 +49,7 @@ enum { }; enum { - /* VEC/2R/2RF instruction */ + /* VEC/2R instruction */ OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC, OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC, OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC, @@ -54,7 +59,6 @@ enum { OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC, OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC, /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */ OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R, @@ -62,24 +66,6 @@ enum { OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R, - /* 2RF instruction df(bit 16) = _w, _d */ - OPC_FCLASS_df = (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df = (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df = (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df = (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df = (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df = (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df = (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df = (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df = (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df = (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df = (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df = (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df = (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df = (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df = (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df = (0x0F << 17) | OPC_MSA_2RF, - /* 3R instruction df(bits 22..21) = _b, _h, _w, d */ OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E, @@ -1928,73 +1914,38 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } -static void gen_msa_2rf(DisasContext *ctx) +static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_2rf) { -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - uint8_t df = (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; + if (!check_msa_enabled(ctx)) { + return true; } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_2rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; } +TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); +TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); +TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); +TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); +TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); +TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); +TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); +TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); +TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); +TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); +TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); +TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); +TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); +TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); +TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); + static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) @@ -2053,9 +2004,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_MSA_2R: gen_msa_2r(ctx); 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id i13sm3972363wmq.41.2021.10.28.14.09.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:09:58 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 15/32] target/mips: Convert MSA FILL opcode to decodetree Date: Thu, 28 Oct 2021 23:08:26 +0200 Message-Id: <20211028210843.2120802-16-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: - Return false if BITS != 64 && DF_DOUBLE instead of raising exception --- target/mips/tcg/msa.decode | 2 ++ target/mips/tcg/msa_translate.c | 31 +++++++++++++++++++------------ 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 33288b50355..bcbc573deec 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @@ -82,6 +83,7 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + FILL 011110 11000000 .. ..... ..... 011110 @2r FCLASS 011110 110010000 . ..... ..... 011110 @2rf FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 477eba49ac4..1894d779196 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -61,7 +61,6 @@ enum { OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC, /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */ - OPC_FILL_df = (0x00 << 18) | OPC_MSA_2R, OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R, OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R, OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R, @@ -1845,17 +1844,6 @@ static void gen_msa_2r(DisasContext *ctx) TCGv_i32 tws = tcg_const_i32(ws); switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df == DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df), - twd, tws); /* trs */ - break; case OPC_NLOC_df: switch (df) { case DF_BYTE: @@ -1914,6 +1902,25 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(tws); } +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) +{ + if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { + /* Double format valid only for MIPS64 */ + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_fill_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; +} + static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_2rf) { From patchwork Thu Oct 28 21:08:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n8sm2998426wrp.95.2021.10.28.14.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 16/32] target/mips: Convert MSA 2R instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:27 +0200 Message-Id: <20211028210843.2120802-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 2-register operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211027180730.1551932-17-f4bug@amsat.org> --- v3: - Call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 3 ++ target/mips/tcg/msa_translate.c | 89 ++++++--------------------------- 2 files changed, 18 insertions(+), 74 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bcbc573deec..b6ac80560f6 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -84,6 +84,9 @@ BNZ 010001 111 .. ..... ................ @bz SRLRI 011110 011 ....... ..... ..... 001010 @bit FILL 011110 11000000 .. ..... ..... 011110 @2r + PCNT 011110 11000001 .. ..... ..... 011110 @2r + NLOC 011110 11000010 .. ..... ..... 011110 @2r + NLZC 011110 11000011 .. ..... ..... 011110 @2r FCLASS 011110 110010000 . ..... ..... 011110 @2rf FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 1894d779196..f0077f7e54c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -58,13 +58,6 @@ enum { OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC, OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC, - OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC, - - /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */ - OPC_PCNT_df = (0x01 << 18) | OPC_MSA_2R, - OPC_NLOC_df = (0x02 << 18) | OPC_MSA_2R, - OPC_NLZC_df = (0x03 << 18) | OPC_MSA_2R, - /* 3R instruction df(bits 22..21) = _b, _h, _w, d */ OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E, @@ -298,6 +291,7 @@ static inline bool check_msa_enabled(DisasContext *ctx) } typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); +typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); @@ -310,6 +304,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); #define TRANS_DF_iv(NAME, trans_func, gen_func) \ TRANS_DF_x(iv, NAME, trans_func, gen_func) +#define TRANS_DF_ii(NAME, trans_func, gen_func) \ + TRANS_DF_x(ii, NAME, trans_func, gen_func) + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -1833,75 +1830,22 @@ static void gen_msa_3rf(DisasContext *ctx) tcg_temp_free_i32(twt); } -static void gen_msa_2r(DisasContext *ctx) +static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, + gen_helper_pii *gen_msa_2r) { -#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0x7 << 18))) - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - uint8_t df = (ctx->opcode >> 16) & 0x3; - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - - switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_NLOC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nloc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nloc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nloc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nloc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_NLZC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nlzc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nlzc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nlzc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nlzc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_PCNT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pcnt_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_pcnt_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_pcnt_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_pcnt_d(cpu_env, twd, tws); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); + gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); + + return true; } +TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); +TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); +TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); + static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) { if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { @@ -2008,9 +1952,6 @@ static void gen_msa_vec(DisasContext *ctx) case OPC_BSEL_V: gen_msa_vec_v(ctx); break; - case OPC_MSA_2R: - gen_msa_2r(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); From patchwork Thu Oct 28 21:08:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547692 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id f133sm1469210wmf.31.2021.10.28.14.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 17/32] target/mips: Convert MSA VEC instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:28 +0200 Message-Id: <20211028210843.2120802-18-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: - Do not add trans_msa_vec(), directly use trans_msa_3r() --- target/mips/tcg/msa.decode | 8 +++ target/mips/tcg/msa_translate.c | 98 ++++++++------------------------- 2 files changed, 31 insertions(+), 75 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index b6ac80560f6..afcb868aade 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -27,6 +27,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -83,6 +84,13 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + AND_V 011110 00000 ..... ..... ..... 011110 @vec + OR_V 011110 00001 ..... ..... ..... 011110 @vec + NOR_V 011110 00010 ..... ..... ..... 011110 @vec + XOR_V 011110 00011 ..... ..... ..... 011110 @vec + BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec + BMZ_V 011110 00101 ..... ..... ..... 011110 @vec + BSEL_V 011110 00110 ..... ..... ..... 011110 @vec FILL 011110 11000000 .. ..... ..... 011110 @2r PCNT 011110 11000001 .. ..... ..... 011110 @2r NLOC 011110 11000010 .. ..... ..... 011110 @2r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index f0077f7e54c..f063a08631c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,19 +45,9 @@ enum { OPC_MSA_3RF_1A = 0x1A | OPC_MSA, OPC_MSA_3RF_1B = 0x1B | OPC_MSA, OPC_MSA_3RF_1C = 0x1C | OPC_MSA, - OPC_MSA_VEC = 0x1E | OPC_MSA, }; enum { - /* VEC/2R instruction */ - OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V = (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V = (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V = (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V = (0x06 << 21) | OPC_MSA_VEC, - /* 3R instruction df(bits 22..21) = _b, _h, _w, d */ OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D, OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E, @@ -515,6 +505,29 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); +static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, + gen_helper_piii *gen_msa_3r) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3r(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + +TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); +TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); +TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); +TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); +TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); +TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); +TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1897,68 +1910,6 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt = (ctx->opcode >> 16) & 0x1f; - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} - static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode = ctx->opcode; @@ -1987,9 +1938,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_3RF_1C: gen_msa_3rf(ctx); break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); From patchwork Thu Oct 28 21:08:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=amRyzE2Z; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id z5sm8918345wmp.26.2021.10.28.14.10.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Date: Thu, 28 Oct 2021 23:08:29 +0200 Message-Id: <20211028210843.2120802-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v3: - Add plus_1(), extract DF in decoder - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 9 +++++ target/mips/tcg/msa_translate.c | 68 ++++++++++++++------------------- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index afcb868aade..f90b2d21c92 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -22,6 +22,7 @@ %bit_df 16:7 !function=bit_df %bit_m 16:7 !function=bit_m %2r_df_w 16:1 !function=plus_2 +%3r_df_h 21:1 !function=plus_1 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @@ -30,6 +31,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w +@3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -84,6 +86,13 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h + MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h + MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h + MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h + MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h + MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h + AND_V 011110 00000 ..... ..... ..... 011110 @vec OR_V 011110 00001 ..... ..... ..... 011110 @vec NOR_V 011110 00010 ..... ..... ..... 011110 @vec diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index f063a08631c..955e4ad0457 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -20,6 +20,11 @@ static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); +static inline int plus_1(DisasContext *s, int x) +{ + return x + 1; +} + static inline int plus_2(DisasContext *s, int x) { return x + 2; @@ -138,12 +143,9 @@ enum { OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C, OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A, OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C, OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A, OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C, OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C, OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A, OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B, OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A, @@ -157,13 +159,10 @@ enum { OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C, OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A, OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C, OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A, OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C, OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A, OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C, OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A, OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B, }; @@ -505,6 +504,22 @@ TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); +static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + gen_helper_piiii *gen_msa_3rf) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_3rf(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->wt)); + + return true; +} + static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_3r) { @@ -1680,6 +1695,13 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } +TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); +TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); +TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); +TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); +TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); +TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); + static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -1691,22 +1713,8 @@ static void gen_msa_3rf(DisasContext *ctx) TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); TCGv_i32 twt = tcg_const_i32(wt); - TCGv_i32 tdf; - /* adjust df value for floating-point instruction */ - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_MUL_Q_df: - case OPC_MADD_Q_df: - case OPC_MSUB_Q_df: - case OPC_MULR_Q_df: - case OPC_MADDR_Q_df: - case OPC_MSUBR_Q_df: - tdf = tcg_constant_i32(DF_HALF + df); - break; - default: - tdf = tcg_constant_i32(DF_WORD + df); - break; - } + TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df); switch (MASK_MSA_3RF(ctx->opcode)) { case OPC_FCAF_df: @@ -1748,24 +1756,15 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMADD_df: gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MUL_Q_df: - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULT_df: gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMSUB_df: gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADD_Q_df: - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCLE_df: gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUB_Q_df: - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FCULE_df: gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); break; @@ -1805,27 +1804,18 @@ static void gen_msa_3rf(DisasContext *ctx) case OPC_FMIN_df: gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MULR_Q_df: - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULT_df: gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMIN_A_df: gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MADDR_Q_df: - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSLE_df: gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); break; case OPC_FMAX_df: gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUBR_Q_df: - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_FSULE_df: gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); break; From patchwork Thu Oct 28 21:08:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547704 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Hxn4/v8M; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJcW35rYz9sfG for ; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id n9sm3729942wmq.6.2021.10.28.14.10.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Date: Thu, 28 Oct 2021 23:08:30 +0200 Message-Id: <20211028210843.2120802-20-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: Extract DF in decoder --- target/mips/tcg/msa.decode | 39 ++++++ target/mips/tcg/msa_translate.c | 213 ++++++-------------------------- 2 files changed, 76 insertions(+), 176 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index f90b2d21c92..1d6ada4c142 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -23,6 +23,7 @@ %bit_m 16:7 !function=bit_m %2r_df_w 16:1 !function=plus_2 %3r_df_h 21:1 !function=plus_1 +%3r_df_w 21:1 !function=plus_2 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @@ -32,6 +33,7 @@ @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h +@3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i @i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_i @@ -86,9 +88,46 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w + FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w + FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w + FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w + FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w + FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w + FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w + FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w + FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w + FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w + FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w + FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w + FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w + FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w + FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w + FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w + + FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w + FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w + FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w + FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w + FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w + FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w + FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w + FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w + FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w + FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w + FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w + FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w + FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w + + FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w + FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w + FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h + FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w + FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w + FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 955e4ad0457..fbaf9f622f3 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -47,9 +47,6 @@ enum { OPC_MSA_3R_14 = 0x14 | OPC_MSA, OPC_MSA_3R_15 = 0x15 | OPC_MSA, OPC_MSA_ELM = 0x19 | OPC_MSA, - OPC_MSA_3RF_1A = 0x1A | OPC_MSA, - OPC_MSA_3RF_1B = 0x1B | OPC_MSA, - OPC_MSA_3RF_1C = 0x1C | OPC_MSA, }; enum { @@ -128,43 +125,6 @@ enum { OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, - - /* 3RF instruction _df(bit 21) = _w, _d */ - OPC_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A, - OPC_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B, - OPC_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A, - OPC_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B, - OPC_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C, - OPC_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A, - OPC_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B, - OPC_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C, - OPC_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A, - OPC_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B, - OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C, - OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A, - OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A, - OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A, - OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B, - OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A, - OPC_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B, - OPC_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A, - OPC_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C, - OPC_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A, - OPC_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B, - OPC_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C, - OPC_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A, - OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C, - OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B, - OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B, - OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B, - OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B, }; static const char msaregnames[][6] = { @@ -1695,144 +1655,50 @@ static void gen_msa_elm(DisasContext *ctx) gen_msa_elm_df(ctx, df, n); } +TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); +TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); +TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); +TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); +TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); +TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); +TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); +TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); +TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); +TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); +TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); +TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); +TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); +TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); +TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); +TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); + +TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); +TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); +TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); +TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); +TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); +TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); +TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); +TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); +TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); +TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); +TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); +TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); +TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); + +TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); +TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); +TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); +TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); +TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); +TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); -static void gen_msa_3rf(DisasContext *ctx) -{ -#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t df = (ctx->opcode >> 21) & 0x1; - uint8_t wt = (ctx->opcode >> 16) & 0x1f; - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df); - - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_FCAF_df: - gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FADD_df: - gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUN_df: - gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUB_df: - gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCOR_df: - gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCEQ_df: - gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMUL_df: - gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUNE_df: - gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUEQ_df: - gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FDIV_df: - gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCNE_df: - gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLT_df: - gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMADD_df: - gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULT_df: - gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMSUB_df: - gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLE_df: - gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULE_df: - gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXP2_df: - gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSAF_df: - gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXDO_df: - gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUN_df: - gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSOR_df: - gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSEQ_df: - gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FTQ_df: - gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUNE_df: - gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUEQ_df: - gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSNE_df: - gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLT_df: - gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_df: - gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULT_df: - gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_A_df: - gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLE_df: - gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_df: - gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULE_df: - gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_A_df: - gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, gen_helper_pii *gen_msa_2r) { @@ -1923,11 +1789,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) case OPC_MSA_ELM: gen_msa_elm(ctx); break; - case OPC_MSA_3RF_1A: - case OPC_MSA_3RF_1B: - case OPC_MSA_3RF_1C: - gen_msa_3rf(ctx); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); From patchwork Thu Oct 28 21:08:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=iLmf9vVN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgJTK66p9z9sRN for ; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id o2sm4130780wrg.1.2021.10.28.14.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Date: Thu, 28 Oct 2021 23:08:31 +0200 Message-Id: <20211028210843.2120802-21-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v3: - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 6 ++++++ target/mips/tcg/msa_translate.c | 17 +++++------------ 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 1d6ada4c142..4b14acce26f 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -32,6 +32,7 @@ @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w +@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h @3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w @u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i @@ -88,6 +89,11 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + SLD 011110 000 .. ..... ..... ..... 010100 @3r + SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + + VSHF 011110 000 .. ..... ..... ..... 010101 @3r + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index fbaf9f622f3..6738a2b8cd7 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -58,15 +58,12 @@ enum { OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12, OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15, OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12, OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14, OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E, @@ -503,6 +500,11 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); +TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); +TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); + +TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); + static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) @@ -1253,12 +1255,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBV_df: switch (df) { case DF_BYTE: @@ -1291,9 +1287,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUS_U_df: switch (df) { case DF_BYTE: From patchwork Thu Oct 28 21:08:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id f7sm4652090wmg.14.2021.10.28.14.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Date: Thu, 28 Oct 2021 23:08:32 +0200 Message-Id: <20211028210843.2120802-22-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register operations to decodetree. Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v3: - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 11 ++ target/mips/tcg/msa_translate.c | 182 +++++--------------------------- 2 files changed, 35 insertions(+), 158 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 4b14acce26f..0e2f474cde6 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,10 +89,21 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r + DOTP_U 011110 001.. ..... ..... ..... 010011 @3r + DPADD_S 011110 010.. ..... ..... ..... 010011 @3r + DPADD_U 011110 011.. ..... ..... ..... 010011 @3r + DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r + DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r + SLD 011110 000 .. ..... ..... ..... 010100 @3r SPLAT 011110 001 .. ..... ..... ..... 010100 @3r VSHF 011110 000 .. ..... ..... ..... 010101 @3r + HADD_S 011110 100.. ..... ..... ..... 010101 @3r + HADD_U 011110 101.. ..... ..... ..... 010101 @3r + HSUB_S 011110 110.. ..... ..... ..... 010101 @3r + HSUB_U 011110 111.. ..... ..... ..... 010101 @3r FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 6738a2b8cd7..b65474261f0 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -57,13 +57,11 @@ enum { OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10, OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11, OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13, OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D, OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E, OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10, OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11, OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13, OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15, OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D, OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E, @@ -71,7 +69,6 @@ enum { OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10, OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11, OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13, OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14, OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15, OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D, @@ -79,7 +76,6 @@ enum { OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F, OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10, OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13, OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14, OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D, OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E, @@ -87,30 +83,24 @@ enum { OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10, OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11, OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13, OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15, OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D, OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E, OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F, OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10, OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13, OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15, OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15, OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12, OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15, /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, @@ -253,6 +243,15 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); #define TRANS_DF_ii(NAME, trans_func, gen_func) \ TRANS_DF_x(ii, NAME, trans_func, gen_func) +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ + static gen_helper_piii * const NAME##_tab[4] = { \ + NULL, gen_func##_h, gen_func##_w, gen_func##_d \ + }; \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { \ + return trans_func(ctx, a, NAME##_tab[a->df]); \ + } + static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, TCGCond cond) { @@ -480,6 +479,10 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, gen_helper_piii *gen_msa_3r) { + if (!gen_msa_3r) { + return false; + } + if (!check_msa_enabled(ctx)) { return true; } @@ -500,10 +503,21 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); +TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); +TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); +TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); +TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); +TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); +TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); + TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); +TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); +TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); +TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); +TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); static void gen_msa_3r(DisasContext *ctx) { @@ -1319,154 +1333,6 @@ static void gen_msa_3r(DisasContext *ctx) break; } break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df == DF_BYTE) { - gen_reserved_instruction(ctx); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); From patchwork Thu Oct 28 21:08:33 2021 Content-Type: text/plain; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id k14sm1957624wms.21.2021.10.28.14.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Date: Thu, 28 Oct 2021 23:08:33 +0200 Message-Id: <20211028210843.2120802-23-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 3 +++ target/mips/tcg/msa_translate.c | 40 +++++---------------------------- 2 files changed, 9 insertions(+), 34 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0e2f474cde6..f2bacbaea86 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + BINSL 011110 110.. ..... ..... ..... 001101 @3r + BINSR 011110 111.. ..... ..... ..... 001101 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index b65474261f0..23d7ab6fd5b 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -91,12 +91,10 @@ enum { OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11, OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12, OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14, - OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D, OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E, OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10, OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12, OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14, - OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D, OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E, OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10, OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12, @@ -243,6 +241,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); #define TRANS_DF_ii(NAME, trans_func, gen_func) \ TRANS_DF_x(ii, NAME, trans_func, gen_func) +#define TRANS_DF_iii(NAME, trans_func, gen_func) \ + TRANS_DF_x(iii, NAME, trans_func, gen_func) + #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ static gen_helper_piii * const NAME##_tab[4] = { \ NULL, gen_func##_h, gen_func##_w, gen_func##_d \ @@ -503,6 +504,9 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); +TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); +TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); + TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); @@ -533,38 +537,6 @@ static void gen_msa_3r(DisasContext *ctx) TCGv_i32 twt = tcg_const_i32(wt); switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; case OPC_BCLR_df: switch (df) { case DF_BYTE: From patchwork Thu Oct 28 21:08:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id f133sm1469989wmf.31.2021.10.28.14.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Date: Thu, 28 Oct 2021 23:08:34 +0200 Message-Id: <20211028210843.2120802-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert 3-register operations to decodetree. Reviewed-by: Richard Henderson Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 53 ++ target/mips/tcg/msa_translate.c | 916 ++------------------------------ 2 files changed, 106 insertions(+), 863 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index f2bacbaea86..391261109a5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -89,9 +89,54 @@ BNZ 010001 111 .. ..... ................ @bz SRARI 011110 010 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit + SLL 011110 000.. ..... ..... ..... 001101 @3r + SRA 011110 001.. ..... ..... ..... 001101 @3r + SRL 011110 010.. ..... ..... ..... 001101 @3r + BCLR 011110 011.. ..... ..... ..... 001101 @3r + BSET 011110 100.. ..... ..... ..... 001101 @3r + BNEG 011110 101.. ..... ..... ..... 001101 @3r BINSL 011110 110.. ..... ..... ..... 001101 @3r BINSR 011110 111.. ..... ..... ..... 001101 @3r + ADDV 011110 000.. ..... ..... ..... 001110 @3r + SUBV 011110 001.. ..... ..... ..... 001110 @3r + MAX_S 011110 010.. ..... ..... ..... 001110 @3r + MAX_U 011110 011.. ..... ..... ..... 001110 @3r + MIN_S 011110 100.. ..... ..... ..... 001110 @3r + MIN_U 011110 101.. ..... ..... ..... 001110 @3r + MAX_A 011110 110.. ..... ..... ..... 001110 @3r + MIN_A 011110 111.. ..... ..... ..... 001110 @3r + + CEQ 011110 000.. ..... ..... ..... 001111 @3r + CLT_S 011110 010.. ..... ..... ..... 001111 @3r + CLT_U 011110 011.. ..... ..... ..... 001111 @3r + CLE_S 011110 100.. ..... ..... ..... 001111 @3r + CLE_U 011110 101.. ..... ..... ..... 001111 @3r + + ADD_A 011110 000.. ..... ..... ..... 010000 @3r + ADDS_A 011110 001.. ..... ..... ..... 010000 @3r + ADDS_S 011110 010.. ..... ..... ..... 010000 @3r + ADDS_U 011110 011.. ..... ..... ..... 010000 @3r + AVE_S 011110 100.. ..... ..... ..... 010000 @3r + AVE_U 011110 101.. ..... ..... ..... 010000 @3r + AVER_S 011110 110.. ..... ..... ..... 010000 @3r + AVER_U 011110 111.. ..... ..... ..... 010000 @3r + + SUBS_S 011110 000.. ..... ..... ..... 010001 @3r + SUBS_U 011110 001.. ..... ..... ..... 010001 @3r + SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r + SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r + ASUB_S 011110 100.. ..... ..... ..... 010001 @3r + ASUB_U 011110 101.. ..... ..... ..... 010001 @3r + + MULV 011110 000.. ..... ..... ..... 010010 @3r + MADDV 011110 001.. ..... ..... ..... 010010 @3r + MSUBV 011110 010.. ..... ..... ..... 010010 @3r + DIV_S 011110 100.. ..... ..... ..... 010010 @3r + DIV_U 011110 101.. ..... ..... ..... 010010 @3r + MOD_S 011110 110.. ..... ..... ..... 010010 @3r + MOD_U 011110 111.. ..... ..... ..... 010010 @3r + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r @@ -101,8 +146,16 @@ BNZ 010001 111 .. ..... ................ @bz SLD 011110 000 .. ..... ..... ..... 010100 @3r SPLAT 011110 001 .. ..... ..... ..... 010100 @3r + PCKEV 011110 010 .. ..... ..... ..... 010100 @3r + PCKOD 011110 011 .. ..... ..... ..... 010100 @3r + ILVL 011110 100 .. ..... ..... ..... 010100 @3r + ILVR 011110 101 .. ..... ..... ..... 010100 @3r + ILVEV 011110 110 .. ..... ..... ..... 010100 @3r + ILVOD 011110 111 .. ..... ..... ..... 010100 @3r VSHF 011110 000 .. ..... ..... ..... 010101 @3r + SRAR 011110 001 .. ..... ..... ..... 010101 @3r + SRLR 011110 010 .. ..... ..... ..... 010101 @3r HADD_S 011110 100.. ..... ..... ..... 010101 @3r HADD_U 011110 101.. ..... ..... ..... 010101 @3r HSUB_S 011110 110.. ..... ..... ..... 010101 @3r diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 23d7ab6fd5b..b0aae11b06c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -37,69 +37,10 @@ static inline int plus_2(DisasContext *s, int x) #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { - OPC_MSA_3R_0D = 0x0D | OPC_MSA, - OPC_MSA_3R_0E = 0x0E | OPC_MSA, - OPC_MSA_3R_0F = 0x0F | OPC_MSA, - OPC_MSA_3R_10 = 0x10 | OPC_MSA, - OPC_MSA_3R_11 = 0x11 | OPC_MSA, - OPC_MSA_3R_12 = 0x12 | OPC_MSA, - OPC_MSA_3R_13 = 0x13 | OPC_MSA, - OPC_MSA_3R_14 = 0x14 | OPC_MSA, - OPC_MSA_3R_15 = 0x15 | OPC_MSA, OPC_MSA_ELM = 0x19 | OPC_MSA, }; enum { - /* 3R instruction df(bits 22..21) = _b, _h, _w, d */ - OPC_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D, - OPC_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E, - OPC_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F, - OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10, - OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11, - OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12, - OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D, - OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E, - OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10, - OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11, - OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12, - OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15, - OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D, - OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E, - OPC_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10, - OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11, - OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12, - OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14, - OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15, - OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D, - OPC_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E, - OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10, - OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11, - OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14, - OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D, - OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E, - OPC_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F, - OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10, - OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11, - OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12, - OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14, - OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D, - OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E, - OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F, - OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10, - OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11, - OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12, - OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14, - OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E, - OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10, - OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12, - OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14, - OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E, - OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10, - OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12, - OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14, - /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, @@ -504,9 +445,54 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); +TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); +TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); +TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); +TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); +TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); +TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); +TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); +TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); +TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); +TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); +TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); +TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); +TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); +TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); + +TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); +TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); +TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); +TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); +TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); + +TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); +TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); +TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); +TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); +TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); +TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); +TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); +TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); + +TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); +TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); +TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); +TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); +TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); +TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); + +TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); +TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); +TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); +TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); +TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); +TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); +TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); + TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); @@ -516,806 +502,21 @@ TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); +TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); +TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); +TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); +TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); +TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); +TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); +TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); +TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); -static void gen_msa_3r(DisasContext *ctx) -{ -#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df = (ctx->opcode >> 21) & 0x3; - uint8_t wt = (ctx->opcode >> 16) & 0x1f; - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf = tcg_const_i32(df); - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); - - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BCLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BNEG_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BSET_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bset_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bset_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bset_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bset_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADD_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_addv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_addv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_addv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_addv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CEQ_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MSUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sll_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sll_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sll_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sll_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRA_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sra_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sra_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sra_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sra_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRAR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srar_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srar_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srar_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srar_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MULV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUU_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) @@ -1606,17 +807,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) } switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_3R_0D: - case OPC_MSA_3R_0E: - case OPC_MSA_3R_0F: - case OPC_MSA_3R_10: - case OPC_MSA_3R_11: - case OPC_MSA_3R_12: - case OPC_MSA_3R_13: - case OPC_MSA_3R_14: - case OPC_MSA_3R_15: - gen_msa_3r(ctx); - break; case OPC_MSA_ELM: gen_msa_elm(ctx); break; From patchwork Thu Oct 28 21:08:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id s8sm4081250wrr.15.2021.10.28.14.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 24/32] target/mips: Convert MSA ELM instruction format to decodetree Date: Thu, 28 Oct 2021 23:08:35 +0200 Message-Id: <20211028210843.2120802-25-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert instructions with an immediate element index and data format df/n to decodetree. Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211027180730.1551932-26-f4bug@amsat.org> --- v3: - Remove TRANS_MSA(), call check_msa_enabled in trans_X() --- target/mips/tcg/msa.decode | 8 +++++ target/mips/tcg/msa_translate.c | 57 +++++++++++++++++++++++++-------- 2 files changed, 52 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 391261109a5..bf014524eed 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -18,7 +18,10 @@ &msa_ldi df wd sa &msa_i df wd ws sa &msa_bit df wd ws m +&msa_elm_df df wd ws n +%elm_df 16:6 !function=elm_df +%elm_n 16:6 !function=elm_n %bit_df 16:7 !function=bit_df %bit_m 16:7 !function=bit_m %2r_df_w 16:1 !function=plus_2 @@ -29,6 +32,7 @@ @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz +@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @@ -161,6 +165,10 @@ BNZ 010001 111 .. ..... ................ @bz HSUB_S 011110 110.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + INSVE 011110 0101 ...... ..... ..... 011001 @elm_df + FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index b0aae11b06c..af73b385019 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -17,6 +17,8 @@ #include "fpu_helper.h" #include "internal.h" +static int elm_n(DisasContext *ctx, int x); +static int elm_df(DisasContext *ctx, int x); static int bit_m(DisasContext *ctx, int x); static int bit_df(DisasContext *ctx, int x); @@ -42,15 +44,12 @@ enum { enum { /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ - OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; static const char msaregnames[][6] = { @@ -107,6 +106,24 @@ static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) return -1; } +static const struct dfe df_elm[] = { + /* Table 3.26 ELM Instruction Format */ + [DF_BYTE] = {4, 2, 0b00}, + [DF_HALF] = {3, 3, 0b100}, + [DF_WORD] = {2, 4, 0b1100}, + [DF_DOUBLE] = {1, 5, 0b11100} +}; + +static int elm_n(DisasContext *ctx, int x) +{ + return df_extract_val(ctx, x, df_elm); +} + +static int elm_df(DisasContext *ctx, int x) +{ + return df_extract_df(ctx, x, df_elm); +} + static const struct dfe df_bit[] = { /* Table 3.28 BIT Instruction Format */ [DF_BYTE] = {3, 4, 0b1110}, @@ -549,6 +566,30 @@ static void gen_msa_elm_3e(DisasContext *ctx) tcg_temp_free_i32(tsr); } +static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, + gen_helper_piiii *gen_msa_elm_df) +{ + if (a->df < 0) { + return false; + } + + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_msa_elm_df(cpu_env, + tcg_constant_i32(a->df), + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->n)); + + return true; +} + +TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); +TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); +TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); + static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -558,18 +599,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) TCGv_i32 tws = tcg_const_i32(ws); TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tn = tcg_const_i32(n); - TCGv_i32 tdf = tcg_constant_i32(df); switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; case OPC_COPY_S_df: case OPC_COPY_U_df: case OPC_INSERT_df: From patchwork Thu Oct 28 21:08:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=as+0xg7y; dkim-atps=neutral Authentication-Results: ozlabs.org; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id m34sm2627378wms.25.2021.10.28.14.10.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 25/32] target/mips: Convert MSA COPY_U opcode to decodetree Date: Thu, 28 Oct 2021 23:08:36 +0200 Message-Id: <20211028210843.2120802-26-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree. Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v2: Add NULL_IF_TARGET_MIPS32() macro, use array of 4 functions --- target/mips/tcg/msa.decode | 1 + target/mips/tcg/msa_translate.c | 66 ++++++++++++++++++++------------- 2 files changed, 41 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bf014524eed..0e166a4e61d 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,6 +167,7 @@ BNZ 010001 111 .. ..... ................ @bz SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index af73b385019..eca38557769 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -48,7 +48,6 @@ enum { OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; @@ -590,6 +589,46 @@ TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); +static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, + gen_helper_piii * const gen_msa_elm[4]) +{ + if (a->df < 0 || !gen_msa_elm[a->df]) { + return false; + } + + if (check_msa_enabled(ctx)) { + return true; + } + + if (a->wd == 0) { + /* Treat as NOP. */ + return true; + } + + gen_msa_elm[a->df](cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws), + tcg_constant_i32(a->n)); + + return true; +} + +#if defined(TARGET_MIPS64) +#define NULL_IF_MIPS32(function) function +#else +#define NULL_IF_MIPS32(function) NULL +#endif + +static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) +{ + static gen_helper_piii * const gen_msa_copy_u[4] = { + gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, + NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL + }; + + return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); +} + static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) @@ -602,7 +641,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: - case OPC_COPY_U_df: case OPC_INSERT_df: #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ @@ -610,11 +648,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) gen_reserved_instruction(ctx); break; } - if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) && - (df == DF_WORD)) { - gen_reserved_instruction(ctx); - break; - } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -633,25 +666,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) case DF_DOUBLE: gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); break; -#endif - default: - assert(0); - } - } - break; - case OPC_COPY_U_df: - if (likely(wd != 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_WORD: - gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); - break; #endif default: assert(0); From patchwork Thu Oct 28 21:08:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=BZwa5faZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgK752JTnz9sRN for ; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id l5sm4025724wru.24.2021.10.28.14.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree Date: Thu, 28 Oct 2021 23:08:37 +0200 Message-Id: <20211028210843.2120802-27-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 2 + target/mips/tcg/msa_translate.c | 103 +++++--------------------------- 2 files changed, 18 insertions(+), 87 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 0e166a4e61d..9aac6808fc5 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,7 +167,9 @@ BNZ 010001 111 .. ..... ................ @bz SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df + INSERT 011110 0100 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index eca38557769..e10dd5e6ef8 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -46,9 +46,7 @@ enum { /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, }; static const char msaregnames[][6] = { @@ -629,98 +627,31 @@ static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); } -static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) +static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) { -#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t ws = (ctx->opcode >> 11) & 0x1f; - uint8_t wd = (ctx->opcode >> 6) & 0x1f; + static gen_helper_piii * const gen_msa_copy_s[4] = { + gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, + gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) + }; - TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twd = tcg_const_i32(wd); - TCGv_i32 tn = tcg_const_i32(n); + return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); +} - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - case OPC_INSERT_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df == DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - if (likely(wd != 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_INSERT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_insert_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_insert_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_insert_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_insert_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(tn); +static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) +{ + static gen_helper_piii * const gen_msa_insert[4] = { + gen_helper_msa_insert_b, gen_helper_msa_insert_h, + gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) + }; + + return trans_msa_elm_fn(ctx, a, gen_msa_insert); } static void gen_msa_elm(DisasContext *ctx) { uint8_t dfn = (ctx->opcode >> 16) & 0x3f; - uint32_t df = 0, n = 0; - if ((dfn & 0x30) == 0x00) { - n = dfn & 0x0f; - df = DF_BYTE; - } else if ((dfn & 0x38) == 0x20) { - n = dfn & 0x07; - df = DF_HALF; - } else if ((dfn & 0x3c) == 0x30) { - n = dfn & 0x03; - df = DF_WORD; - } else if ((dfn & 0x3e) == 0x38) { - n = dfn & 0x01; - df = DF_DOUBLE; - } else if (dfn == 0x3E) { + if (dfn == 0x3E) { /* CTCMSA, CFCMSA, MOVE.V */ gen_msa_elm_3e(ctx); return; @@ -728,8 +659,6 @@ static void gen_msa_elm(DisasContext *ctx) gen_reserved_instruction(ctx); return; } - - gen_msa_elm_df(ctx, df, n); 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id r1sm8006053wmr.36.2021.10.28.14.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:10:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 27/32] target/mips: Convert MSA MOVE.V opcode to decodetree Date: Thu, 28 Oct 2021 23:08:38 +0200 Message-Id: <20211028210843.2120802-28-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the MOVE.V opcode (Vector Move) to decodetree. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 7 ++++++- target/mips/tcg/msa_translate.c | 19 ++++++++++++++----- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 9aac6808fc5..d1b6a63b526 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -19,6 +19,7 @@ &msa_i df wd ws sa &msa_bit df wd ws m &msa_elm_df df wd ws n +&msa_elm wd ws %elm_df 16:6 !function=elm_df %elm_n 16:6 !function=elm_n @@ -33,6 +34,7 @@ @bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 @bz ...... ... df:2 wt:5 sa:16 &msa_bz @elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n +@elm ...... .......... ws:5 wd:5 ...... &msa_elm @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 @2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0 @2rf ...... ......... . ws:5 wd:5 ...... &msa_r wt=0 df=%2r_df_w @@ -167,7 +169,10 @@ BNZ 010001 111 .. ..... ................ @bz SLDI 011110 0000 ...... ..... ..... 011001 @elm_df SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df - COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df + { + MOVE_V 011110 0010111110 ..... ..... 011001 @elm + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df + } COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df INSERT 011110 0100 ...... ..... ..... 011001 @elm_df INSVE 011110 0101 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index e10dd5e6ef8..1cc9cd8afa5 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -46,7 +46,6 @@ enum { /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, }; static const char msaregnames[][6] = { @@ -531,6 +530,19 @@ TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); +static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) +{ + if (!check_msa_enabled(ctx)) { + return true; + } + + gen_helper_msa_move_v(cpu_env, + tcg_constant_i32(a->wd), + tcg_constant_i32(a->ws)); + + return true; +} + static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) @@ -549,9 +561,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) gen_helper_msa_cfcmsa(telm, cpu_env, tsr); gen_store_gpr(telm, dest); break; - case OPC_MOVE_V: - gen_helper_msa_move_v(cpu_env, tdt, tsr); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -652,7 +661,7 @@ static void gen_msa_elm(DisasContext *ctx) uint8_t dfn = (ctx->opcode >> 16) & 0x3f; if (dfn == 0x3E) { - /* CTCMSA, CFCMSA, MOVE.V */ + /* CTCMSA, CFCMSA */ gen_msa_elm_3e(ctx); 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id p1sm7343125wmq.23.2021.10.28.14.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:11:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 28/32] target/mips: Convert CFCMSA opcode to decodetree Date: Thu, 28 Oct 2021 23:08:39 +0200 Message-Id: <20211028210843.2120802-29-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 5 ++++- target/mips/tcg/msa_translate.c | 27 +++++++++++++++++++-------- 2 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index d1b6a63b526..de8153a89bf 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ................ @bz HSUB_U 011110 111.. ..... ..... ..... 010101 @3r SLDI 011110 0000 ...... ..... ..... 011001 @elm_df - SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + { + CFCMSA 011110 0001111110 ..... ..... 011001 @elm + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + } { MOVE_V 011110 0010111110 ..... ..... 011001 @elm COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 1cc9cd8afa5..b8439a2bd37 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,7 +45,6 @@ enum { enum { /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, }; static const char msaregnames[][6] = { @@ -549,7 +548,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) uint8_t source = (ctx->opcode >> 11) & 0x1f; uint8_t dest = (ctx->opcode >> 6) & 0x1f; TCGv telm = tcg_temp_new(); - TCGv_i32 tsr = tcg_const_i32(source); TCGv_i32 tdt = tcg_const_i32(dest); switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { @@ -557,10 +555,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) gen_load_gpr(telm, source); gen_helper_msa_ctcmsa(cpu_env, telm, tdt); break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -569,7 +563,24 @@ static void gen_msa_elm_3e(DisasContext *ctx) tcg_temp_free(telm); tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); +} + +static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) +{ + TCGv telm; + + if (!check_msa_enabled(ctx)) { + return true; + } + + telm = tcg_temp_new(); + + gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); + gen_store_gpr(telm, a->wd); + + tcg_temp_free(telm); + + return true; } static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, @@ -661,7 +672,7 @@ static void gen_msa_elm(DisasContext *ctx) uint8_t dfn = (ctx->opcode >> 16) & 0x3f; if (dfn == 0x3E) { - /* CTCMSA, CFCMSA */ + /* CTCMSA */ gen_msa_elm_3e(ctx); return; } else { From patchwork Thu Oct 28 21:08:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FbiV6LYJ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id b18sm4588258wru.54.2021.10.28.14.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:11:07 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 29/32] target/mips: Convert CTCMSA opcode to decodetree Date: Thu, 28 Oct 2021 23:08:40 +0200 Message-Id: <20211028210843.2120802-30-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 5 ++- target/mips/tcg/msa_translate.c | 69 ++++++--------------------------- 2 files changed, 16 insertions(+), 58 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index de8153a89bf..a4c7cceb15f 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -167,7 +167,10 @@ BNZ 010001 111 .. ..... ................ @bz HSUB_S 011110 110.. ..... ..... ..... 010101 @3r HSUB_U 011110 111.. ..... ..... ..... 010101 @3r - SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + { + CTCMSA 011110 0000111110 ..... ..... 011001 @elm + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df + } { CFCMSA 011110 0001111110 ..... ..... 011001 @elm SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index b8439a2bd37..62aef43a6e7 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -35,18 +35,6 @@ static inline int plus_2(DisasContext *s, int x) /* Include the auto-generated decoder. */ #include "decode-msa.c.inc" -#define OPC_MSA (0x1E << 26) - -#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) -enum { - OPC_MSA_ELM = 0x19 | OPC_MSA, -}; - -enum { - /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ - OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, -}; - static const char msaregnames[][6] = { "w0.d0", "w0.d1", "w1.d0", "w1.d1", "w2.d0", "w2.d1", "w3.d0", "w3.d1", @@ -542,27 +530,22 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) return true; } -static void gen_msa_elm_3e(DisasContext *ctx) +static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a) { -#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) - uint8_t source = (ctx->opcode >> 11) & 0x1f; - uint8_t dest = (ctx->opcode >> 6) & 0x1f; - TCGv telm = tcg_temp_new(); - TCGv_i32 tdt = tcg_const_i32(dest); + TCGv telm; - switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { - case OPC_CTCMSA: - gen_load_gpr(telm, source); - gen_helper_msa_ctcmsa(cpu_env, telm, tdt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; + if (!check_msa_enabled(ctx)) { + return true; } + telm = tcg_temp_new(); + + gen_load_gpr(telm, a->ws); + gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); + tcg_temp_free(telm); - tcg_temp_free_i32(tdt); + + return true; } static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) @@ -667,20 +650,6 @@ static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) return trans_msa_elm_fn(ctx, a, gen_msa_insert); } -static void gen_msa_elm(DisasContext *ctx) -{ - uint8_t dfn = (ctx->opcode >> 16) & 0x3f; - - if (dfn == 0x3E) { - /* CTCMSA */ - gen_msa_elm_3e(ctx); - return; - } else { - gen_reserved_instruction(ctx); - return; - } -} - TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); @@ -794,21 +763,7 @@ TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { - uint32_t opcode = ctx->opcode; - - if (!check_msa_enabled(ctx)) { - return true; - } - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_ELM: - gen_msa_elm(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } + gen_reserved_instruction(ctx); return true; } From patchwork Thu Oct 28 21:08:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=fF5Ofo9F; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgK0K2kk7z9sRN for ; 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id g7sm5287333wrd.81.2021.10.28.14.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:11:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 30/32] target/mips: Remove generic MSA opcode Date: Thu, 28 Oct 2021 23:08:41 +0200 Message-Id: <20211028210843.2120802-31-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 2 -- target/mips/tcg/msa_translate.c | 7 ------- 2 files changed, 9 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index a4c7cceb15f..124768132ba 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -257,6 +257,4 @@ BNZ 010001 111 .. ..... ................ @bz LD 011110 .......... ..... ..... 1000 .. @ldst ST 011110 .......... ..... ..... 1001 .. @ldst - - MSA 011110 -------------------------- } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 62aef43a6e7..a1455ca6fa7 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -761,13 +761,6 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); -static bool trans_MSA(DisasContext *ctx, arg_MSA *a) -{ - gen_reserved_instruction(ctx); - - return true; -} - static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, gen_helper_piv *gen_msa_ldst) { From patchwork Thu Oct 28 21:08:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547716 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=CeIhF1Mq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HgK6r5BWfz9sRN for ; Fri, 29 Oct 2021 08:52:51 +1100 (AEDT) Received: from localhost ([::1]:60000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgDKJ-0008L6-FH for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2021 17:52:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgCgH-0001VT-Gh for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:11:26 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:34363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgCgB-0007XW-Fq for qemu-devel@nongnu.org; Thu, 28 Oct 2021 17:11:22 -0400 Received: by mail-wm1-x333.google.com with SMTP id o4-20020a1c7504000000b0032cab7473caso5363045wmc.1 for ; Thu, 28 Oct 2021 14:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R4+dw+1Xcz/zHwGjc+X6ZkAOJvuUJcE17DmY+cMGe3w=; b=CeIhF1MqicHOHjvtHsQ7n24jJ+hB/3GGssoSpfk3ccmM66infPqXPPU+aJ3056qnrt /b/sVWr2ph9Ijxak9RDr9qrj4YUAL9F/ayIrbM7AOwAoPCUsfwMabnmX4Ii7nICFsgb+ qh08J5c8AG+y2lT8ilVoPAINFbz6TPrr4EglLecbtquRhLDw+oqOPVMtVRCtJRNrresi jFb6VaJNh5p9LYuwecoOg0i6YmEw0xYdokapnyGH21uLsNsXgclAP/V5FG3PZLpgEs7V 6pA0BGeStn0XgOl9Jh1w2BQvmT0sLT8Y1THoY8JPsE0gUcA9SJdKyrPL4L70GkPd1V5O 0vcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R4+dw+1Xcz/zHwGjc+X6ZkAOJvuUJcE17DmY+cMGe3w=; b=Ed57Qhwfdho1SBUjXNDMz/IoXNgy4Np6XRVj+Xw2I60fAyvRi4CPGPG2ddMpoPQjhM Byy2UslB3Jbz9Upf8DkjpYPUL4cXbweFu6SDFHN9u65w6zU2LU62Ltw8MNYZcGzh5EEv Z8oYKqXCj/TM3BBf/7VXTj2JO8suZlITk40NYFCiUvmWyfQWhzEyJKYLOc/Jbb6oMgyq yklq+CUv6FHnazX1sKbcjeDkGZMANVV7NppCPQSpHajRpGe7RKNY5fu3hnfBSTZwAB8Z YNYmeOTq8stk7IxWbJbu21VI5pLW8sTxwuCnNgT4YE1CxoxSg8L+DlUcqcYutwSoWaqs 7F0w== X-Gm-Message-State: AOAM530yNYuS3J34Hs046tz0Zu3KZlXVz+m82yh0Lo7I6RTriMtWh2aO 3fi0aeuEXzq+CEk8B+RSIX+xNcKNNV8= X-Google-Smtp-Source: ABdhPJwTTR0U+L6byHzFbqE/8I6gJjhXufhgYCpi7tWJHKj9O7lJW/+/ydq6UzF/BgQ/qqHZkMettQ== X-Received: by 2002:a05:600c:17d4:: with SMTP id y20mr11857394wmo.113.1635455477352; Thu, 28 Oct 2021 14:11:17 -0700 (PDT) Received: from x1w.redhat.com (62.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.62]) by smtp.gmail.com with ESMTPSA id h17sm2312464wrp.34.2021.10.28.14.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:11:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Date: Thu, 28 Oct 2021 23:08:42 +0200 Message-Id: <20211028210843.2120802-32-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa.decode | 398 ++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 200 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 124768132ba..95752891956 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -56,205 +56,203 @@ BNZ_V 010001 01111 ..... ................ @bz_v BZ 010001 110 .. ..... ................ @bz BNZ 010001 111 .. ..... ................ @bz +ANDI 011110 00 ........ ..... ..... 000000 @i8 +ORI 011110 01 ........ ..... ..... 000000 @i8 +NORI 011110 10 ........ ..... ..... 000000 @i8 +XORI 011110 11 ........ ..... ..... 000000 @i8 +BMNZI 011110 00 ........ ..... ..... 000001 @i8 +BMZI 011110 01 ........ ..... ..... 000001 @i8 +BSELI 011110 10 ........ ..... ..... 000001 @i8 +SHF 011110 .. ........ ..... ..... 000010 @i8_df + +ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 +SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 +MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 +MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 +MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 +MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 + +CEQI 011110 000 .. ..... ..... ..... 000111 @s5 +CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 +CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 +CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 +CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 + +LDI 011110 110 .. .......... ..... 000111 @ldi + +SLLI 011110 000 ....... ..... ..... 001001 @bit +SRAI 011110 001 ....... ..... ..... 001001 @bit +SRLI 011110 010 ....... ..... ..... 001001 @bit +BCLRI 011110 011 ....... ..... ..... 001001 @bit +BSETI 011110 100 ....... ..... ..... 001001 @bit +BNEGI 011110 101 ....... ..... ..... 001001 @bit +BINSLI 011110 110 ....... ..... ..... 001001 @bit +BINSRI 011110 111 ....... ..... ..... 001001 @bit + +SAT_S 011110 000 ....... ..... ..... 001010 @bit +SAT_U 011110 001 ....... ..... ..... 001010 @bit +SRARI 011110 010 ....... ..... ..... 001010 @bit +SRLRI 011110 011 ....... ..... ..... 001010 @bit + +SLL 011110 000.. ..... ..... ..... 001101 @3r +SRA 011110 001.. ..... ..... ..... 001101 @3r +SRL 011110 010.. ..... ..... ..... 001101 @3r +BCLR 011110 011.. ..... ..... ..... 001101 @3r +BSET 011110 100.. ..... ..... ..... 001101 @3r +BNEG 011110 101.. ..... ..... ..... 001101 @3r +BINSL 011110 110.. ..... ..... ..... 001101 @3r +BINSR 011110 111.. ..... ..... ..... 001101 @3r + +ADDV 011110 000.. ..... ..... ..... 001110 @3r +SUBV 011110 001.. ..... ..... ..... 001110 @3r +MAX_S 011110 010.. ..... ..... ..... 001110 @3r +MAX_U 011110 011.. ..... ..... ..... 001110 @3r +MIN_S 011110 100.. ..... ..... ..... 001110 @3r +MIN_U 011110 101.. ..... ..... ..... 001110 @3r +MAX_A 011110 110.. ..... ..... ..... 001110 @3r +MIN_A 011110 111.. ..... ..... ..... 001110 @3r + +CEQ 011110 000.. ..... ..... ..... 001111 @3r +CLT_S 011110 010.. ..... ..... ..... 001111 @3r +CLT_U 011110 011.. ..... ..... ..... 001111 @3r +CLE_S 011110 100.. ..... ..... ..... 001111 @3r +CLE_U 011110 101.. ..... ..... ..... 001111 @3r + +ADD_A 011110 000.. ..... ..... ..... 010000 @3r +ADDS_A 011110 001.. ..... ..... ..... 010000 @3r +ADDS_S 011110 010.. ..... ..... ..... 010000 @3r +ADDS_U 011110 011.. ..... ..... ..... 010000 @3r +AVE_S 011110 100.. ..... ..... ..... 010000 @3r +AVE_U 011110 101.. ..... ..... ..... 010000 @3r +AVER_S 011110 110.. ..... ..... ..... 010000 @3r +AVER_U 011110 111.. ..... ..... ..... 010000 @3r + +SUBS_S 011110 000.. ..... ..... ..... 010001 @3r +SUBS_U 011110 001.. ..... ..... ..... 010001 @3r +SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r +SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r +ASUB_S 011110 100.. ..... ..... ..... 010001 @3r +ASUB_U 011110 101.. ..... ..... ..... 010001 @3r + +MULV 011110 000.. ..... ..... ..... 010010 @3r +MADDV 011110 001.. ..... ..... ..... 010010 @3r +MSUBV 011110 010.. ..... ..... ..... 010010 @3r +DIV_S 011110 100.. ..... ..... ..... 010010 @3r +DIV_U 011110 101.. ..... ..... ..... 010010 @3r +MOD_S 011110 110.. ..... ..... ..... 010010 @3r +MOD_U 011110 111.. ..... ..... ..... 010010 @3r + +DOTP_S 011110 000.. ..... ..... ..... 010011 @3r +DOTP_U 011110 001.. ..... ..... ..... 010011 @3r +DPADD_S 011110 010.. ..... ..... ..... 010011 @3r +DPADD_U 011110 011.. ..... ..... ..... 010011 @3r +DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r +DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r + +SLD 011110 000 .. ..... ..... ..... 010100 @3r +SPLAT 011110 001 .. ..... ..... ..... 010100 @3r +PCKEV 011110 010 .. ..... ..... ..... 010100 @3r +PCKOD 011110 011 .. ..... ..... ..... 010100 @3r +ILVL 011110 100 .. ..... ..... ..... 010100 @3r +ILVR 011110 101 .. ..... ..... ..... 010100 @3r +ILVEV 011110 110 .. ..... ..... ..... 010100 @3r +ILVOD 011110 111 .. ..... ..... ..... 010100 @3r + +VSHF 011110 000 .. ..... ..... ..... 010101 @3r +SRAR 011110 001 .. ..... ..... ..... 010101 @3r +SRLR 011110 010 .. ..... ..... ..... 010101 @3r +HADD_S 011110 100.. ..... ..... ..... 010101 @3r +HADD_U 011110 101.. ..... ..... ..... 010101 @3r +HSUB_S 011110 110.. ..... ..... ..... 010101 @3r +HSUB_U 011110 111.. ..... ..... ..... 010101 @3r + { - ANDI 011110 00 ........ ..... ..... 000000 @i8 - ORI 011110 01 ........ ..... ..... 000000 @i8 - NORI 011110 10 ........ ..... ..... 000000 @i8 - XORI 011110 11 ........ ..... ..... 000000 @i8 - BMNZI 011110 00 ........ ..... ..... 000001 @i8 - BMZI 011110 01 ........ ..... ..... 000001 @i8 - BSELI 011110 10 ........ ..... ..... 000001 @i8 - SHF 011110 .. ........ ..... ..... 000010 @i8_df - - ADDVI 011110 000 .. ..... ..... ..... 000110 @u5 - SUBVI 011110 001 .. ..... ..... ..... 000110 @u5 - MAXI_S 011110 010 .. ..... ..... ..... 000110 @s5 - MAXI_U 011110 011 .. ..... ..... ..... 000110 @u5 - MINI_S 011110 100 .. ..... ..... ..... 000110 @s5 - MINI_U 011110 101 .. ..... ..... ..... 000110 @u5 - - CEQI 011110 000 .. ..... ..... ..... 000111 @s5 - CLTI_S 011110 010 .. ..... ..... ..... 000111 @s5 - CLTI_U 011110 011 .. ..... ..... ..... 000111 @u5 - CLEI_S 011110 100 .. ..... ..... ..... 000111 @s5 - CLEI_U 011110 101 .. ..... ..... ..... 000111 @u5 - - LDI 011110 110 .. .......... ..... 000111 @ldi - - SLLI 011110 000 ....... ..... ..... 001001 @bit - SRAI 011110 001 ....... ..... ..... 001001 @bit - SRLI 011110 010 ....... ..... ..... 001001 @bit - BCLRI 011110 011 ....... ..... ..... 001001 @bit - BSETI 011110 100 ....... ..... ..... 001001 @bit - BNEGI 011110 101 ....... ..... ..... 001001 @bit - BINSLI 011110 110 ....... ..... ..... 001001 @bit - BINSRI 011110 111 ....... ..... ..... 001001 @bit - - SAT_S 011110 000 ....... ..... ..... 001010 @bit - SAT_U 011110 001 ....... ..... ..... 001010 @bit - SRARI 011110 010 ....... ..... ..... 001010 @bit - SRLRI 011110 011 ....... ..... ..... 001010 @bit - - SLL 011110 000.. ..... ..... ..... 001101 @3r - SRA 011110 001.. ..... ..... ..... 001101 @3r - SRL 011110 010.. ..... ..... ..... 001101 @3r - BCLR 011110 011.. ..... ..... ..... 001101 @3r - BSET 011110 100.. ..... ..... ..... 001101 @3r - BNEG 011110 101.. ..... ..... ..... 001101 @3r - BINSL 011110 110.. ..... ..... ..... 001101 @3r - BINSR 011110 111.. ..... ..... ..... 001101 @3r - - ADDV 011110 000.. ..... ..... ..... 001110 @3r - SUBV 011110 001.. ..... ..... ..... 001110 @3r - MAX_S 011110 010.. ..... ..... ..... 001110 @3r - MAX_U 011110 011.. ..... ..... ..... 001110 @3r - MIN_S 011110 100.. ..... ..... ..... 001110 @3r - MIN_U 011110 101.. ..... ..... ..... 001110 @3r - MAX_A 011110 110.. ..... ..... ..... 001110 @3r - MIN_A 011110 111.. ..... ..... ..... 001110 @3r - - CEQ 011110 000.. ..... ..... ..... 001111 @3r - CLT_S 011110 010.. ..... ..... ..... 001111 @3r - CLT_U 011110 011.. ..... ..... ..... 001111 @3r - CLE_S 011110 100.. ..... ..... ..... 001111 @3r - CLE_U 011110 101.. ..... ..... ..... 001111 @3r - - ADD_A 011110 000.. ..... ..... ..... 010000 @3r - ADDS_A 011110 001.. ..... ..... ..... 010000 @3r - ADDS_S 011110 010.. ..... ..... ..... 010000 @3r - ADDS_U 011110 011.. ..... ..... ..... 010000 @3r - AVE_S 011110 100.. ..... ..... ..... 010000 @3r - AVE_U 011110 101.. ..... ..... ..... 010000 @3r - AVER_S 011110 110.. ..... ..... ..... 010000 @3r - AVER_U 011110 111.. ..... ..... ..... 010000 @3r - - SUBS_S 011110 000.. ..... ..... ..... 010001 @3r - SUBS_U 011110 001.. ..... ..... ..... 010001 @3r - SUBSUS_U 011110 010.. ..... ..... ..... 010001 @3r - SUBSUU_S 011110 011.. ..... ..... ..... 010001 @3r - ASUB_S 011110 100.. ..... ..... ..... 010001 @3r - ASUB_U 011110 101.. ..... ..... ..... 010001 @3r - - MULV 011110 000.. ..... ..... ..... 010010 @3r - MADDV 011110 001.. ..... ..... ..... 010010 @3r - MSUBV 011110 010.. ..... ..... ..... 010010 @3r - DIV_S 011110 100.. ..... ..... ..... 010010 @3r - DIV_U 011110 101.. ..... ..... ..... 010010 @3r - MOD_S 011110 110.. ..... ..... ..... 010010 @3r - MOD_U 011110 111.. ..... ..... ..... 010010 @3r - - DOTP_S 011110 000.. ..... ..... ..... 010011 @3r - DOTP_U 011110 001.. ..... ..... ..... 010011 @3r - DPADD_S 011110 010.. ..... ..... ..... 010011 @3r - DPADD_U 011110 011.. ..... ..... ..... 010011 @3r - DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r - DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r - - SLD 011110 000 .. ..... ..... ..... 010100 @3r - SPLAT 011110 001 .. ..... ..... ..... 010100 @3r - PCKEV 011110 010 .. ..... ..... ..... 010100 @3r - PCKOD 011110 011 .. ..... ..... ..... 010100 @3r - ILVL 011110 100 .. ..... ..... ..... 010100 @3r - ILVR 011110 101 .. ..... ..... ..... 010100 @3r - ILVEV 011110 110 .. ..... ..... ..... 010100 @3r - ILVOD 011110 111 .. ..... ..... ..... 010100 @3r - - VSHF 011110 000 .. ..... ..... ..... 010101 @3r - SRAR 011110 001 .. ..... ..... ..... 010101 @3r - SRLR 011110 010 .. ..... ..... ..... 010101 @3r - HADD_S 011110 100.. ..... ..... ..... 010101 @3r - HADD_U 011110 101.. ..... ..... ..... 010101 @3r - HSUB_S 011110 110.. ..... ..... ..... 010101 @3r - HSUB_U 011110 111.. ..... ..... ..... 010101 @3r - - { - CTCMSA 011110 0000111110 ..... ..... 011001 @elm - SLDI 011110 0000 ...... ..... ..... 011001 @elm_df - } - { - CFCMSA 011110 0001111110 ..... ..... 011001 @elm - SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df - } - { - MOVE_V 011110 0010111110 ..... ..... 011001 @elm - COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df - } - COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df - INSERT 011110 0100 ...... ..... ..... 011001 @elm_df - INSVE 011110 0101 ...... ..... ..... 011001 @elm_df - - FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w - FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w - FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w - FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w - FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w - FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w - FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w - FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w - FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w - FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w - FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w - FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w - FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w - FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w - FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w - FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w - - FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w - FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w - FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w - FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w - FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w - FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w - FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w - FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w - FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w - FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w - FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w - FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w - FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w - - FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w - FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w - FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w - MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h - MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h - MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h - FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w - FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w - FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w - MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h - MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h - MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h - - AND_V 011110 00000 ..... ..... ..... 011110 @vec - OR_V 011110 00001 ..... ..... ..... 011110 @vec - NOR_V 011110 00010 ..... ..... ..... 011110 @vec - XOR_V 011110 00011 ..... ..... ..... 011110 @vec - BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec - BMZ_V 011110 00101 ..... ..... ..... 011110 @vec - BSEL_V 011110 00110 ..... ..... ..... 011110 @vec - FILL 011110 11000000 .. ..... ..... 011110 @2r - PCNT 011110 11000001 .. ..... ..... 011110 @2r - NLOC 011110 11000010 .. ..... ..... 011110 @2r - NLZC 011110 11000011 .. ..... ..... 011110 @2r - FCLASS 011110 110010000 . ..... ..... 011110 @2rf - FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf - FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf - FSQRT 011110 110010011 . ..... ..... 011110 @2rf - FRSQRT 011110 110010100 . ..... ..... 011110 @2rf - FRCP 011110 110010101 . ..... ..... 011110 @2rf - FRINT 011110 110010110 . ..... ..... 011110 @2rf - FLOG2 011110 110010111 . ..... ..... 011110 @2rf - FEXUPL 011110 110011000 . ..... ..... 011110 @2rf - FEXUPR 011110 110011001 . ..... ..... 011110 @2rf - FFQL 011110 110011010 . ..... ..... 011110 @2rf - FFQR 011110 110011011 . ..... ..... 011110 @2rf - FTINT_S 011110 110011100 . ..... ..... 011110 @2rf - FTINT_U 011110 110011101 . ..... ..... 011110 @2rf - FFINT_S 011110 110011110 . ..... ..... 011110 @2rf - FFINT_U 011110 110011111 . ..... ..... 011110 @2rf - - LD 011110 .......... ..... ..... 1000 .. @ldst - ST 011110 .......... ..... ..... 1001 .. @ldst + CTCMSA 011110 0000111110 ..... ..... 011001 @elm + SLDI 011110 0000 ...... ..... ..... 011001 @elm_df } +{ + CFCMSA 011110 0001111110 ..... ..... 011001 @elm + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df +} +{ + MOVE_V 011110 0010111110 ..... ..... 011001 @elm + COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df +} +COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df +INSERT 011110 0100 ...... ..... ..... 011001 @elm_df +INSVE 011110 0101 ...... ..... ..... 011001 @elm_df + +FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w +FCUN 011110 0001 . ..... ..... ..... 011010 @3rf_w +FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf_w +FCUEQ 011110 0011 . ..... ..... ..... 011010 @3rf_w +FCLT 011110 0100 . ..... ..... ..... 011010 @3rf_w +FCULT 011110 0101 . ..... ..... ..... 011010 @3rf_w +FCLE 011110 0110 . ..... ..... ..... 011010 @3rf_w +FCULE 011110 0111 . ..... ..... ..... 011010 @3rf_w +FSAF 011110 1000 . ..... ..... ..... 011010 @3rf_w +FSUN 011110 1001 . ..... ..... ..... 011010 @3rf_w +FSEQ 011110 1010 . ..... ..... ..... 011010 @3rf_w +FSUEQ 011110 1011 . ..... ..... ..... 011010 @3rf_w +FSLT 011110 1100 . ..... ..... ..... 011010 @3rf_w +FSULT 011110 1101 . ..... ..... ..... 011010 @3rf_w +FSLE 011110 1110 . ..... ..... ..... 011010 @3rf_w +FSULE 011110 1111 . ..... ..... ..... 011010 @3rf_w + +FADD 011110 0000 . ..... ..... ..... 011011 @3rf_w +FSUB 011110 0001 . ..... ..... ..... 011011 @3rf_w +FMUL 011110 0010 . ..... ..... ..... 011011 @3rf_w +FDIV 011110 0011 . ..... ..... ..... 011011 @3rf_w +FMADD 011110 0100 . ..... ..... ..... 011011 @3rf_w +FMSUB 011110 0101 . ..... ..... ..... 011011 @3rf_w +FEXP2 011110 0111 . ..... ..... ..... 011011 @3rf_w +FEXDO 011110 1000 . ..... ..... ..... 011011 @3rf_w +FTQ 011110 1010 . ..... ..... ..... 011011 @3rf_w +FMIN 011110 1100 . ..... ..... ..... 011011 @3rf_w +FMIN_A 011110 1101 . ..... ..... ..... 011011 @3rf_w +FMAX 011110 1110 . ..... ..... ..... 011011 @3rf_w +FMAX_A 011110 1111 . ..... ..... ..... 011011 @3rf_w + +FCOR 011110 0001 . ..... ..... ..... 011100 @3rf_w +FCUNE 011110 0010 . ..... ..... ..... 011100 @3rf_w +FCNE 011110 0011 . ..... ..... ..... 011100 @3rf_w +MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf_h +MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf_h +MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf_h +FSOR 011110 1001 . ..... ..... ..... 011100 @3rf_w +FSUNE 011110 1010 . ..... ..... ..... 011100 @3rf_w +FSNE 011110 1011 . ..... ..... ..... 011100 @3rf_w +MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf_h +MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf_h +MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf_h + +AND_V 011110 00000 ..... ..... ..... 011110 @vec +OR_V 011110 00001 ..... ..... ..... 011110 @vec +NOR_V 011110 00010 ..... ..... ..... 011110 @vec +XOR_V 011110 00011 ..... ..... ..... 011110 @vec +BMNZ_V 011110 00100 ..... ..... ..... 011110 @vec +BMZ_V 011110 00101 ..... ..... ..... 011110 @vec +BSEL_V 011110 00110 ..... ..... ..... 011110 @vec +FILL 011110 11000000 .. ..... ..... 011110 @2r +PCNT 011110 11000001 .. ..... ..... 011110 @2r +NLOC 011110 11000010 .. ..... ..... 011110 @2r +NLZC 011110 11000011 .. ..... ..... 011110 @2r +FCLASS 011110 110010000 . ..... ..... 011110 @2rf +FTRUNC_S 011110 110010001 . ..... ..... 011110 @2rf +FTRUNC_U 011110 110010010 . ..... ..... 011110 @2rf +FSQRT 011110 110010011 . ..... ..... 011110 @2rf +FRSQRT 011110 110010100 . ..... ..... 011110 @2rf +FRCP 011110 110010101 . ..... ..... 011110 @2rf +FRINT 011110 110010110 . ..... ..... 011110 @2rf +FLOG2 011110 110010111 . ..... ..... 011110 @2rf +FEXUPL 011110 110011000 . ..... ..... 011110 @2rf +FEXUPR 011110 110011001 . ..... ..... 011110 @2rf +FFQL 011110 110011010 . ..... ..... 011110 @2rf +FFQR 011110 110011011 . ..... ..... 011110 @2rf +FTINT_S 011110 110011100 . ..... ..... 011110 @2rf +FTINT_U 011110 110011101 . ..... ..... 011110 @2rf +FFINT_S 011110 110011110 . ..... ..... 011110 @2rf +FFINT_U 011110 110011111 . ..... ..... 011110 @2rf + +LD 011110 .......... ..... ..... 1000 .. @ldst +ST 011110 .......... ..... ..... 1001 .. @ldst From patchwork Thu Oct 28 21:08:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1547718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=N3Crz0Am; dkim-atps=neutral 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[83.57.168.62]) by smtp.gmail.com with ESMTPSA id t6sm3939777wrw.78.2021.10.28.14.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Oct 2021 14:11:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 32/32] target/mips: Adjust style in msa_translate_init() Date: Thu, 28 Oct 2021 23:08:43 +0200 Message-Id: <20211028210843.2120802-33-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211028210843.2120802-1-f4bug@amsat.org> References: <20211028210843.2120802-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" While the first 'off' variable assignment is unused, it helps to better understand the code logic. Move the assignation where it would have been used so it is easier to compare the MSA registers based on FPU ones versus the MSA specific registers. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/msa_translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index a1455ca6fa7..7576b3ed86b 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -132,13 +132,15 @@ void msa_translate_init(void) int i; for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + int off; /* * The MSA vector registers are mapped on the * scalar floating-point unit (FPU) registers. */ + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = fpu_f64[i]; + off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);