From patchwork Mon Oct 18 12:37:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=isMHjZIx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HXxHc42nNz9sPf for ; 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Mon, 18 Oct 2021 12:37:52 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.170.57]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Mon, 18 Oct 2021 12:37:52 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:46 +0200 Message-Id: <20211018123751.72794-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: hIFg4V1nFhOn1RGZ_Lqc5CSTIgu6996s X-Proofpoint-ORIG-GUID: hIFg4V1nFhOn1RGZ_Lqc5CSTIgu6996s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_03,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=948 adultscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180075 Subject: [Skiboot] [PATCH 1/6] i2c: Add more info to debug trace X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add the bus ID and device address when showing the result of an i2c request. It makes debug easier when several requests are flying simultaneously. Signed-off-by: Frederic Barrat --- core/i2c.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/core/i2c.c b/core/i2c.c index b4313d43..8f4c01c5 100644 --- a/core/i2c.c +++ b/core/i2c.c @@ -215,10 +215,11 @@ int64_t i2c_request_sync(struct i2c_request *req) *(unsigned char *)(req->rw_buf+i)); } - prlog(PR_DEBUG, "I2C: %s req op=%x offset=%x buf=%s buflen=%d " - "delay=%lu/%lld rc=%lld\n", - (rc) ? "!!!!" : "----", req->op, req->offset, - buf, req->rw_len, tb_to_msecs(waited), req->timeout, rc); + /* print the device address shifted by one to match all hw docs */ + prlog(PR_DEBUG, "I2C: %s bus=%x req op=%x dev_addr=%x offset=%x buf=%s buflen=%d delay=%lu/%lld rc=%lld\n", + (rc) ? "!!!!" : "----", req->bus->opal_id, req->op, + req->dev_addr << 1, req->offset, buf, req->rw_len, + tb_to_msecs(waited), req->timeout, rc); return rc; } From patchwork Mon Oct 18 12:37:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=DWSkhQzv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HXxHm0Dp5z9sPf for ; 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Mon, 18 Oct 2021 12:37:52 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.170.57]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Mon, 18 Oct 2021 12:37:52 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:47 +0200 Message-Id: <20211018123751.72794-3-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mfLqSdfYgnTbdLwyAGM7hsMMoe9jcLru X-Proofpoint-ORIG-GUID: mfLqSdfYgnTbdLwyAGM7hsMMoe9jcLru X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_05,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 mlxlogscore=893 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 phishscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180075 Subject: [Skiboot] [PATCH 2/6] rainier: Remove old version of code to power on the PCI slots X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is mostly for readability of the next patch, where we'll be able to control the state of individual PCI slots. Signed-off-by: Frederic Barrat --- platforms/astbmc/rainier.c | 87 -------------------------------------- 1 file changed, 87 deletions(-) diff --git a/platforms/astbmc/rainier.c b/platforms/astbmc/rainier.c index 17d9fe2b..605e7b1b 100644 --- a/platforms/astbmc/rainier.c +++ b/platforms/astbmc/rainier.c @@ -12,97 +12,10 @@ #include "astbmc.h" -/* - * puti2c pu 2 1 C6 00 6 1 -quiet - * puti2c pu 2 1 C6 54 7 1 -quiet - * puti2c pu 2 1 C6 05 8 1 -quiet - * puti2c pu 2 1 C6 00 9 1 -quiet - * - * sleep 4 - * - * puti2c pu 2 1 C6 55 6 1 -quiet - * puti2c pu 2 1 C6 55 7 1 -quiet - * 2 - engine - * 1 - port - * C6 - slave addr - * 55 - data - * 7 - register - * 1 - register length? - */ - -static int64_t smbus_write8(struct i2c_bus *bus, uint8_t reg, uint8_t data) -{ - struct i2c_request req; - - memset(&req, 0, sizeof(req)); - - req.bus = bus; - req.dev_addr = 0xC6 >> 1; /* Docs use 8bit addresses */ - - req.op = SMBUS_WRITE; - req.offset = reg; - req.offset_bytes = 1; - req.rw_buf = &data; - req.rw_len = 1; - req.timeout = 100; - - return i2c_request_sync(&req); -} - -static int64_t slot_power_enable(struct i2c_bus *bus) -{ - /* FIXME: we could do this in one transaction using auto-increment */ - if (smbus_write8(bus, 0x6, 0x00)) - return -1; - if (smbus_write8(bus, 0x7, 0x54)) - return -1; - if (smbus_write8(bus, 0x8, 0x05)) - return -1; - if (smbus_write8(bus, 0x9, 0x00)) - return -1; - - /* FIXME: Poll for PGOOD going high */ - - if (smbus_write8(bus, 0x6, 0x55)) - return -1; - if (smbus_write8(bus, 0x7, 0x55)) - return -1; - - return 0; -} - -static void rainier_init_slot_power(void) -{ - struct proc_chip *chip; - struct i2c_bus *bus; - - /* - * Controller on P0 is for slots C7 -> C11 - * on P2 is for slots C0 -> C4 - * Both chips use engine 2 port 1 - * - * Rainier with only one socket is officially supported, so - * we may not have slots C0 -> C4 - */ - for_each_chip(chip) { - if (chip->id % 4) - continue; - bus = p8_i2c_add_bus(chip->id, 2, 1, 400000); - if (!bus) { - prerror("Unable to find PCIe power controller I2C bus!\n"); - return; - } - if (slot_power_enable(bus)) { - prerror("Error enabling PCIe slot power on chip %d\n", - chip->id); - } - } -} static void rainier_init(void) { astbmc_init(); - rainier_init_slot_power(); } static bool rainier_probe(void) From patchwork Mon Oct 18 12:37:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=rRWaCnU0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HXxHv3RsNz9sPf for ; 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Mon, 18 Oct 2021 12:37:52 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.170.57]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Mon, 18 Oct 2021 12:37:52 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:48 +0200 Message-Id: <20211018123751.72794-4-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: BzOGyPAuVd6tMaiB-TqwJkiqjgtAkErU X-Proofpoint-ORIG-GUID: BzOGyPAuVd6tMaiB-TqwJkiqjgtAkErU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_05,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 priorityscore=1501 spamscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180077 Subject: [Skiboot] [PATCH 3/6] rainier: Introduce PCI hotplug controller interface X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The power of PCI slots can be controlled through i2c controllers (PCA9552). Rainier has two, one per DCM. This patch adds a hotplug controller interface, which allow to control the state of each PCI slot. As described in the workbook, once power is enable and after a 1 or 2 second window, we need to check pgood to detect any failure and set a control bit per the hw design. At power-on, all slots are enabled at once but a later patch will allow the OS to control the state of each slot individually. Signed-off-by: Frederic Barrat --- platforms/astbmc/astbmc.h | 1 + platforms/astbmc/rainier.c | 232 +++++++++++++++++++++++++++++++++++++ 2 files changed, 233 insertions(+) diff --git a/platforms/astbmc/astbmc.h b/platforms/astbmc/astbmc.h index 00f22123..9fbeb15d 100644 --- a/platforms/astbmc/astbmc.h +++ b/platforms/astbmc/astbmc.h @@ -27,6 +27,7 @@ struct slot_table_entry { uint32_t location; const char *name; const struct slot_table_entry *children; + const void *platform_data; uint8_t power_limit; }; diff --git a/platforms/astbmc/rainier.c b/platforms/astbmc/rainier.c index 605e7b1b..467e6d5a 100644 --- a/platforms/astbmc/rainier.c +++ b/platforms/astbmc/rainier.c @@ -9,13 +9,244 @@ #include #include #include +#include +#include #include "astbmc.h" +#define PGOOD_QUERY_WINDOW 2000 /* ms */ + +/* + * Rainier has one PCI hotplug controller per DCM. Each can control 5 + * PCI slots through i2c operations. + * The bits controlling the slot states are spread over 4 consecutive + * 8-bit registers and it's a lot easier to treat them as a 32-bit + * word and extract the state of the slot we target by using the + * proper masks. The PCA9552 supports address auto-increment so we can + * read/write the state of all the slots with one i2c request. + * See the system workbook for the i2c register definition. + * + * Unlike most systems, slots are powered off when reaching skiboot on + * Rainier so the first thing to do is to enable them. + */ + +struct hp_controller { + uint32_t chip_id; + struct lock lock; /* for atomicity of i2c requests */ + struct i2c_request req; + uint32_t i2c_buf; + struct timer slot_timer[5]; +}; + +struct hp_controller hp_controller_dcm0; /* for slots C7 -> C11 */ +struct hp_controller hp_controller_dcm1; /* for slots C0 -> C4 */ + +struct slot_hp_data { + struct hp_controller *hp_controller; + uint8_t slot_index; +}; + +static int64_t hp_controller_i2c_read(struct hp_controller *hpc, + uint32_t *data) +{ + uint64_t rc; + + if (!hpc->req.bus) + return OPAL_HARDWARE; + + hpc->req.op = SMBUS_READ; + rc = i2c_request_sync(&hpc->req); + if (!rc) + *data = le32_to_cpu(hpc->i2c_buf); + return rc; +} + +static int64_t hp_controller_i2c_write(struct hp_controller *hpc, + uint32_t data) +{ + if (!hpc->req.bus) + return OPAL_HARDWARE; + + hpc->i2c_buf = cpu_to_le32(data); + hpc->req.op = SMBUS_WRITE; + return i2c_request_sync(&hpc->req); +} + +static void hp_get_masks(int slot_index, uint32_t *en_mask, uint32_t *pg_mask, + uint32_t *ctl_mask) +{ + if (slot_index == -1) { + /* + * slot_index = -1 is a shortcut used at boot to + * enable all slots in one operation. Unlike other + * platforms, slots are powered off when we reach + * skiboot on rainier. + */ + *en_mask = 0x155; + *pg_mask = 0x155 << 10; + *ctl_mask = 0x155 << 20; + } else { + /* each slot state uses 2 bits */ + *en_mask = 0b01 << (2 * slot_index); + *pg_mask = 0b01 << (2 * (slot_index + 5)); + *ctl_mask = 0b01 << (2 * (slot_index + 10)); + } +} + +static int64_t hp_controller_check_enable(struct hp_controller *hpc, + int slot_index) +{ + uint32_t state, en_mask, ctl_mask, pg_mask; + int64_t rc, rc2; + + if (slot_index < -1 || slot_index > 4) + return OPAL_PARAMETER; + + hp_get_masks(slot_index, &en_mask, &pg_mask, &ctl_mask); + + /* + * Query PGOOD to make sure the slot is powered on correctly. + * If it is, then raise the CTL bits. + * If not, then disable the slot + */ + lock(&hpc->lock); + rc = hp_controller_i2c_read(hpc, &state); + if (rc) + goto unlock; + + state |= ctl_mask; + if (!(state & pg_mask)) { + state &= ~en_mask; + rc = OPAL_HARDWARE; + } + rc2 = hp_controller_i2c_write(hpc, state); + if (!rc) + rc = rc2; +unlock: + unlock(&hpc->lock); + return rc; +} + +static void __unused timer_check_enable(struct timer *t __unused, void *data, + uint64_t now __unused) +{ + struct pci_slot *slot = data; + struct slot_table_entry *ent = slot->data; + const struct slot_hp_data *hp_data; + struct hp_controller *hpc; + uint32_t slot_index; + + hp_data = ent->platform_data; + slot_index = hp_data->slot_index; + hpc = hp_data->hp_controller; + + hp_controller_check_enable(hpc, slot_index); + pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE); +} + +static int64_t hp_controller_enable(struct hp_controller *hpc, int slot_index) +{ + uint32_t state, en_mask, ctl_mask, pg_mask; + int64_t rc = OPAL_SUCCESS; + + if (slot_index < -1 || slot_index > 4) + return OPAL_PARAMETER; + + hp_get_masks(slot_index, &en_mask, &pg_mask, &ctl_mask); + + lock(&hpc->lock); + rc = hp_controller_i2c_read(hpc, &state); + if (rc) + goto unlock; + + /* lower ctrl line */ + state &= ~0x40000000; + state &= ~en_mask; + state |= pg_mask; + state &= ~ctl_mask; + rc = hp_controller_i2c_write(hpc, state); + if (rc) + goto unlock; + + /* enable slot */ + state |= en_mask; + rc = hp_controller_i2c_write(hpc, state); +unlock: + unlock(&hpc->lock); + return rc; +} + +static int64_t __unused hp_controller_disable(struct hp_controller *hpc, int slot_index) +{ + uint32_t state, en_mask, ctl_mask, pg_mask; + uint64_t rc = OPAL_SUCCESS; + + if (slot_index < 0 || slot_index > 4) + return OPAL_PARAMETER; + + hp_get_masks(slot_index, &en_mask, &pg_mask, &ctl_mask); + + lock(&hpc->lock); + rc = hp_controller_i2c_read(hpc, &state); + if (rc) + goto unlock; + + state &= ~ctl_mask; + rc = hp_controller_i2c_write(hpc, state); + if (rc) + goto unlock; + + state &= ~en_mask; + rc = hp_controller_i2c_write(hpc, state); + if (rc) + goto unlock; + + state |= ctl_mask; + rc = hp_controller_i2c_write(hpc, state); +unlock: + unlock(&hpc->lock); + return rc; +} + +static void hp_controller_init(struct hp_controller *hpc, uint32_t chip_id) +{ + init_lock(&hpc->lock); + hpc->chip_id = chip_id; + hpc->i2c_buf = 0; + + hpc->req.dev_addr = 0xC6 >> 1; /* Docs use 8bit addresses */ + hpc->req.offset = 0x16; /* PCA9552: register 6 + auto-increment bit */ + hpc->req.offset_bytes = 1; + hpc->req.rw_buf = &hpc->i2c_buf; + hpc->req.rw_len = 4; + hpc->req.timeout = 100; + hpc->req.bus = p8_i2c_find_bus_by_port(chip_id, 2, 1); + if (!hpc->req.bus) { + prerror("PLAT: Unable to find PCI power controller I2C bus for chip %d\n", chip_id); + return; + } +} + +static void rainier_pci_probe_complete(void) +{ + prlog(PR_DEBUG, "PLAT: checking power of PCI slots\n"); + hp_controller_check_enable(&hp_controller_dcm0, -1); + hp_controller_check_enable(&hp_controller_dcm1, -1); +} + +static void rainier_init_slot_power(void) +{ + prlog(PR_DEBUG, "PLAT: powering on PCI slots\n"); + hp_controller_init(&hp_controller_dcm0, 0); + hp_controller_init(&hp_controller_dcm1, 4); + hp_controller_enable(&hp_controller_dcm0, -1); + hp_controller_enable(&hp_controller_dcm1, -1); +} static void rainier_init(void) { astbmc_init(); + rainier_init_slot_power(); } static bool rainier_probe(void) @@ -43,6 +274,7 @@ DECLARE_PLATFORM(rainier) = { .bmc = &bmc_plat_ast2600_openbmc, .cec_power_down = astbmc_ipmi_power_down, .cec_reboot = astbmc_ipmi_reboot, + .pci_probe_complete = rainier_pci_probe_complete, .elog_commit = ipmi_elog_commit, .exit = astbmc_exit, .terminate = ipmi_terminate, From patchwork Mon Oct 18 12:37:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=loD+jePD; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Mon, 18 Oct 2021 12:37:52 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.170.57]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Mon, 18 Oct 2021 12:37:52 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:49 +0200 Message-Id: <20211018123751.72794-5-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: y55Dqzz8h7ue_sGLtfCZnNKAcawEW0VN X-Proofpoint-ORIG-GUID: y55Dqzz8h7ue_sGLtfCZnNKAcawEW0VN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_03,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 clxscore=1015 adultscore=0 suspectscore=0 mlxscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180075 Subject: [Skiboot] [PATCH 4/6] rainier: Define PCI slot table X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Define the table of PCI slots for Rainier, reusing the existing slot table infrastructure. For each slot, add the information useful to control power through the hotplug controller. This patch also redefines the slot power management callbacks to route them to the previously introduced hotplug controller interfaces. Signed-off-by: Frederic Barrat --- platforms/astbmc/rainier.c | 159 ++++++++++++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 2 deletions(-) diff --git a/platforms/astbmc/rainier.c b/platforms/astbmc/rainier.c index 467e6d5a..baa93254 100644 --- a/platforms/astbmc/rainier.c +++ b/platforms/astbmc/rainier.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "astbmc.h" @@ -46,6 +47,61 @@ struct slot_hp_data { uint8_t slot_index; }; +#define RAINIER_HP_DATA(st_name, controller, n) \ + static const struct slot_hp_data st_name = { \ + .hp_controller = &(controller), \ + .slot_index = n, \ + } + +#define RAINIER_SLOT_DEF(st_name, slot_name, hp_data) \ + static const struct slot_table_entry st_name[] = { \ + { \ + .etype = st_pluggable_slot, \ + .name = slot_name, \ + .platform_data = &(hp_data), \ + }, \ + { .etype = st_end }, \ + } + +RAINIER_HP_DATA(c7_data, hp_controller_dcm0, 0); +RAINIER_HP_DATA(c8_data, hp_controller_dcm0, 1); +RAINIER_HP_DATA(c9_data, hp_controller_dcm0, 2); +RAINIER_HP_DATA(c10_data, hp_controller_dcm0, 3); +RAINIER_HP_DATA(c11_data, hp_controller_dcm0, 4); +RAINIER_SLOT_DEF(p1phb3_slot, "C7", c7_data); +RAINIER_SLOT_DEF(p1phb1_slot, "C8", c8_data); +RAINIER_SLOT_DEF(p1phb0_slot, "C9", c9_data); +RAINIER_SLOT_DEF(p0phb3_slot, "C10", c10_data); +RAINIER_SLOT_DEF(p0phb0_slot, "C11", c11_data); + +RAINIER_HP_DATA(c0_data, hp_controller_dcm1, 0); +RAINIER_HP_DATA(c1_data, hp_controller_dcm1, 1); +RAINIER_HP_DATA(c2_data, hp_controller_dcm1, 2); +RAINIER_HP_DATA(c3_data, hp_controller_dcm1, 3); +RAINIER_HP_DATA(c4_data, hp_controller_dcm1, 4); +RAINIER_SLOT_DEF(p3phb3_slot, "C0", c0_data); +RAINIER_SLOT_DEF(p3phb1_slot, "C1", c1_data); +RAINIER_SLOT_DEF(p3phb0_slot, "C2", c2_data); +RAINIER_SLOT_DEF(p2phb3_slot, "C3", c3_data); +RAINIER_SLOT_DEF(p2phb0_slot, "C4", c4_data); + +static const struct slot_table_entry rainier_phb_table[] = { + ST_PHB_ENTRY(0, 0, p0phb0_slot), + ST_PHB_ENTRY(0, 3, p0phb3_slot), + + ST_PHB_ENTRY(2, 0, p1phb0_slot), + ST_PHB_ENTRY(2, 1, p1phb1_slot), + ST_PHB_ENTRY(2, 3, p1phb3_slot), + + ST_PHB_ENTRY(4, 0, p2phb0_slot), + ST_PHB_ENTRY(4, 3, p2phb3_slot), + + ST_PHB_ENTRY(6, 0, p3phb0_slot), + ST_PHB_ENTRY(6, 1, p3phb1_slot), + ST_PHB_ENTRY(6, 3, p3phb3_slot), + { .etype = st_end }, +}; + static int64_t hp_controller_i2c_read(struct hp_controller *hpc, uint32_t *data) { @@ -127,7 +183,7 @@ unlock: return rc; } -static void __unused timer_check_enable(struct timer *t __unused, void *data, +static void timer_check_enable(struct timer *t __unused, void *data, uint64_t now __unused) { struct pci_slot *slot = data; @@ -176,7 +232,7 @@ unlock: return rc; } -static int64_t __unused hp_controller_disable(struct hp_controller *hpc, int slot_index) +static int64_t hp_controller_disable(struct hp_controller *hpc, int slot_index) { uint32_t state, en_mask, ctl_mask, pg_mask; uint64_t rc = OPAL_SUCCESS; @@ -227,11 +283,108 @@ static void hp_controller_init(struct hp_controller *hpc, uint32_t chip_id) } } +static int64_t rainier_pci_slot_get_power_state(struct pci_slot *slot, + uint8_t *val) +{ + uint32_t state, en_mask, ctl_mask, pg_mask; + struct slot_table_entry *ent = slot->data; + const struct slot_hp_data *hp_data; + struct hp_controller *hpc; + uint32_t slot_index; + + if (!ent || !ent->platform_data) + return OPAL_PARAMETER; + + hp_data = ent->platform_data; + slot_index = hp_data->slot_index; + hpc = hp_data->hp_controller; + + hp_get_masks(slot_index, &en_mask, &pg_mask, &ctl_mask); + + lock(&hpc->lock); + hp_controller_i2c_read(hpc, &state); + unlock(&hpc->lock); + + *val = (state & en_mask) && (state & pg_mask); + return 0; +} + +static int64_t rainier_pci_slot_set_power_state(struct pci_slot *slot, + uint8_t val) +{ + struct slot_table_entry *ent = slot->data; + const struct slot_hp_data *hp_data; + struct hp_controller *hpc; + uint32_t slot_index; + int64_t rc; + + if (!ent || !ent->platform_data) + return OPAL_PARAMETER; + if (val != PCI_SLOT_POWER_OFF && val != PCI_SLOT_POWER_ON) + return OPAL_PARAMETER; + + hp_data = ent->platform_data; + slot_index = hp_data->slot_index; + hpc = hp_data->hp_controller; + + slot->power_state = val; + if (val == PCI_SLOT_POWER_ON) { + rc = hp_controller_enable(hpc, slot_index); + if (!rc) { + /* schedule to check state of PGOOD after 2s */ + init_timer(&hpc->slot_timer[slot_index], + timer_check_enable, slot); + schedule_timer(&hpc->slot_timer[slot_index], + msecs_to_tb(PGOOD_QUERY_WINDOW)); + pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_START); + rc = OPAL_ASYNC_COMPLETION; + } + } else { + rc = hp_controller_disable(hpc, slot_index); + } + return rc; +} + +static void rainier_get_slot_info(struct phb *phb, struct pci_device *pd) +{ + struct pci_slot *slot; + + if (!pd || pd->slot) + return; + + slot_table_get_slot_info(phb, pd); + if (!pd->slot) + return; + + slot = pd->slot; + if (!pd->parent && phb->slot) { + void (*tmp)(struct pci_slot *slot, struct dt_node *np); + /* + * For PHB slots, keep the ops of the PHB, except for + * add_properties, which was defined by the slot table + * framework and takes care of things like slot label, + * location, ... + */ + tmp = slot->ops.add_properties; + memcpy(&slot->ops, &phb->slot->ops, + sizeof(struct pci_slot_ops)); + slot->ops.add_properties = tmp; + } + + if (slot->data) { + /* slots defined in our slot table support power management */ + slot->ops.get_power_state = rainier_pci_slot_get_power_state; + slot->ops.set_power_state = rainier_pci_slot_set_power_state; + } +} + static void rainier_pci_probe_complete(void) { prlog(PR_DEBUG, "PLAT: checking power of PCI slots\n"); hp_controller_check_enable(&hp_controller_dcm0, -1); hp_controller_check_enable(&hp_controller_dcm1, -1); + + check_all_slot_table(); } static void rainier_init_slot_power(void) @@ -246,6 +399,7 @@ static void rainier_init_slot_power(void) static void rainier_init(void) { astbmc_init(); + slot_table_init(rainier_phb_table); rainier_init_slot_power(); } @@ -274,6 +428,7 @@ DECLARE_PLATFORM(rainier) = { .bmc = &bmc_plat_ast2600_openbmc, .cec_power_down = astbmc_ipmi_power_down, .cec_reboot = astbmc_ipmi_reboot, + .pci_get_slot_info = rainier_get_slot_info, .pci_probe_complete = rainier_pci_probe_complete, .elog_commit = ipmi_elog_commit, .exit = astbmc_exit, From patchwork Mon Oct 18 12:37:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Mon, 18 Oct 2021 12:37:52 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:50 +0200 Message-Id: <20211018123751.72794-6-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Pi1P2wtUwgwZ99idFy83Hw0fcQRD0SbJ X-Proofpoint-GUID: Pi1P2wtUwgwZ99idFy83Hw0fcQRD0SbJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_05,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180077 Subject: [Skiboot] [PATCH 5/6] zz: Rework PCI slots definition and hotplug control X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The ZZ platform reuses most of the P8, fsp-based system infrastructure for PCI slot definitions (firenze-pci, lxvpd). However the PCI hotplug controller hardware is different. We got lucky as the i2c bus definitions used on firenze were invalid on ZZ, so PCI hotplug control errors out nicely, as opposed to sending random i2c requests to an unsuspecting device. This patch defines an interface to the hotplug controller used on ZZ. It also provides the updated i2c information for each PCI slot. Signed-off-by: Frederic Barrat --- platforms/ibm-fsp/firenze-pci.c | 5 +- platforms/ibm-fsp/ibm-fsp.h | 1 + platforms/ibm-fsp/zz.c | 189 ++++++++++++++++++++++++++++++++ 3 files changed, 194 insertions(+), 1 deletion(-) diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c index 5fbbc2ff..08467632 100644 --- a/platforms/ibm-fsp/firenze-pci.c +++ b/platforms/ibm-fsp/firenze-pci.c @@ -969,7 +969,10 @@ void firenze_pci_get_slot_info(struct phb *phb, struct pci_device *pd) s = lxvpd_get_slot(slot); if (s) { lxvpd_extract_info(slot, s); - firenze_pci_slot_init(slot); + if (proc_gen == proc_gen_p9) + zz_pci_slot_init(slot); + else + firenze_pci_slot_init(slot); } } diff --git a/platforms/ibm-fsp/ibm-fsp.h b/platforms/ibm-fsp/ibm-fsp.h index bb191645..b5b61b56 100644 --- a/platforms/ibm-fsp/ibm-fsp.h +++ b/platforms/ibm-fsp/ibm-fsp.h @@ -31,6 +31,7 @@ extern void firenze_pci_get_slot_info(struct phb *phb, struct pci_device *pd); extern void firenze_pci_add_loc_code(struct dt_node *np, struct pci_device *pd); +void zz_pci_slot_init(struct pci_slot *slot); /* VPD support */ void vpd_iohub_load(struct dt_node *hub_node); diff --git a/platforms/ibm-fsp/zz.c b/platforms/ibm-fsp/zz.c index 493d6030..8ce3e936 100644 --- a/platforms/ibm-fsp/zz.c +++ b/platforms/ibm-fsp/zz.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -141,6 +142,193 @@ static void add_opencapi_dt_nodes(void) } } +#define UCD_GPIO_SELECT 0xFA +#define UCD_GPIO_CONFIG 0xFB + +struct hp_controller { + struct lock lock; + struct i2c_request req; +}; + +struct hp_controller ucd; + +struct zz_pci_slot_info { + uint8_t index; + const char *label; + uint8_t slave_addr; + uint8_t enable_port; + uint8_t pgood_port; +}; + +static struct zz_pci_slot_info zz_pci_slots[] = { + /* UCD 9090-0 */ + { 0x06, "C2", 0xC8, 0, 18 }, + { 0x07, "C3", 0xC8, 4, 22 }, + { 0x08, "C4", 0xC8, 5, 15 }, + { 0x09, "C5", 0xC8, 6, 16 }, + { 0x0A, "C6", 0xC8, 7, 17 }, + /* UCD 90120A-0 */ + { 0x0B, "C7", 0xD0, 0, 18 }, + { 0x0C, "C8", 0xD0, 1, 19 }, + { 0x0D, "C9", 0xD0, 4, 20 }, + { 0x0E, "C10", 0xD0, 5, 21 }, + { 0x0F, "C11", 0xD0, 6, 24 }, + { 0x10, "C12", 0xD0, 7, 25 }, +}; + +static struct zz_pci_slot_info *zz_get_slot_info(struct lxvpd_pci_slot *s) +{ + for (int i = 0; i < ARRAY_SIZE(zz_pci_slots); i++) { + if (zz_pci_slots[i].index == s->slot_index && + !strcmp(zz_pci_slots[i].label, s->label)) { + return &zz_pci_slots[i]; + } + } + return NULL; +} + +static void hp_controller_init(struct hp_controller *hpc) +{ + init_lock(&hpc->lock); + hpc->req.offset = 0; + hpc->req.offset_bytes = 1; + hpc->req.rw_len = 1; + hpc->req.timeout = 100; + hpc->req.bus = p8_i2c_find_bus_by_port(0, 2, 1); + if (!hpc->req.bus) { + prerror("PLAT: Unable to find PCI power controller I2C bus\n"); + return; + } +} + +static int64_t __ucd_op(struct hp_controller *hpc, enum i2c_operation op, + uint32_t addr, uint8_t port, uint8_t *state) +{ + int64_t rc; + + if (!hpc->req.bus) + return OPAL_HARDWARE; + + hpc->req.op = SMBUS_WRITE; + hpc->req.dev_addr = addr >> 1; + hpc->req.offset = UCD_GPIO_SELECT; + hpc->req.rw_buf = &port; + rc = i2c_request_sync(&hpc->req); + if (rc) + return rc; + + hpc->req.op = op; + hpc->req.dev_addr = addr >> 1; + hpc->req.offset = UCD_GPIO_CONFIG; + hpc->req.rw_buf = state; + return i2c_request_sync(&hpc->req); +} + +static int64_t ucd_read(struct hp_controller *hpc, uint32_t addr, + uint8_t port, uint8_t *state) +{ + return __ucd_op(hpc, SMBUS_READ, addr, port, state); +} + +static int64_t ucd_write(struct hp_controller *hpc, uint32_t addr, + uint8_t port, uint8_t state) +{ + return __ucd_op(hpc, SMBUS_WRITE, addr, port, &state); +} + +static int64_t hp_controller_read_state(struct hp_controller *hpc, + struct zz_pci_slot_info *info, + uint8_t *val) +{ + uint8_t enable, pgood; + int64_t rc; + + lock(&hpc->lock); + + rc = ucd_read(hpc, info->slave_addr, info->pgood_port, &pgood); + if (rc) + goto unlock_err; + + rc = ucd_read(hpc, info->slave_addr, info->enable_port, &enable); + if (rc) + goto unlock_err; + + unlock(&hpc->lock); + + *val = ((enable & 0xE) == 0xE) && ((pgood & 0xE) == 0x8); + return OPAL_SUCCESS; + +unlock_err: + unlock(&hpc->lock); + prerror("PLAT: Can't read the state of PCI slot %s, rc=%lld\n", + info->label, rc); + return rc; +} + +static int64_t hp_controller_write_state(struct hp_controller *hpc, + struct zz_pci_slot_info *info, + uint8_t val) +{ + uint8_t enable; + int64_t rc; + + if (val == PCI_SLOT_POWER_ON) + enable = 0x7; + else + enable = 0x3; + + lock(&hpc->lock); + rc = ucd_write(hpc, info->slave_addr, info->enable_port, enable); + unlock(&hpc->lock); + return rc; +} + +static int64_t zz_pci_slot_get_power_state(struct pci_slot *slot, uint8_t *val) +{ + struct lxvpd_pci_slot *s = slot->data; + struct zz_pci_slot_info *info = NULL; + + info = zz_get_slot_info(s); + if (!info) + return OPAL_PARAMETER; + + return hp_controller_read_state(&ucd, info, val); +} + +static int64_t zz_pci_slot_set_power_state(struct pci_slot *slot, + uint8_t val) +{ + struct lxvpd_pci_slot *s = slot->data; + struct zz_pci_slot_info *info = NULL; + + if (val != PCI_SLOT_POWER_OFF && val != PCI_SLOT_POWER_ON) + return OPAL_PARAMETER; + + info = zz_get_slot_info(s); + if (!info) + return OPAL_PARAMETER; + + slot->power_state = val; + return hp_controller_write_state(&ucd, info, val); +} + +void zz_pci_slot_init(struct pci_slot *slot) +{ + struct lxvpd_pci_slot *s = slot->data; + struct zz_pci_slot_info *info; + + slot->ops.add_properties = lxvpd_add_slot_properties; + + info = zz_get_slot_info(s); + if (!info) + return; /* Slot doesn't support power management */ + + prlog(PR_INFO, "PLAT: PCI slot %s supports power management\n", + info->label); + slot->ops.get_power_state = zz_pci_slot_get_power_state; + slot->ops.set_power_state = zz_pci_slot_set_power_state; +} + static bool zz_probe(void) { /* FIXME: make this neater when the dust settles */ @@ -179,6 +367,7 @@ static void zz_init(void) { ibm_fsp_init(); hservice_fsp_init(); + hp_controller_init(&ucd); } DECLARE_PLATFORM(zz) = { From patchwork Mon Oct 18 12:37:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1542588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Mon, 18 Oct 2021 12:37:53 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Mon, 18 Oct 2021 14:37:51 +0200 Message-Id: <20211018123751.72794-7-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211018123751.72794-1-fbarrat@linux.ibm.com> References: <20211018123751.72794-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 9zaxTHCtLyjN_F-wpDWCn8DyAyNloMdg X-Proofpoint-GUID: 9zaxTHCtLyjN_F-wpDWCn8DyAyNloMdg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_05,2021-10-14_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110180077 Subject: [Skiboot] [PATCH 6/6] core/pci: Go through a fundamental reset on hotplug X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch triggers a fundamental reset when hotplugging a slot on P9 and P10. It cleans up the host state and has the proper workarounds to train correctly and have a stable link. Signed-off-by: Frederic Barrat --- core/pci-opal.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/core/pci-opal.c b/core/pci-opal.c index aa375c6a..3cd354a2 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -811,12 +811,19 @@ out: phb_unlock(phb); } -static bool training_needed(struct pci_slot *slot) +static bool reset_needed(struct pci_slot *slot) { struct phb *phb = slot->phb; struct pci_device *pd = slot->pd; - /* only for opencapi slots for now */ + /* + * On P9 and P10, we go trough freset. The device is powering + * on and doesn't need it but on the host side, it's required + * to have the link train correctly + */ + if (phb->phb_type == phb_type_pcie_v4) + return true; + /* opencapi slots */ if (!pd && phb->phb_type == phb_type_npu_v2_opencapi) return true; return false; @@ -831,7 +838,7 @@ static void wait_for_link_up_and_rescan(struct pci_slot *slot) * fundamental reset. Other slots also need to be tested for * readiness */ - if (training_needed(slot)) { + if (reset_needed(slot)) { pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); rc = slot->ops.freset(slot); if (rc < 0) {