From patchwork Fri Feb 2 14:38:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luis Machado X-Patchwork-Id: 868598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-472531-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fJiRGMuJ"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zY03v4t4Kz9t20 for ; Sat, 3 Feb 2018 01:39:06 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=h0z0YWNz32m/ zjvKDVR3X6oPcPOC2FOmbyOaYon439um2ullDqF2KjV6uVU7W11PGoJmhEROMm2D mhZ/gwaJ7c4MmeBJfzv0HfyHyR3zQTSKqzrzjf0I/mChRnZdWgRCtOgfD5y02SEO Oh4xZySpHuGxr9Yo6L45X/ysu1tieVg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=7pqgMJJGq7VUQV+lrS gFErRAxO0=; b=fJiRGMuJkYzsA+FrrrqJuqTXnPMhK9x4rvMjzmgD8+I22mwpc8 PB9+5RDeaoU/WXs7vVk+5s/3lvAUCpGPlRG4JFiWj80RU/MQiORKAEEJS3bkokIB fJdpu4F8vYTeyBhxIpFVDPKNon/KPknLaYuCycK1HrdqZ5b7NjW3JELHY= Received: (qmail 123626 invoked by alias); 2 Feb 2018 14:38:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 123608 invoked by uid 89); 2 Feb 2018 14:38:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:3159, customer X-HELO: mail-qt0-f171.google.com Received: from mail-qt0-f171.google.com (HELO mail-qt0-f171.google.com) (209.85.216.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 02 Feb 2018 14:38:57 +0000 Received: by mail-qt0-f171.google.com with SMTP id s39so31108108qth.7 for ; Fri, 02 Feb 2018 06:38:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=J1LNmm8CVbpX7PKVMwxgkdtL3uJC7L/Emu6IBE1zJS0=; b=i+lsQgkWX2NOE8vXBEcGW9JNRTpsSlN/BNP/2x7BueoRJZwdx8kcJr+Cn2YxtyB5D6 G/LwEnov63G/QgkgHwiTX/oytA+gQ1RIZvo4TBna9DLK04ustt7KcnTRFnUjFLdwtWqs 1vRz3O3g/QGKuYlT2LHJv1q19MJkasl4Rwjht2WCaKvBM6PFv4OqV7LSQIGt3eeuQ21r MTnaFtUho+m0evaFJxCTQgZa5I5qKeDhEEkzw2S5gmHOPK+5E7DVkgbVoXXUTA0hRb+Z AzgkDsZSMQ7I51ATuKBr9doorX1iq6jNpy7nxTssPvXeP725criQpE1qGKfJxAGywNBd 0q5w== X-Gm-Message-State: AKwxytfIXJ4GTHWtNzsWkwIQwOTbsPdCeGDKHmgDg/YForX1IOwZ5BQD 4N33L89RsAVCHupdqOSIjcSUBbvkG3k= X-Google-Smtp-Source: AH8x227v/aNrJ2A+Yyut0WrwddkXWDkWre28c4oYc8tQYrfE819qQ7FaZybDZ7QuljxkGhRhIZ2Znw== X-Received: by 10.200.0.17 with SMTP id a17mr25608864qtg.46.1517582335193; Fri, 02 Feb 2018 06:38:55 -0800 (PST) Received: from localhost.localdomain ([177.180.105.91]) by smtp.gmail.com with ESMTPSA id q54sm1454639qtj.41.2018.02.02.06.38.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Feb 2018 06:38:54 -0800 (PST) From: Luis Machado To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, Richard.Earnshaw@arm.com Subject: [PATCH] Recognize a missed usage of a sbfiz instruction Date: Fri, 2 Feb 2018 12:38:07 -0200 Message-Id: <1517582287-9923-1-git-send-email-luis.machado@linaro.org> X-IsSubscribed: yes A customer reported the following missed opportunities to combine a couple instructions into a sbfiz. int sbfiz32 (int x) { return x << 29 >> 10; } long sbfiz64 (long x) { return x << 58 >> 20; } This gets converted to the following pattern: (set (reg:SI 98) (ashift:SI (sign_extend:SI (reg:HI 0 x0 [ xD.3334 ])) (const_int 6 [0x6]))) Currently, gcc generates the following: sbfiz32: lsl x0, x0, 29 asr x0, x0, 10 ret sbfiz64: lsl x0, x0, 58 asr x0, x0, 20 ret It could generate this instead: sbfiz32: sbfiz w0, w0, 19, 3 ret sbfiz64:: sbfiz x0, x0, 38, 6 ret The unsigned versions already generate ubfiz for the same code, so the lack of a sbfiz pattern may have been an oversight. This particular sbfiz pattern shows up in both CPU2006 (~ 80 hits) and CPU2017 (~ 280 hits). It's not a lot, but seems beneficial in any case. No significant performance differences, probably due to the small number of occurrences or cases outside hot areas. Regression-tested and bootstrapped ok on aarch64-linux. Validated with CPU2017 and CPU2006 runs. I thought i'd put this up for review. I know we're still not in development mode yet. 2018-02-02 Luis Machado gcc/ * config/aarch64/aarch64.md (*ashift_extv_bfiz): New pattern. * testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c: New test. --- gcc/config/aarch64/aarch64.md | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5a2a930..d336bf0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4828,6 +4828,19 @@ [(set_attr "type" "bfx")] ) +;; Match sbfiz pattern in a shift left + shift right operation. + +(define_insn "*ashift_extv_bfiz" + [(set (match_operand:GPI 0 "register_operand" "=r") + (ashift:GPI (sign_extract:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n") + (match_operand 3 "const_int_operand" "n")) + (match_operand 4 "const_int_operand" "n")))] + "UINTVAL (operands[2]) < " + "sbfiz\\t%0, %1, %4, %2" + [(set_attr "type" "bfx")] +) + ;; When the bit position and width of the equivalent extraction add up to 32 ;; we can use a W-reg LSL instruction taking advantage of the implicit ;; zero-extension of the X-reg. diff --git a/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c b/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c new file mode 100644 index 0000000..931f8f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* Check that a LSL followed by an ASR can be combined into a single SBFIZ + instruction. */ + +/* Using W-reg */ + +int +sbfiz32 (int x) +{ + return x << 29 >> 10; +} + +/* Using X-reg */ + +long +sbfiz64 (long x) +{ + return x << 58 >> 20; +} + +/* { dg-final { scan-assembler "sbfiz\tw" } } */ +/* { dg-final { scan-assembler "sbfiz\tx" } } */