From patchwork Wed Sep 22 10:31:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531189 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwRr67rzz9sW4 for ; Wed, 22 Sep 2021 21:04:56 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwRr4qsgz2ywc for ; Wed, 22 Sep 2021 21:04:56 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvjt5Bn4z2yJC; Wed, 22 Sep 2021 20:32:01 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB7N1012563; Wed, 22 Sep 2021 18:11:07 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:25 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source Date: Wed, 22 Sep 2021 18:31:07 +0800 Message-ID: <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB7N1012563 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" - There are two clock sources used to generate SD/SDIO clock, APLL clock and HCLK (200MHz). User can select which clock source should be used by configuring SCU310[8]. - The SD/SDIO clock divider selection table SCU310[30:28] is different between AST2600-A1 and AST2600-A2/A3. For AST2600-A1, 200MHz SD/SDIO clock cannot be gotten by the dividers in SCU310[30:28] if APLL is not the multiple of 200MHz and HCLK is 200MHz. For AST2600-A2/A3, a new divider, "1", is added and 200MHz SD/SDIO clock can be obtained by adopting HCLK as clock source and setting SCU310[30:28] to 3b'111. Signed-off-by: Chin-Ting Kuo --- drivers/clk/clk-ast2600.c | 69 ++++++++++++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index bc3be5f3eae1..a6778c18274a 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -168,6 +168,30 @@ static const struct clk_div_table ast2600_div_table[] = { { 0 } }; +static const struct clk_div_table ast2600_sd_div_a1_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2600_sd_div_a2_table[] = { + { 0x0, 2 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 1 }, + { 0 } +}; + /* For hpll/dpll/epll/mpll */ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) { @@ -424,6 +448,11 @@ static const char *const emmc_extclk_parent_names[] = { "mpll", }; +static const char *const sd_extclk_parent_names[] = { + "hclk", + "apll", +}; + static const char * const vclk_parent_names[] = { "dpll", "d1pll", @@ -523,18 +552,42 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; - /* SD/SDIO clock divider and gate */ - hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, - scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, - &aspeed_g6_clk_lock); + clk_hw_register_fixed_rate(NULL, "hclk", NULL, 0, 200000000); + + regmap_read(map, 0x310, &val); + hw = clk_hw_register_mux(dev, "sd_extclk_mux", + sd_extclk_parent_names, + ARRAY_SIZE(sd_extclk_parent_names), 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 8, 1, + 0, &aspeed_g6_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); - hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", - 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, - ast2600_div_table, - &aspeed_g6_clk_lock); + + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "sd_extclk_mux", + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, + 31, 0, &aspeed_g6_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); + + regmap_read(map, 0x14, &val); + /* AST2600-A2/A3 clock divisor is different from AST2600-A1 */ + if (((val & GENMASK(23, 16)) >> 16) >= 2) { + /* AST2600-A2/A3 */ + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, + ast2600_sd_div_a2_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + } else { + /* AST2600-A1 */ + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, + ast2600_sd_div_a1_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + } aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; /* MAC1/2 RMII 50MHz RCLK */ From patchwork Wed Sep 22 10:31:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwSS339qz9sW4 for ; Wed, 22 Sep 2021 21:05:28 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwSS1nY5z3096 for ; Wed, 22 Sep 2021 21:05:28 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvjt6158z2yJG; Wed, 22 Sep 2021 20:32:00 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB7kO012564; Wed, 22 Sep 2021 18:11:07 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:26 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 02/10] sdhci: aspeed: Add SDR50 support Date: Wed, 22 Sep 2021 18:31:08 +0800 Message-ID: <20210922103116.30652-3-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB7kO012564 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From the analog waveform analysis result, SD/SDIO controller of AST2600 cannot always work well with 200MHz. The upper bound stable frequency for SD/SDIO controller is 100MHz. Thus, SDR50 supported bit, instead of SDR104, in capability 2 register should be set in advance. Signed-off-by: Chin-Ting Kuo --- drivers/mmc/host/sdhci-of-aspeed.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index 6e4e132903a6..c6eaeb02e3f9 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -35,6 +35,8 @@ #define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26) /* SDIO{14,24} */ #define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1) +/* SDIO{14,24} */ +#define ASPEED_SDC_CAP2_SDR50 (1 * 32 + 0) struct aspeed_sdc { struct clk *clk; @@ -410,11 +412,17 @@ static int aspeed_sdhci_probe(struct platform_device *pdev) sdhci_get_of_property(pdev); if (of_property_read_bool(np, "mmc-hs200-1_8v") || + of_property_read_bool(np, "sd-uhs-sdr50") || of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V, true, slot); } + if (of_property_read_bool(np, "sd-uhs-sdr50")) { + aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR50, + true, slot); + } + if (of_property_read_bool(np, "sd-uhs-sdr104")) { aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104, true, slot); From patchwork Wed Sep 22 10:31:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwTL6M90z9ssP for ; Wed, 22 Sep 2021 21:06:14 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwTL5C4Cz2xtf for ; Wed, 22 Sep 2021 21:06:14 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvjy1BGCz2yKF; Wed, 22 Sep 2021 20:32:06 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB8xY012565; Wed, 22 Sep 2021 18:11:08 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:26 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device Date: Wed, 22 Sep 2021 18:31:09 +0800 Message-ID: <20210922103116.30652-4-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB8xY012565 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The maximum frequency for SD controller on AST2600 EVB is 100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property should be added and the driver will set the SDR50 supported bit in capability 2 register during probing stage. Signed-off-by: Chin-Ting Kuo --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index b7eb552640cb..4551dba499c2 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -280,6 +280,7 @@ &sdhci0 { status = "okay"; bus-width = <4>; + sd-uhs-sdr50; max-frequency = <100000000>; sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; @@ -292,6 +293,7 @@ &sdhci1 { status = "okay"; bus-width = <4>; + sd-uhs-sdr50; max-frequency = <100000000>; sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; From patchwork Wed Sep 22 10:31:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531193 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwTf39Svz9sW4 for ; Wed, 22 Sep 2021 21:06:30 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwTf2MV9z2yp2 for ; Wed, 22 Sep 2021 21:06:30 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvk15798z2yJN; Wed, 22 Sep 2021 20:32:09 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB8JN012566; Wed, 22 Sep 2021 18:11:08 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:26 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 04/10] mmc: Add invert flag for clock phase signedness Date: Wed, 22 Sep 2021 18:31:10 +0800 Message-ID: <20210922103116.30652-5-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB8JN012566 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The clock phase degree may be between -360 to 360. If the data signal is leading to the clock, the signedness of clock phase is postive, otherwise, the signedness is negative. Signed-off-by: Chin-Ting Kuo --- drivers/mmc/core/host.c | 10 ++++++---- include/linux/mmc/host.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index d4683b1d263f..c2de7cbc7838 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -214,14 +214,16 @@ static void mmc_retune_timer(struct timer_list *t) static void mmc_of_parse_timing_phase(struct device *dev, const char *prop, struct mmc_clk_phase *phase) { - int degrees[2] = {0}; + int degrees[4] = {0}; int rc; - rc = device_property_read_u32_array(dev, prop, degrees, 2); + rc = device_property_read_u32_array(dev, prop, degrees, 4); phase->valid = !rc; if (phase->valid) { - phase->in_deg = degrees[0]; - phase->out_deg = degrees[1]; + phase->inv_in_deg = degrees[0] ? true : false; + phase->in_deg = degrees[1]; + phase->inv_out_deg = degrees[2] ? true : false; + phase->out_deg = degrees[3]; } } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 0c0c9a0fdf57..3c13010683e0 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -82,7 +82,9 @@ struct mmc_ios { struct mmc_clk_phase { bool valid; + bool inv_in_deg; u16 in_deg; + bool inv_out_deg; u16 out_deg; }; From patchwork Wed Sep 22 10:31:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531194 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwVF4bmYz9sW4 for ; Wed, 22 Sep 2021 21:07:01 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwVF3dH0z3c6N for ; Wed, 22 Sep 2021 21:07:01 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkB45JCz2xWT; Wed, 22 Sep 2021 20:32:18 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB8vj012567; Wed, 22 Sep 2021 18:11:08 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:26 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 05/10] mmc: aspeed: Adjust delay taps calculation method Date: Wed, 22 Sep 2021 18:31:11 +0800 Message-ID: <20210922103116.30652-6-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB8vj012567 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" - The maximum tap delay may be slightly different on different platforms. It may also be different due to different SoC processes or different manufacturers. Thus, the maximum tap delay should be gotten from the device tree through max-tap-delay property. - The delay time for each tap is an absolute value which is independent of clock frequency. But, in order to combine this principle with "phase" concept, clock frequency is took into consideration during calculating delay taps. - The delay cell of eMMC device is non-uniform. The time period of the first tap is two times of others. - The clock phase degree range is from -360 to 360. But, if the clock phase signedness is negative, clock signal is output from the falling edge first by default and thus, clock signal is leading to data signal by 90 degrees at least. Signed-off-by: Chin-Ting Kuo --- drivers/mmc/host/sdhci-of-aspeed.c | 115 ++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c index c6eaeb02e3f9..739c9503a5ed 100644 --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -44,6 +44,7 @@ struct aspeed_sdc { spinlock_t lock; void __iomem *regs; + u32 max_tap_delay_ps; }; struct aspeed_sdhci_tap_param { @@ -63,6 +64,7 @@ struct aspeed_sdhci_tap_desc { struct aspeed_sdhci_phase_desc { struct aspeed_sdhci_tap_desc in; struct aspeed_sdhci_tap_desc out; + u32 nr_taps; }; struct aspeed_sdhci_pdata { @@ -158,43 +160,60 @@ aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc, } #define PICOSECONDS_PER_SECOND 1000000000000ULL -#define ASPEED_SDHCI_NR_TAPS 15 -/* Measured value with *handwave* environmentals and static loading */ -#define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253 +#define ASPEED_SDHCI_MAX_TAPS 15 + static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz, - int phase_deg) + bool invert, int phase_deg, u32 nr_taps) { u64 phase_period_ps; u64 prop_delay_ps; u64 clk_period_ps; - unsigned int tap; - u8 inverted; + u32 tap = 0; + struct aspeed_sdc *sdc = dev_get_drvdata(dev->parent); - phase_deg %= 360; + if (sdc->max_tap_delay_ps == 0) + return 0; - if (phase_deg >= 180) { - inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; - phase_deg -= 180; - dev_dbg(dev, - "Inverting clock to reduce phase correction from %d to %d degrees\n", - phase_deg + 180, phase_deg); - } else { - inverted = 0; + prop_delay_ps = sdc->max_tap_delay_ps / nr_taps; + clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); + + /* + * For ast2600, if clock phase degree is negative, clock signal is + * output from falling edge first by default. Namely, clock signal + * is leading to data signal by 90 degrees at least. + */ + if (invert) { + if (phase_deg >= 90) + phase_deg -= 90; + else + phase_deg = 0; } - prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS; - clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz); phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL); - tap = div_u64(phase_period_ps, prop_delay_ps); - if (tap > ASPEED_SDHCI_NR_TAPS) { + /* + * The delay cell is non-uniform for eMMC controller. + * The time period of the first tap is two times of others. + */ + if (nr_taps == 16 && phase_period_ps > prop_delay_ps * 2) { + phase_period_ps -= prop_delay_ps * 2; + tap++; + } + + tap += div_u64(phase_period_ps, prop_delay_ps); + if (tap > ASPEED_SDHCI_MAX_TAPS) { dev_dbg(dev, "Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n", - tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS); - tap = ASPEED_SDHCI_NR_TAPS; + tap, phase_deg, rate_hz, ASPEED_SDHCI_MAX_TAPS); + tap = ASPEED_SDHCI_MAX_TAPS; } - return inverted | tap; + if (invert) { + dev_info(dev, "invert the clock\n"); + tap |= ASPEED_SDHCI_TAP_PARAM_INVERT_CLK; + } + + return tap; } static void @@ -202,13 +221,19 @@ aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate, const struct mmc_clk_phase *phases, struct aspeed_sdhci_tap_param *taps) { + struct sdhci_host *host = dev->driver_data; + struct aspeed_sdhci *sdhci; + + sdhci = sdhci_pltfm_priv(sdhci_priv(host)); taps->valid = phases->valid; if (!phases->valid) return; - taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg); - taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg); + taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->inv_in_deg, + phases->in_deg, sdhci->phase_desc->nr_taps); + taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->inv_out_deg, + phases->out_deg, sdhci->phase_desc->nr_taps); } static void @@ -230,8 +255,8 @@ aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate) aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps); dev_dbg(dev, "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n", - taps->in & ASPEED_SDHCI_NR_TAPS, - taps->out & ASPEED_SDHCI_NR_TAPS, + taps->in & ASPEED_SDHCI_MAX_TAPS, + taps->out & ASPEED_SDHCI_MAX_TAPS, params->in_deg, params->out_deg, rate, host->timing); } @@ -493,6 +518,7 @@ static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, .enable_value = 3, }, + .nr_taps = 15, }, /* SDHCI/Slot 1 */ [1] = { @@ -506,6 +532,31 @@ static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = { .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN, .enable_value = 3, }, + .nr_taps = 15, + }, +}; + +static const struct aspeed_sdhci_phase_desc ast2600_emmc_phase[] = { + /* eMMC slot 0 */ + [0] = { + .in = { + .tap_mask = ASPEED_SDC_S0_PHASE_IN, + .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN, + .enable_value = 1, + }, + .out = { + .tap_mask = ASPEED_SDC_S0_PHASE_OUT, + .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN, + .enable_value = 3, + }, + + /* + * There are 15 taps recorded in AST2600 datasheet. + * But, actually, the time period of the first tap + * is two times of others. Thus, 16 tap is used to + * emulate this situation. + */ + .nr_taps = 16, }, }; @@ -515,10 +566,17 @@ static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = { .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase), }; +static const struct aspeed_sdhci_pdata ast2600_emmc_pdata = { + .clk_div_start = 1, + .phase_desc = ast2600_emmc_phase, + .nr_phase_descs = ARRAY_SIZE(ast2600_emmc_phase), +}; + static const struct of_device_id aspeed_sdhci_of_match[] = { { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, }, { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, }, { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, }, + { .compatible = "aspeed,ast2600-emmc", .data = &ast2600_emmc_pdata, }, { } }; @@ -562,6 +620,11 @@ static int aspeed_sdc_probe(struct platform_device *pdev) goto err_clk; } + ret = of_property_read_u32(pdev->dev.of_node, "max-tap-delay", + &sdc->max_tap_delay_ps); + if (ret) + sdc->max_tap_delay_ps = 0; + dev_set_drvdata(&pdev->dev, sdc); parent = pdev->dev.of_node; From patchwork Wed Sep 22 10:31:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwVY0vYFz9sW4 for ; Wed, 22 Sep 2021 21:07:17 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwVY01k7z3c8K for ; Wed, 22 Sep 2021 21:07:17 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkF02Mlz2yfb; Wed, 22 Sep 2021 20:32:20 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB8W3012568; Wed, 22 Sep 2021 18:11:08 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:27 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 06/10] arm: dts: aspeed: Change eMMC device compatible Date: Wed, 22 Sep 2021 18:31:12 +0800 Message-ID: <20210922103116.30652-7-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB8W3012568 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Since the eMMC device's delay parameters are different from the SD's, a new compatible should be used to distinguish between eMMC and SD device. Signed-off-by: Chin-Ting Kuo --- arch/arm/boot/dts/aspeed-g6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 1b47be1704f8..d083de1d6567 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -597,7 +597,7 @@ status = "disabled"; emmc: sdhci@1e750100 { - compatible = "aspeed,ast2600-sdhci"; + compatible = "aspeed,ast2600-emmc"; reg = <0x100 0x100>; sdhci,auto-cmd12; interrupts = ; From patchwork Wed Sep 22 10:31:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwXL1DKhz9ssP for ; Wed, 22 Sep 2021 21:08:50 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwXL0HHnz3cCX for ; Wed, 22 Sep 2021 21:08:50 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkf73cPz2yN6; Wed, 22 Sep 2021 20:32:42 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB9Ko012569; Wed, 22 Sep 2021 18:11:09 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:27 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 07/10] arm: dts: aspeed: Adjust clock phase parameter Date: Wed, 22 Sep 2021 18:31:13 +0800 Message-ID: <20210922103116.30652-8-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB9Ko012569 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Change clock phase degree for AST2600 EVB. These parameter has been verified with 100MHz clock frequency for eMMC and SD controllers. Signed-off-by: Chin-Ting Kuo --- arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts | 8 ++++++++ arch/arm/boot/dts/aspeed-ast2600-evb.dts | 9 ++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts index dd7148060c4a..2d83617dc436 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts @@ -13,3 +13,11 @@ }; /delete-node/ &sdc; + +&emmc_controller { + max-tap-delay = <706>; +}; + +&emmc { + clk-phase-mmc-hs200 = <0 13>, <1 103>; +}; diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 4551dba499c2..f728b9d9b4cf 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -143,13 +143,15 @@ &emmc_controller { status = "okay"; + /* Measured value with *handwave* environmentals and static loading */ + max-tap-delay = <736>; }; &emmc { non-removable; bus-width = <4>; max-frequency = <100000000>; - clk-phase-mmc-hs200 = <9>, <225>; + clk-phase-mmc-hs200 = <0 27>, <1 95>; }; &rtc { @@ -260,6 +262,7 @@ &sdc { status = "okay"; + max-tap-delay = <9000>; }; /* @@ -287,7 +290,7 @@ sdhci,wp-inverted; vmmc-supply = <&vcc_sdhci0>; vqmmc-supply = <&vccq_sdhci0>; - clk-phase-sd-hs = <7>, <200>; + clk-phase-uhs-sdr50 = <0 130>, <0 238>; }; &sdhci1 { @@ -300,5 +303,5 @@ sdhci,wp-inverted; vmmc-supply = <&vcc_sdhci1>; vqmmc-supply = <&vccq_sdhci1>; - clk-phase-sd-hs = <7>, <200>; + clk-phase-uhs-sdr50 = <0 130>, <0 130>; }; From patchwork Wed Sep 22 10:31:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwX25HBHz9sBB for ; Wed, 22 Sep 2021 21:08:34 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwX242MGz3blb for ; Wed, 22 Sep 2021 21:08:34 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkf3r3Zz2yJv; Wed, 22 Sep 2021 20:32:42 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB9Cp012570; Wed, 22 Sep 2021 18:11:09 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:27 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 08/10] arm: dts: ibm: Adjust clock phase parameter Date: Wed, 22 Sep 2021 18:31:14 +0800 Message-ID: <20210922103116.30652-9-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB9Cp012570 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" - Add max-tap-delay property for eMMC controller. - Change clock phase degree for AST2600 on IBM platforms. Signed-off-by: Chin-Ting Kuo --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 3 ++- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 3 ++- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 2efd70666738..eccb4749755a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -2824,6 +2824,7 @@ &emmc_controller { status = "okay"; + max-tap-delay = <1253>; }; &pinctrl_emmc_default { @@ -2832,7 +2833,7 @@ &emmc { status = "okay"; - clk-phase-mmc-hs200 = <210>, <228>; + clk-phase-mmc-hs200 = <1 124>, <1 141>; }; &fsim0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 6419c9762c0b..2138a8a10d6e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -299,6 +299,7 @@ &emmc_controller { status = "okay"; + max-tap-delay = <1253>; }; &pinctrl_emmc_default { @@ -307,7 +308,7 @@ &emmc { status = "okay"; - clk-phase-mmc-hs200 = <180>, <180>; + clk-phase-mmc-hs200 = <1 90>, <1 90>; }; &fsim0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index e39f310d55eb..7427809354cc 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -182,11 +182,12 @@ &emmc_controller { status = "okay"; + max-tap-delay = <1253>; }; &emmc { status = "okay"; - clk-phase-mmc-hs200 = <36>, <270>; + clk-phase-mmc-hs200 = <0 40>, <1 181>; }; &fsim0 { From patchwork Wed Sep 22 10:31:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwW82Q8Jz9sW4 for ; Wed, 22 Sep 2021 21:07:48 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwW81DkVz3c8h for ; Wed, 22 Sep 2021 21:07:48 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkM1nx5z2xtf; Wed, 22 Sep 2021 20:32:27 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB9WW012571; Wed, 22 Sep 2021 18:11:09 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:28 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 09/10] dt-bindings: mmc: aspeed: Add max-tap-delay property Date: Wed, 22 Sep 2021 18:31:15 +0800 Message-ID: <20210922103116.30652-10-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB9WW012571 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Add max-tap-delay proptery in order to record the maximum tap delay on different platforms. Signed-off-by: Chin-Ting Kuo --- Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml index 987b287f3bff..5bb66849df65 100644 --- a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml @@ -37,6 +37,9 @@ properties: clocks: maxItems: 1 description: The SD/SDIO controller clock gate + max-tap-delay: + maxItems: 1 + description: The maximum delay in picosecond for SD/SDIO controller patternProperties: "^sdhci@[0-9a-f]+$": From patchwork Wed Sep 22 10:31:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 1531197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HDwWS0wsMz9sBB for ; Wed, 22 Sep 2021 21:08:04 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HDwWS01Jbz3cC6 for ; Wed, 22 Sep 2021 21:08:04 +1000 (AEST) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chin-ting_kuo@aspeedtech.com; receiver=) Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HDvkQ3rXWz2ynm; Wed, 22 Sep 2021 20:32:30 +1000 (AEST) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 18MAB9WG012572; Wed, 22 Sep 2021 18:11:09 +0800 (GMT-8) (envelope-from chin-ting_kuo@aspeedtech.com) Received: from localhost.localdomain (192.168.10.9) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Sep 2021 18:31:28 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , Subject: [PATCH 10/10] dt-bindings: mmc: aspeed: Add a new compatible string Date: Wed, 22 Sep 2021 18:31:16 +0800 Message-ID: <20210922103116.30652-11-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.9] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 18MAB9WG012572 X-Mailman-Approved-At: Wed, 22 Sep 2021 21:04:50 +1000 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Add "aspeed,ast2600-emmc" compatible string for the sake of distinguishing between SD and eMMC device. Signed-off-by: Chin-Ting Kuo --- Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml index 5bb66849df65..41105cd104c6 100644 --- a/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml @@ -52,6 +52,7 @@ patternProperties: - aspeed,ast2400-sdhci - aspeed,ast2500-sdhci - aspeed,ast2600-sdhci + - aspeed,ast2600-emmc reg: maxItems: 1 description: The SDHCI registers