From patchwork Tue Sep 21 18:34:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 1530833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4HDVdk43fwz9sXV for ; Wed, 22 Sep 2021 04:42:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233516AbhIUSn3 (ORCPT ); Tue, 21 Sep 2021 14:43:29 -0400 Received: from lb2-smtp-cloud7.xs4all.net ([194.109.24.28]:51397 "EHLO lb2-smtp-cloud7.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233372AbhIUSn3 (ORCPT ); Tue, 21 Sep 2021 14:43:29 -0400 X-Greylist: delayed 431 seconds by postgrey-1.27 at vger.kernel.org; Tue, 21 Sep 2021 14:43:14 EDT Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud7.xs4all.net with ESMTPA id Skb8mlMr9pQdWSkbKmYt3s; Tue, 21 Sep 2021 20:34:42 +0200 From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Nicolas Saenz Julienne , Jim Quinlan , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v5 1/4] dt-bindings: interrupt-controller: Convert MSI controller to json-schema Date: Tue, 21 Sep 2021 20:34:12 +0200 Message-Id: <20210921183420.436-2-kettenis@openbsd.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210921183420.436-1-kettenis@openbsd.org> References: <20210921183420.436-1-kettenis@openbsd.org> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfIlpYFiGaSAXpAnocbCedhdc9w5ORcy16MbexeqrUt9heusGvQR0ct6u4W6KKa6LUSEWt+uhsEfl8afqN2dav/AIj6sBKWxbG9ZqBF2tlE9E5Cx5r8+k naUalhJp0zKsE4TOQhfQMFHq55Lrz/RM2X8AB6F8/si00+vAWZub9nXSB5WcskFXqtUc8+gzveqVg3FS/tOkXh3SJXBCSEGDaJ19KIYnKKvTosrJgAYNMQTC WtwbSAt3CAxnXztaa8/bOKIRxw/bU/8KYv+dhpEm4Dpv8nMqZW35oMSVOA7SzFJ/ms3uMI6ky/d6UB+aF7Hl0Zz/pqckuNfp7CPAT4E1k3EfhZ6E1/J1vioc 01RqHspf3sNw/DUSrTFNRhaWFi68u59GYc/BMiRuFDIUoznpmRo0/Kym8TegGcJPVtKwFnYu6HyVhOby9rXmGBTkYpUMUU4RFKwXfJslLRU1wUoYzSG67QcR +/e62w6eVOFfzYtaYOfXe1QkN3rAtfP2WplmzBd/vjcR6rSvjBwOCpDdVmfgEWzYuP+LghAvuLVz6cC/X2xhKL0P2ZVjvDqTRh4CdlDJW6VuHCMNkGoYjebQ ZLH8olt0tsweARdGIdcocruZubPsiQywSMPOn7cixe6mhQV1aT3d+lq2wks00hHAdPcaRDH5TbHNjjiAuYj34bzWCUXHQ2TgZXzz1rq13pzEZqQ4gNyFQihq 7PO/Cyy5m7EvFdT1qLmgvwaweeAQTmxp19tR6quO9gCIAunQ3LmrdrJkjQ91aTRxv2JffkD+JtDaK7IHhQdcRfHiyVxLNuB9MVL3wVJ0RS+j35CTGqTLTW61 wR3ISaGZteDGDJoOLDg6e1yEoV3z8A79nV7i9BuG+j2XiOzd7JtJrx5QLi5abA== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Split the MSI controller bindings from the MSI binding document into DT schema format using json-schema. Acked-by: Marc Zyngier Signed-off-by: Mark Kettenis --- .../interrupt-controller/msi-controller.yaml | 38 +++++++++++++++++++ .../bindings/pci/brcm,stb-pcie.yaml | 1 + .../bindings/pci/microchip,pcie-host.yaml | 1 + 3 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml new file mode 100644 index 000000000000..58d898d5b943 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSI controller + +maintainers: + - Marc Zyngier + +description: | + An MSI controller signals interrupts to a CPU when a write is made + to an MMIO address by some master. An MSI controller may feature a + number of doorbells. + +properties: + "#msi-cells": + description: | + The number of cells in an msi-specifier, required if not zero. + + Typically this will encode information related to sideband data, + and will not encode doorbells or payloads as these can be + configured dynamically. + + The meaning of the msi-specifier is defined by the device tree + binding of the specific MSI controller. + enum: [0, 1] + + msi-controller: + description: + Identifies the node as an MSI controller. + $ref: /schemas/types.yaml#/definitions/flag + +dependencies: + "#msi-cells": [ msi-controller ] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index b9589a0daa5c..1fe102743f82 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -88,6 +88,7 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index fb95c276a986..7b0776457178 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: From patchwork Tue Sep 21 18:34:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 1530835 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4HDVdr1qs1z9sXk for ; Wed, 22 Sep 2021 04:42:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233612AbhIUSne (ORCPT ); Tue, 21 Sep 2021 14:43:34 -0400 Received: from lb2-smtp-cloud7.xs4all.net ([194.109.24.28]:59415 "EHLO lb2-smtp-cloud7.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233522AbhIUSnb (ORCPT ); Tue, 21 Sep 2021 14:43:31 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud7.xs4all.net with ESMTPA id Skb8mlMr9pQdWSkbPmYt4s; Tue, 21 Sep 2021 20:34:48 +0200 From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Nicolas Saenz Julienne , Jim Quinlan , Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v5 2/4] dt-bindings: interrupt-controller: msi: Add msi-ranges property Date: Tue, 21 Sep 2021 20:34:13 +0200 Message-Id: <20210921183420.436-3-kettenis@openbsd.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210921183420.436-1-kettenis@openbsd.org> References: <20210921183420.436-1-kettenis@openbsd.org> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfCOvKz2df6lbTQqu+3Bzl6OQqAFL8doZ/jDcyRiIzdBreR3rp4pyYwYhBQrErzWcJET/cD3qEqXLVR35034HdpC4xi9pV8rEqfNTZWExb6eNoLKtc+d/ oj8X1qAWRjgBaqY/AwP+kjppW2QkzcDbHo8Kua8l5oaNhHOT+R1wzGwDLoVqNOrucIqm1KGlteDGMSMk6W4z2Urt+uAAl+ncwICjOpC8WF70pxD1RHI8WP4M a9+The1Ekb4MQ9o120gi79ST5HZoaaSQgrdTGLQWCLpoVkWOs33dgNCwcYILc/VCvc3wQGUCGTJaWns0SPzh6JO4s/a5t6T6wZtLI/vEvQvNiBLsPwZw0L89 WLMM6elSZzwAQDLWlT/F/JU+0o4O/Hjbn7Bmpds2Rn+8w9rbcdOiwNWRti9YHR/vaRbmPzC9Bg0Hnd1EaYRIrsfuPHp39zaSp4k2oR5O8JF0TjK64KKdNEJT Iuy0QV12WA3b1WswR85lfMOY2A//xhZpxGW59WmvBIHUfVLmX7Vql0cax0te4u53wOJqnsbMyIq9kuNDSY7+8QESHfczbzk6v9jzS9VWWgp1sFcKJ1+ZElmb 6lpRcckmpKVVYcfIvaDIvIX6xfsqd2jvuV4h+CLBQ/n1COnDtuXgOab6pn2rKkealROD+Y/jWKNJ9CAW36aQVz0apTjasW0RvuO4VxbVh4VsUCa6s/HO1rhm KNZBd3dUqedKenX5nwj+kUNUGSi30RKqcuZx71kbJnm7R24iyMFSxqOIl2sZ8HMrgt+VjoUX/tMBwe7XQ8W48jirGpZIiTeWNc8+6vWXRGMwHwX8Q7RC0A0F pFNHN+6rjB7GR02TwAl6XrQlQBplfkrTmzv5VLoNiJGqVxFpf+f7aGM7DxXzWw== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update the MSI controller binding to add an msi-ranges property that specifies how MSIs map onto regular interrupts on some other interrupt controller. Acked-by: Marc Zyngier Signed-off-by: Mark Kettenis --- .../bindings/interrupt-controller/msi-controller.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml index 58d898d5b943..449d6067ec88 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml @@ -32,6 +32,14 @@ properties: Identifies the node as an MSI controller. $ref: /schemas/types.yaml#/definitions/flag + msi-ranges: + description: + A list of tuples, where "phandle" is the + parent interrupt controller, "intspec" is the starting/base + interrupt specifier and "span" is the size of the + range. Multiple ranges can be provided. + $ref: /schemas/types.yaml#/definitions/phandle-array + dependencies: "#msi-cells": [ msi-controller ] From patchwork Tue Sep 21 18:34:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 1530838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4HDVdw2DKvz9sxS for ; Wed, 22 Sep 2021 04:42:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233668AbhIUSnh (ORCPT ); Tue, 21 Sep 2021 14:43:37 -0400 Received: from lb3-smtp-cloud7.xs4all.net ([194.109.24.31]:36409 "EHLO lb3-smtp-cloud7.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233592AbhIUSng (ORCPT ); Tue, 21 Sep 2021 14:43:36 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud7.xs4all.net with ESMTPA id Skb8mlMr9pQdWSkbVmYt60; Tue, 21 Sep 2021 20:34:53 +0200 From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Jim Quinlan , Nicolas Saenz Julienne , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v5 3/4] dt-bindings: pci: Add DT bindings for apple,pcie Date: Tue, 21 Sep 2021 20:34:14 +0200 Message-Id: <20210921183420.436-4-kettenis@openbsd.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210921183420.436-1-kettenis@openbsd.org> References: <20210921183420.436-1-kettenis@openbsd.org> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfOLUNauYebB14EKfYCcbtG7mcDuU16KBc//0aV3bOFb2jgIgXgskJmIcM2nFmWXZ/SOzVeFKGkQlulOTpX+CRgTIb97aEZi6Yz0xPD9zFnFpFp25ltSt 4osBgFMz/+r4zu8dfOxgL7+Pvjt1Pt2JL0ggeCcuPZ4Maksaj6UyiNh19CDQu5duRqBPiwr2L3S/KyM5L4leI88jcIzh80902pYaN/7UkKAPUERiMJzA/CiL 4NXjFjjYzWAYRyo/UQi1JffDojcUbjqPYxS5t6xUzOPmDeMEs4ew1BE9exe7E9ZkgNv0vmT+3w/pC8W75M0XnEoGH09ARjcnNggWnmHRbu/lnc2K9jU2Jw7X HXA89zy000nXDT3wsPBFoTZHJFuVgbHz6fvpHnm7yZC4BrfMm0q76mV/WZRr6n4SRU/HFE7hW+7wZs89dSv8O5a21FB7Zg+xTyAwXgvbY3vvKsmCTUvcjSK/ GWFyg+ms18hjCac2W7N9kDe6ZqzJRF8l6OO1d00izgu8E2pwj7hDLvjugGp/GKMPSNB9R3A1eTYHJ05/XQmAbj8Hh2OxIQaHzeD5kZLOE4FfkrEwZUcal9Yk s/QNYMQnHYkXKqfgxiwhANJMyl5om+s08NyzE6/MkvXQnO4WWaZnoV6wDhGvgKYquMgsdPcXsDaawGE7LLJ30wTbzhuDLU1XpofAqiLci+kXsqj6yqPI68si fqPgzRB0HybBJmB33lFgxjfityA/LzXw2jvjxpkfjhNg4pkYvxsq39G1oNiBa74SswNLyDd6K+Jg+NqdHMQFbCLEzlNHT9kSJA8rl+bmurSufNLajdyNJeVl AzkB5MSfA5rV7AOhn+9FNUCBQ6QQQvHqxTGzDMwy+0UjhxA4jRsgx1/kellpzA== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Apple PCIe host controller is a PCIe host controller with multiple root ports present in Apple ARM SoC platforms, including various iPhone and iPad devices and the "Apple Silicon" Macs. Acked-by: Marc Zyngier Signed-off-by: Mark Kettenis --- .../devicetree/bindings/pci/apple,pcie.yaml | 161 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml new file mode 100644 index 000000000000..f17a8fe39e6b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple PCIe host controller + +maintainers: + - Mark Kettenis + +description: | + The Apple PCIe host controller is a PCIe host controller with + multiple root ports present in Apple ARM SoC platforms, including + various iPhone and iPad devices and the "Apple Silicon" Macs. + The controller incorporates Synopsys DesigWare PCIe logic to + implements its root ports. But the ATU found on most DesignWare + PCIe host bridges is absent. + + All root ports share a single ECAM space, but separate GPIOs are + used to take the PCI devices on those ports out of reset. Therefore + the standard "reset-gpios" and "max-link-speed" properties appear on + the child nodes that represent the PCI bridges that correspond to + the individual root ports. + + MSIs are handled by the PCIe controller and translated into regular + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be + distributed over the root ports as the OS sees fit by programming + the PCIe controller's port registers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - const: apple,t8103-pcie + - const: apple,pcie + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 + items: + - const: config + - const: rc + - const: port0 + - const: port1 + - const: port2 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: + Interrupt specifiers, one for each root port. + minItems: 1 + maxItems: 3 + + msi-parent: true + + msi-ranges: + maxItems: 1 + + iommu-map: true + iommu-map-mask: true + +required: + - compatible + - reg + - reg-names + - bus-range + - interrupts + - msi-controller + - msi-parent + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &dart0 1 1>, + <0x200 &dart1 1 1>, + <0x300 &dart2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c6b8a720c0bc..30bea4042e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1694,6 +1694,7 @@ C: irc://chat.freenode.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c From patchwork Tue Sep 21 18:34:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 1530836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4HDVdt11yRz9t0Y for ; Wed, 22 Sep 2021 04:42:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233639AbhIUSng (ORCPT ); Tue, 21 Sep 2021 14:43:36 -0400 Received: from lb2-smtp-cloud7.xs4all.net ([194.109.24.28]:51397 "EHLO lb2-smtp-cloud7.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233600AbhIUSng (ORCPT ); Tue, 21 Sep 2021 14:43:36 -0400 X-Greylist: delayed 431 seconds by postgrey-1.27 at vger.kernel.org; Tue, 21 Sep 2021 14:43:14 EDT Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud7.xs4all.net with ESMTPA id Skb8mlMr9pQdWSkbamYt73; Tue, 21 Sep 2021 20:34:58 +0200 From: Mark Kettenis To: devicetree@vger.kernel.org Cc: maz@kernel.org, robin.murphy@arm.com, sven@svenpeter.dev, alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Rob Herring , Hector Martin , Bjorn Helgaas , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Jim Quinlan , Nicolas Saenz Julienne , Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v5 4/4] arm64: apple: Add PCIe node Date: Tue, 21 Sep 2021 20:34:15 +0200 Message-Id: <20210921183420.436-5-kettenis@openbsd.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210921183420.436-1-kettenis@openbsd.org> References: <20210921183420.436-1-kettenis@openbsd.org> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfHhQZ6AJi25iA7HphsHmJwim8Jvgsd9KkIPWji3RvlBIC8jLZYr7rslO9k7z7tmQrrwWHesyulwaXXRZ6DAF/SK3svoW/pvrIQV/YXd1rGrJxcSDm2M0 ZKHfHBR0+WX8j2SjgAf+twYv+Nb+sPTyX0fJsqa6oUJKE605ALB1YTdeCmbUAIk4XVQBMCva7mcAyf4ZgTSLQDmjmxpgC9b1WXqfIb3mYCIIu8o2eNrLhqyu h5hYAaycS/GcuGTqI5YP3dTTkhKdTWNpKcuVKKnMwNfAGhff3cCgYRPUlzvLlj8ys9AG8kjtXFxNmr3cfXRXMur+//WJOLxXwhiE8lLmN4DK3yeMdSudybAT oEO4pV9YQDiZWNjpAb7GexxGH+SRZXvZG8SfX86EDfY5yrbI+D+DhPejf5W/jMZGA2wZVo22m9zO5oKbFjNb68r204es1IzaErqdiM9J5sW8BqUUjrTcZqza hiNHZZdapii+cnn1hlOcJbWK+VMw0E2BkDdedpoZ2bLBS1nHkxz6sAfDHo16Ys5YgTZjWolIZqsXRW4WxiJ8tc+oZ02fzZcxTEDoWDS2GwOG/CzrCKXF3/r8 aOHbA+Gt2TjNFJdwDpu4uJJpOMYOL9acSRO9j0mF/xBWPhECREFW6ubbvgi2XGLjNF8NHUdtviQ7Zbk5JfEADiSTdnZfGOp1foON9iOqyYp0TuO1LWvcFq7Z eMxjW2QypkBKzEIhYwXTQLv5SntPN2+SwT0STb+w2c0EdqB6PLFAOLPVnkBRG4khCvzIxOX8XWqJtBnwlQDQIltJ9cJfCxTz4W0nxmym6ru+F/eCK9XSRPPP P+N0uiSFw4nN4Rl7mqe0iHF2OugQSiNyss66Z9UyQ58SaYdevEz6HiD79pKbpQ== Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add node corresponding to the apcie,t8103 node in the Apple device tree for the Mac mini (M1, 2020). Power domain references and DART (IOMMU) references are left out at the moment and will be added once the appropriate bindings have been settled upon. Acked-by: Marc Zyngier Signed-off-by: Mark Kettenis --- arch/arm64/boot/dts/apple/t8103.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 503a76fc30e6..10956859b4bb 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -214,5 +214,68 @@ pinctrl_smc: pinctrl@23e820000 { , ; }; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; };