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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id v28sm2140457wrv.93.2021.09.11.09.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:54:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 01/24] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Date: Sat, 11 Sep 2021 18:54:11 +0200 Message-Id: <20210911165434.531552-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Commit f1c671f96cb ("target/avr: Introduce basic CPU class object") added to target/avr/cpu.h: #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" #endif Remove the CONFIG_USER_ONLY definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Reported-by: Richard Henderson Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index ea14175ca55..5d70e34dd54 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -197,10 +197,7 @@ static const struct TCGCPUOps avr_tcg_ops = { .synchronize_from_tb = avr_cpu_synchronize_from_tb, .cpu_exec_interrupt = avr_cpu_exec_interrupt, .tlb_fill = avr_cpu_tlb_fill, - -#ifndef CONFIG_USER_ONLY .do_interrupt = avr_cpu_do_interrupt, -#endif /* !CONFIG_USER_ONLY */ }; static void avr_cpu_class_init(ObjectClass *oc, void *data) From patchwork Sat Sep 11 16:54:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526758 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Ijui4pww; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6Jnp6kPcz9sRf for ; Sun, 12 Sep 2021 02:57:34 +1000 (AEST) Received: from localhost ([::1]:32864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6Jo-0002Xt-NE for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 12:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6HB-0005yA-Ak for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:49 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6H9-00029m-UZ for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:49 -0400 Received: by mail-wr1-x432.google.com with SMTP id q11so7474347wrr.9 for ; Sat, 11 Sep 2021 09:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l8Jx1m6Bv2t518ZIG2TWOXwbWEoTAme9VK7NQaY4YX8=; b=Ijui4pwwSDnWn+fQzU5fqPxEPYikDpA7UqEtyu8LS57PXvEANIeHJyzhuIV/FBE5qS XH8lMhveBNWTsCBtmJO8wHOWGzCTnS5UDI14LBWe/0poaW+b9zmXExuF4A8TiFon6Gai /9y+ykbfWFJqbSxPx086kfyBnNG0Z6ARejVEaXb+NxEno82i2UuQhY9op/lrUDW1zGxj XK9wi0Be8+h8YiWc6nFW7SIGzCtRHX9qUYlGL1EGH5WvDBFDKi7ajaQhY05Xz2pUvEFl fbRb5zsiSXSTXm87HIRcNyDKVoD6Iv4BhS3W2Ovcgg5rzmPFYimWyAG3ZzqprjTS3QB/ sR1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=l8Jx1m6Bv2t518ZIG2TWOXwbWEoTAme9VK7NQaY4YX8=; b=ToU9NNHoADFRUAlHyusOcBfCfxwN2jcXQs/VUwOFUU613Y/cQHiqAGodaoS76EQB4Q J+e4UG7hT5LPy8nTI3Q12yYW/rWabgzIOPUeYTeNFJ87o4/EiIaYONiiQeta80VGGEbN j3lhfh3ehH76DiULu8e3GyD1N7nVK4tGRwFW84Zttd/5C1VfsVOHcrk+w9Mq0pjUWIVx v4hXZyuxpL3NUZIPAMPl7yLD3pc0oEVznrh1NOJcBYLQXiJhVpRA/F1R/9ylkW1oGZM3 GgC3/UX2qLdanrzbV1b1akg6gza8Dj5scztSLXRBI6JnTw5gcmLi6F559YU8kiHiXkRZ wzvg== X-Gm-Message-State: AOAM5300UEmr5wLLeJ+k9XHfMJWMN6mrLhKoWgSRSfMdQyia9e/Wi6yo ekw/NVgz9tEVo98D1+RdFG9O0ecFcZU= X-Google-Smtp-Source: ABdhPJxjG4Vw9A2AmqqadETnFDudHg2njHPeXmysELlJHmGr6U4eKEE+CnpufoS909QiU7V8dXvwmQ== X-Received: by 2002:a05:6000:1186:: with SMTP id g6mr3921013wrx.126.1631379286405; Sat, 11 Sep 2021 09:54:46 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id t64sm1932224wma.48.2021.09.11.09.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:54:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 02/24] target/i386: Restrict sysemu-only fpu_helper helpers Date: Sat, 11 Sep 2021 18:54:12 +0200 Message-Id: <20210911165434.531552-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict some sysemu-only fpu_helper helpers (see commit 83a3d9c7402: "i386: separate fpu_helper sysemu-only parts"). Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6c50d3ab4f1..c241bc183d2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1833,11 +1833,14 @@ void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); int cpu_get_pic_interrupt(CPUX86State *s); + +#ifndef CONFIG_USER_ONLY /* MSDOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); void fpu_check_raise_ferr_irq(CPUX86State *s); void cpu_set_ignne(void); void cpu_clear_ignne(void); +#endif /* mpx_helper.c */ void cpu_sync_bndcs_hflags(CPUX86State *env); From patchwork Sat Sep 11 16:54:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=B2cPwU6u; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6JlY1kXXz9sX3 for ; Sun, 12 Sep 2021 02:55:37 +1000 (AEST) Received: from localhost ([::1]:54278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6Hu-0006Ep-VH for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 12:55:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6HG-00069p-5y for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:54 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:39527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6HE-0002DD-Ql for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:53 -0400 Received: by mail-wr1-x434.google.com with SMTP id u15so1435460wru.6 for ; Sat, 11 Sep 2021 09:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NZvvlRpa8DC97DN+aH7Pj/vVpZZsHFPzTcOdAGwjWjs=; b=B2cPwU6uBkt0E42CdgO+HC0TFDfX0nWohCtyQyAdOmLaWPvG85p0ybjK7XLniieQGw bF2iZ0ClIKdO9zFCtX/jgvOMGVCahRf2pwWdVVxedz3CwbZCE6aOkSX8u7xmu26dBHKp ZG+Ts4twYkoNsuBRk6Q91jZsnC/oNDHZr7VG+gGqy6CPhnaSBc7zqJYRwGt7WEMeFO8S RfL0JFRrBcmaUQzGy2av0UEODKf508xnbxOWhRPDwRW6nXogk2jgUWkiuLpH4TrdnPJ0 y41EH7SSbgf0tEnZuuiAAxGrFLNexoUpvihIIJ/nhoOecAhFVIetWBkhGWVJ8m+y2f8h vYKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NZvvlRpa8DC97DN+aH7Pj/vVpZZsHFPzTcOdAGwjWjs=; b=7qHUwHHlF7VQ9hVO0pRJdiW2h2pBs3yrd5aENAbFK2BGKXASFUBA4BPGqAUVgx924X gWmGh3UAjYF6gfYNSpIbLYWyXb1idAetsUZEHS1qDUaTaGUOhRfHQ5IbFJNo/VsVNKjb uPOASs/Kkt0Ws7Vf6C0wGRY/Yg41RJMHln1jIpNCdOcGGgdPpTHRCkZU5wJf5HGhpoDi 3pgYQuWF0h+/deG515kB0Y7wiBXazztxZvOnzceAiHx6tsydhtFLO2vHYgM8M4u48v0x 1rd6y24joKFluy6FCDNcigrzTA3c1GT/XeAzBI0MmIZDOGN8t68BmUvhHQqIF1XH154P oBtg== X-Gm-Message-State: AOAM533BXKaJxcA81YRVcMazfppiB894luGI+aOVIW1O4UgqFH3w2GRB 742PR/rLruUblIKDFcOIBmSbM0CNzLE= X-Google-Smtp-Source: ABdhPJxT6i3ughafuEm8UkGbUNSWX88JY7+BJ9t4NGFnaML1XNt/KB3Wx91gTBGLZY+swQ6kz9VAvA== X-Received: by 2002:adf:de8a:: with SMTP id w10mr3802445wrl.388.1631379291288; Sat, 11 Sep 2021 09:54:51 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id y18sm2174002wrq.6.2021.09.11.09.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:54:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 03/24] target/i386: Simplify TARGET_X86_64 #ifdef'ry Date: Sat, 11 Sep 2021 18:54:13 +0200 Message-Id: <20210911165434.531552-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Merge two TARGET_X86_64 consecutive blocks. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 3ed20ca31d7..dee7bef68c6 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -929,9 +929,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, e2); env->eip = offset; } -#endif -#ifdef TARGET_X86_64 void helper_sysret(CPUX86State *env, int dflag) { int cpl, selector; @@ -984,7 +982,7 @@ void helper_sysret(CPUX86State *env, int dflag) DESC_W_MASK | DESC_A_MASK); } } -#endif +#endif /* TARGET_X86_64 */ /* real mode interrupt */ static void do_interrupt_real(CPUX86State *env, int intno, int is_int, From patchwork Sat Sep 11 16:54:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=X6FJpsz8; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6Jnf2rKdz9sRf for ; Sun, 12 Sep 2021 02:57:26 +1000 (AEST) Received: from localhost ([::1]:60364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6Jg-00024I-5k for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 12:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6HL-0006OF-VC for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:59 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:37828) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6HJ-0002G7-GG for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:54:59 -0400 Received: by mail-wr1-x431.google.com with SMTP id t8so2459030wrq.4 for ; Sat, 11 Sep 2021 09:54:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/LWud8OdJVFwV057VSOD2zPTsJ4r3xLQGTPSjELmcjM=; b=X6FJpsz8P9UaBk4Ir5VjesV9HtdzOe6FoBcBEeXquRqJSOJ8chVwUvdxm68nEy7m0l fuGm5aNCCHgRTo4adU2O8T8W3/hoIEMdli+mwAtPcmew6ggt5tuUfZ9c61CzHk6W+JUt +v88AnochnTIkM8JLgVNEv84pvX9yc8ZrL+8+WQ9TivgAthORajTZEcKb2rI2xRxHsB/ oTPFhFyeiGwQn5uQ4wZs/Kk1Vn07q5u/eQXlzYuYyPFIIAwHlKgxDUil/5Nw0oX2xcp4 B7w7R+Y2QC4hs0OiZytXGF4PbMgBU925uhwDT96Looy+k/JLbZaHmTCsj+gBTpnXzNf4 diPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/LWud8OdJVFwV057VSOD2zPTsJ4r3xLQGTPSjELmcjM=; b=GRHMFURtPHNT9Okanb7GRpbo71y9p0aUJtXkLn9pYtUhinXxa98RhTKVM8iYbgkDKI 4Tpfb+42684fih+6PD2zDK0pJhfWYEuF4PtWnqrM85Y0Knv4D/T7+w6Ppvy5cQgd790i c3lCV6sTLOfzNCeY+e0/NoDD4dhDR50zep23cYtOZ3zlaJ61cenoDUuxPxuX4JgsYTbG XlFE+scGgAG9np6kfPUodYVLcpDn2ofRzlvvCldIgLvTNtOzD6KM08jcHwUHGb/6Rie+ pSPjx5Tp0yVQAUXCVGLeMkVdMRXIj65buVJ77IqSdKN909Q2VAEIuTD/HMaEq/F7Q8Gs dbAQ== X-Gm-Message-State: AOAM530Ru2jny8IpxcA/IhUt7gF/u4KAXYLCWIi2o/+4b0ijOxuV3PqP fWKzmdFzZz0XDCqrOETDpS7NubUWvJw= X-Google-Smtp-Source: ABdhPJw4UMz4wjRHdKMg+A53oZ5IRnc56l7F5ybt7t41jI8B8J1cqOA+Xmv7ED79sbtY4nDeWEV4hw== X-Received: by 2002:adf:f0c7:: with SMTP id x7mr3858728wro.432.1631379296014; Sat, 11 Sep 2021 09:54:56 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id u25sm2019941wmj.10.2021.09.11.09.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:54:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 04/24] target/xtensa: Restrict do_transaction_failed() to sysemu Date: Sat, 11 Sep 2021 18:54:14 +0200 Message-Id: <20210911165434.531552-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The do_transaction_failed() is restricted to system emulation since commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops"). Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2345cb59c79..1e0cb1535ca 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -568,10 +568,12 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +#endif /* !CONFIG_USER_ONLY */ void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, From patchwork Sat Sep 11 16:54:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Wvx18w7O; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6JpT3Dylz9sRf for ; Sun, 12 Sep 2021 02:58:09 +1000 (AEST) Received: from localhost ([::1]:33964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6KN-0003Hb-7M for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 12:58:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60430) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6HQ-0006bC-8i for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:04 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:43701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6HO-0002JG-KW for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:03 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b6so7459963wrh.10 for ; Sat, 11 Sep 2021 09:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=82KmkOHInD6T32/MBrAXuGha1mEQ9aTunJA89epWqX8=; b=Wvx18w7OXDMt3qrFbOeAJi01TZPxs6nfyKUuc1WoZpxPbN0luw8v90VdrQP8WpXxvz 6D5Z9YN06NEuWYNUOWpOFtgRuqDO1ofR+8c8+Adrr6+lH7VpSjAm0RD4DBbToIWBKr4O EpcSnGgKKnBjDnbMAyv+l4tj6NyBAwt7kZEQqHtpu+mrJBg9lIUOHURWt8YNbjcNNekI PsSNkyj7HWyZhh+oo7qQKlSqTJicoQ4/diXt6kWUbicyX6LOYgdiLJtYaLWAv6sesqFI fyA3QIMa0d5w9reWvrevYuOFDJO4lqOdvEGSV6x/w/kKpfrEYL+7I47qZw+23ogphZX4 G4ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=82KmkOHInD6T32/MBrAXuGha1mEQ9aTunJA89epWqX8=; b=ObxQQVZpwP3LrnzhfeD1sQ+p5wcuBWre4tVK54W+PReRy6sSOIkcR7RyJX2sqdNdzz lRyM6YQxkAgxleN6p7/BtoNa7fwvi60ApJpEXphOBrCkiHuf+Uhq3h5BXnVzoA6HKiS8 vK9KGNoEnk6sbdBupLbT3ldiqrQoNGdAxWPuitFZDEnGMpH5pjjy8YrhjbD38JSdgxl8 WuOC7670JHzcbSiJ6WuLsU4WqkqxcOwl4c9ywL32qAayUehwQX0Q3JAO75ULFdf+SwzF BqHLGLatOLwG/9qpY70WAbd2BwFcITOBmjy5zLwqhNU6BEu7vi6Wg05MbgUZUTKxRz/9 KaSw== X-Gm-Message-State: AOAM530nT4u41Sl4w3iGrbBvhmB8DlW7Df49fy0R9TNCXnjX4RzuIKkR 8Nr8dJxk5ifiVR9EdFMhjj5b/+rzr4g= X-Google-Smtp-Source: ABdhPJyZOkeQqeD9Cha1QZ+au7oTLStFUBD5ohQ53fqgRfqQc/XFPWDiauSpdQuOdbGBK+hI2RSlpQ== X-Received: by 2002:a05:6000:7:: with SMTP id h7mr3871888wrx.134.1631379300719; Sat, 11 Sep 2021 09:55:00 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id k22sm2161065wrd.59.2021.09.11.09.54.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 05/24] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Date: Sat, 11 Sep 2021 18:54:15 +0200 Message-Id: <20210911165434.531552-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" do_interrupt() is sysemu specific. However due to some X86 specific hack, it is also used in user-mode emulation, which is why it couldn't be restricted to CONFIG_SOFTMMU (see the comment around added in commit 78271684719: "cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"). Keep the hack but rename the handler as fake_user_interrupt() and restrict do_interrupt() to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/tcg-cpu-ops.h | 22 ++++++++++++++-------- accel/tcg/cpu-exec.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 6 ++++-- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index eab27d0c030..6c7ab9600ba 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -37,14 +37,6 @@ struct TCGCPUOps { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); - /** - * @do_interrupt: Callback for interrupt handling. - * - * note that this is in general SOFTMMU only, but it actually isn't - * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it - * in the SOFTMMU section in general. - */ - void (*do_interrupt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -61,6 +53,20 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); #ifdef NEED_CPU_H +#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) + /** + * @fake_user_interrupt: Callback for 'fake exception' handling. + * + * Simulate 'fake exception' which will be handled outside the + * cpu execution loop (hack for x86 user mode). + */ + void (*fake_user_interrupt)(CPUState *cpu); +#else + /** + * @do_interrupt: Callback for interrupt handling. + */ + void (*do_interrupt)(CPUState *cpu); +#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU /** * @do_transaction_failed: Callback for handling failed memory transactions diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e5c0ccd1a2a..2838177e7f0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -651,8 +651,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->do_interrupt(cpu); -#endif + cc->tcg_ops->fake_user_interrupt(cpu); +#endif /* TARGET_I386 */ *ret = cpu->exception_index; cpu->exception_index = -1; return true; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 93a79a57415..04c35486a2f 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -73,9 +73,11 @@ static const struct TCGCPUOps x86_tcg_ops = { .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, .cpu_exec_interrupt = x86_cpu_exec_interrupt, - .do_interrupt = x86_cpu_do_interrupt, .tlb_fill = x86_cpu_tlb_fill, -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + .fake_user_interrupt = x86_cpu_do_interrupt, +#else + .do_interrupt = x86_cpu_do_interrupt, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526761 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id a6sm2017569wmb.7.2021.09.11.09.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 06/24] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:16 +0200 Message-Id: <20210911165434.531552-7-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.h | 2 +- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 5 ++--- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967b..4e993bd15bd 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -274,10 +274,10 @@ struct AlphaCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; -#endif void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4871ad0c0a6..93e16a2ffb4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,10 +218,10 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, - .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .tlb_fill = alpha_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .do_interrupt = alpha_cpu_do_interrupt, .do_transaction_failed = alpha_cpu_do_transaction_failed, .do_unaligned_access = alpha_cpu_do_unaligned_access, diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 4f56fe4d231..81550d9e2ff 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -293,7 +293,6 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } -#endif /* USER_ONLY */ void alpha_cpu_do_interrupt(CPUState *cs) { @@ -348,7 +347,6 @@ void alpha_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; -#if !defined(CONFIG_USER_ONLY) switch (i) { case EXCP_RESET: i = 0x0000; @@ -404,7 +402,6 @@ void alpha_cpu_do_interrupt(CPUState *cs) /* Switch to PALmode. */ env->flags |= ENV_FLAG_PAL_MODE; -#endif /* !USER_ONLY */ } bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -451,6 +448,8 @@ bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) { static const char linux_reg_names[31][4] = { From patchwork Sat Sep 11 16:54:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526762 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id u13sm2185968wrg.68.2021.09.11.09.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 07/24] target/arm: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:17 +0200 Message-Id: <20210911165434.531552-8-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 3 +-- target/arm/cpu.c | 7 +++++-- target/arm/cpu_tcg.c | 6 +++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6a987f65e41..cfd755cff99 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1040,11 +1040,10 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; -#endif void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); -bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d631c4683c4..ba0741b20e4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -440,6 +440,8 @@ static void arm_cpu_reset(DeviceState *dev) arm_rebuild_hflags(env); } +#ifndef CONFIG_USER_ONLY + static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el, unsigned int cur_el, bool secure, @@ -556,7 +558,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, return unmasked || pstate_unmasked; } -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); CPUARMState *env = cs->env_ptr; @@ -608,6 +610,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) cc->tcg_ops->do_interrupt(cs); return true; } +#endif /* !CONFIG_USER_ONLY */ void arm_cpu_update_virq(ARMCPU *cpu) { @@ -2010,11 +2013,11 @@ static const struct SysemuCPUOps arm_sysemu_ops = { static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt = arm_cpu_exec_interrupt, .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt = arm_cpu_exec_interrupt, .do_interrupt = arm_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 33cc75af57d..0d5adccf1a7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -22,7 +22,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -#ifdef CONFIG_TCG +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -46,7 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return ret; } -#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ static void arm926_initfn(Object *obj) { @@ -898,11 +898,11 @@ static void pxa270c5_initfn(Object *obj) static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .tlb_fill = arm_cpu_tlb_fill, .debug_excp_handler = arm_debug_excp_handler, #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, .do_interrupt = arm_v7m_cpu_do_interrupt, .do_transaction_failed = arm_cpu_do_transaction_failed, .do_unaligned_access = arm_cpu_do_unaligned_access, From patchwork Sat Sep 11 16:54:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=IDFzf7nG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6JtK0Z2lz9sRf for ; Sun, 12 Sep 2021 03:01:29 +1000 (AEST) Received: from localhost ([::1]:42500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6Na-0000VN-QT for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 13:01:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6He-0006t3-V7 for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:18 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:34623) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6Hd-0002Sw-Hc for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:18 -0400 Received: by mail-wr1-x434.google.com with SMTP id m9so7506204wrb.1 for ; Sat, 11 Sep 2021 09:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=geqo+TfqXlGgpu7vXFZNKLzFP6S151+7irB5AEU8QIk=; b=IDFzf7nGI4NuCEO7ATmtnY0sLQSx9mJ+m6h0qthylyFe9fRKnXhJZyGmu70yE4BFha QzHBfYILyFfZoBA6BxixN1JCdTafMXE6ivxR6cy7VMD8ICVvDRtbvWm82E+8a3EwyOn6 h4TeUxTSK0/LNBdbdnPU+nAtTJcwRtWUXppDGLihME9ybwl9kK/TsHhhNMqwKbrUj8f6 k04lLLdQYKFVa7fgT/gRWqGsW91+//PLhn9Sr7Eaaz9TWPo5YHZOb47XgDVttD6PPNmM 0NrifKSEio7vA6nC0QW8gaq8UjUUu7loPpE0SpNpKNiZGfbc9KzQMq67WzX8vNcp5KkL vf1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=geqo+TfqXlGgpu7vXFZNKLzFP6S151+7irB5AEU8QIk=; b=7M1TX2Yi9vOf5NubVHyi/LcwiAK5UKFtp8jnx9hsdDHTG0uUCXpYRFWYN79ScwZKg9 YIfAjyDp5EmnnTnFksb1caWqcXBPy9tx4omt7ILDRfq7/ibPCkCWdzTlw063lFUAzYDW 3yRTci1xJn/pBpnKvsqjXB2Hb1FZnITH6QItBi1OP0SJi1H7p8NlLDI7bCFvfuLFVLg9 wApAqlt0p3RD6b5BYJiubB9oWKYdrjI7rz2k5I5ilOEofb3gYIOqYs22aOUyyzLooDl4 E3k8qcXQIlrLKmUHnDJqGk3Y/tdoJLx37E6FMUVNtQlAWehBkrRrXk0X+duStTs8vAaw 7Lig== X-Gm-Message-State: AOAM533EonTx9yayarH0ivGT2qcSp1YRWJ66LU1Ks021vcCxDVotmpLR FwoQqCUqPwSxHtmib7n+dHF/sCD9Vrk= X-Google-Smtp-Source: ABdhPJw9bHA7HE3lakYAFtA/OMyqeWbPmJ+IZkvlG7vNkN+U9u9wIYJTE44598EPQR3/CnW6n7pBBg== X-Received: by 2002:adf:9d4b:: with SMTP id o11mr3836952wre.29.1631379316117; Sat, 11 Sep 2021 09:55:16 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id l124sm2023427wml.8.2021.09.11.09.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 08/24] target/cris: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:18 +0200 Message-Id: <20210911165434.531552-9-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/cris/cpu.h | 2 +- target/cris/cpu.c | 4 ++-- target/cris/helper.c | 17 ++--------------- 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..be021899ae8 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -185,11 +185,11 @@ struct CRISCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_cris_cpu; -#endif void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 70932b1f8c7..c2e7483f5bd 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -205,20 +205,20 @@ static const struct SysemuCPUOps cris_sysemu_ops = { static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, - .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = crisv10_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, - .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = cris_cpu_exec_interrupt, .do_interrupt = cris_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/cris/helper.c b/target/cris/helper.c index 911867f3b48..36926faf323 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -41,20 +41,6 @@ #if defined(CONFIG_USER_ONLY) -void cris_cpu_do_interrupt(CPUState *cs) -{ - CRISCPU *cpu = CRIS_CPU(cs); - CPUCRISState *env = &cpu->env; - - cs->exception_index = -1; - env->pregs[PR_ERP] = env->pc; -} - -void crisv10_cpu_do_interrupt(CPUState *cs) -{ - cris_cpu_do_interrupt(cs); -} - bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -287,7 +273,6 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy)); return phy; } -#endif bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -319,3 +304,5 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return ret; } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=h+NTPtwx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6JxN2QLBz9sRf for ; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id p13sm2102622wro.8.2021.09.11.09.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 09/24] target/hppa: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:19 +0200 Message-Id: <20210911165434.531552-10-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/hppa/cpu.h | 4 ++-- target/hppa/cpu.c | 2 +- target/hppa/int_helper.c | 7 ++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 748270bfa31..7854675b903 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -325,13 +325,13 @@ int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void hppa_cpu_do_interrupt(CPUState *cpu); -bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY +void hppa_cpu_do_interrupt(CPUState *cpu); +bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2eace4ee124..e8edd189bfc 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -144,10 +144,10 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, - .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .tlb_fill = hppa_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = hppa_cpu_exec_interrupt, .do_interrupt = hppa_cpu_do_interrupt, .do_unaligned_access = hppa_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 349495d3610..13073ae2bda 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -88,7 +88,6 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } -#endif /* !CONFIG_USER_ONLY */ void hppa_cpu_do_interrupt(CPUState *cs) { @@ -100,7 +99,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) uint64_t iasq_f = env->iasq_f; uint64_t iasq_b = env->iasq_b; -#ifndef CONFIG_USER_ONLY target_ureg old_psw; /* As documented in pa2.0 -- interruption handling. */ @@ -187,7 +185,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) env->iaoq_b = env->iaoq_f + 4; env->iasq_f = 0; env->iasq_b = 0; -#endif if (qemu_loglevel_mask(CPU_LOG_INT)) { static const char * const names[] = { @@ -248,7 +245,6 @@ void hppa_cpu_do_interrupt(CPUState *cs) bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#ifndef CONFIG_USER_ONLY HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; @@ -258,6 +254,7 @@ bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) hppa_cpu_do_interrupt(cs); return true; } -#endif return false; } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:20 2021 Content-Type: text/plain; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id t18sm2058786wrp.97.2021.09.11.09.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 10/24] target/i386: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:20 +0200 Message-Id: <20210911165434.531552-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/helper-tcg.h | 2 ++ target/i386/tcg/seg_helper.c | 10 ++-------- target/i386/tcg/tcg-cpu.c | 2 +- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 2510cc244e9..60ca09e95eb 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -38,7 +38,9 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); * @cpu: vCPU the interrupt is to be handled by. */ void x86_cpu_do_interrupt(CPUState *cpu); +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* helper.c */ bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index dee7bef68c6..13c6e6ee62e 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,6 +1110,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } +#ifndef CONFIG_USER_ONLY bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu = X86_CPU(cs); @@ -1125,23 +1126,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) * This is required to make icount-driven execution deterministic. */ switch (interrupt_request) { -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_POLL: cs->interrupt_request &= ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); break; -#endif case CPU_INTERRUPT_SIPI: do_cpu_sipi(cpu); break; case CPU_INTERRUPT_SMI: cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); cs->interrupt_request &= ~CPU_INTERRUPT_SMI; -#ifdef CONFIG_USER_ONLY - cpu_abort(CPU(cpu), "SMI interrupt: cannot enter SMM in user-mode"); -#else do_smm_enter(cpu); -#endif /* CONFIG_USER_ONLY */ break; case CPU_INTERRUPT_NMI: cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); @@ -1162,7 +1157,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) "Servicing hardware INT=0x%02x\n", intno); do_interrupt_x86_hardirq(env, intno, 1); break; -#if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_VIRQ: /* FIXME: this should respect TPR */ cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); @@ -1173,12 +1167,12 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) do_interrupt_x86_hardirq(env, intno, 1); cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; break; -#endif } /* Ensure that no TB jump will be modified as the program flow was changed. */ return true; } +#endif /* CONFIG_USER_ONLY */ void helper_lldt(CPUX86State *env, int selector) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 04c35486a2f..3ecfae34cb5 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -72,12 +72,12 @@ static const struct TCGCPUOps x86_tcg_ops = { .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, .cpu_exec_exit = x86_cpu_exec_exit, - .cpu_exec_interrupt = x86_cpu_exec_interrupt, .tlb_fill = x86_cpu_tlb_fill, #ifdef CONFIG_USER_ONLY .fake_user_interrupt = x86_cpu_do_interrupt, #else .do_interrupt = x86_cpu_do_interrupt, + .cpu_exec_interrupt = x86_cpu_exec_interrupt, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:21 2021 Content-Type: text/plain; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id s14sm1912541wmc.25.2021.09.11.09.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 11/24] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder Date: Sat, 11 Sep 2021 18:54:21 +0200 Message-Id: <20210911165434.531552-12-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Following the logic of commit 30493a030ff ("i386: split seg_helper into user-only and sysemu parts"), move x86_cpu_exec_interrupt() under sysemu/seg_helper.c. Reviewed-by: Richard Henderson Reviewed-By: Warner Losh Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.c | 64 ---------------------------- target/i386/tcg/sysemu/seg_helper.c | 65 +++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 64 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 13c6e6ee62e..baa905a0cd6 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } -#ifndef CONFIG_USER_ONLY -bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - X86CPU *cpu = X86_CPU(cs); - CPUX86State *env = &cpu->env; - int intno; - - interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request); - if (!interrupt_request) { - return false; - } - - /* Don't process multiple interrupt requests in a single call. - * This is required to make icount-driven execution deterministic. - */ - switch (interrupt_request) { - case CPU_INTERRUPT_POLL: - cs->interrupt_request &= ~CPU_INTERRUPT_POLL; - apic_poll_irq(cpu->apic_state); - break; - case CPU_INTERRUPT_SIPI: - do_cpu_sipi(cpu); - break; - case CPU_INTERRUPT_SMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); - cs->interrupt_request &= ~CPU_INTERRUPT_SMI; - do_smm_enter(cpu); - break; - case CPU_INTERRUPT_NMI: - cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); - cs->interrupt_request &= ~CPU_INTERRUPT_NMI; - env->hflags2 |= HF2_NMI_MASK; - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); - break; - case CPU_INTERRUPT_MCE: - cs->interrupt_request &= ~CPU_INTERRUPT_MCE; - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); - break; - case CPU_INTERRUPT_HARD: - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); - cs->interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); - intno = cpu_get_pic_interrupt(env); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - break; - case CPU_INTERRUPT_VIRQ: - /* FIXME: this should respect TPR */ - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); - intno = x86_ldl_phys(cs, env->vm_vmcb - + offsetof(struct vmcb, control.int_vector)); - qemu_log_mask(CPU_LOG_TB_IN_ASM, - "Servicing virtual hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - break; - } - - /* Ensure that no TB jump will be modified as the program flow was changed. */ - return true; -} -#endif /* CONFIG_USER_ONLY */ - void helper_lldt(CPUX86State *env, int selector) { SegmentCache *dt; diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index 82c0856c417..b425b930f9d 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -125,6 +125,71 @@ void x86_cpu_do_interrupt(CPUState *cs) } } +bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + int intno; + + interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request); + if (!interrupt_request) { + return false; + } + + /* + * Don't process multiple interrupt requests in a single call. + * This is required to make icount-driven execution deterministic. + */ + switch (interrupt_request) { + case CPU_INTERRUPT_POLL: + cs->interrupt_request &= ~CPU_INTERRUPT_POLL; + apic_poll_irq(cpu->apic_state); + break; + case CPU_INTERRUPT_SIPI: + do_cpu_sipi(cpu); + break; + case CPU_INTERRUPT_SMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); + cs->interrupt_request &= ~CPU_INTERRUPT_SMI; + do_smm_enter(cpu); + break; + case CPU_INTERRUPT_NMI: + cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); + cs->interrupt_request &= ~CPU_INTERRUPT_NMI; + env->hflags2 |= HF2_NMI_MASK; + do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); + break; + case CPU_INTERRUPT_MCE: + cs->interrupt_request &= ~CPU_INTERRUPT_MCE; + do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); + break; + case CPU_INTERRUPT_HARD: + cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); + cs->interrupt_request &= ~(CPU_INTERRUPT_HARD | + CPU_INTERRUPT_VIRQ); + intno = cpu_get_pic_interrupt(env); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing hardware INT=0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + break; + case CPU_INTERRUPT_VIRQ: + /* FIXME: this should respect TPR */ + cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); + intno = x86_ldl_phys(cs, env->vm_vmcb + + offsetof(struct vmcb, control.int_vector)); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing virtual hardware INT=0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + break; + } + + /* + * Ensure that no TB jump will be modified as the program flow was changed. + */ + return true; +} + /* check if Port I/O is allowed in TSS */ void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) { From patchwork Sat Sep 11 16:54:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526765 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id s15sm2142292wrb.22.2021.09.11.09.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 12/24] target/m68k: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:22 +0200 Message-Id: <20210911165434.531552-13-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 +- target/m68k/op_helper.c | 16 +++------------- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 997d588911c..550eb028b6e 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -166,8 +166,10 @@ struct M68kCPU { }; +#ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 72de6e97262..66d22d11895 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -515,10 +515,10 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, - .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .tlb_fill = m68k_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .do_interrupt = m68k_cpu_do_interrupt, .do_transaction_failed = m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d006d1cb3ea..5d624838ae6 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -24,18 +24,7 @@ #include "semihosting/semihost.h" #include "tcg/tcg.h" -#if defined(CONFIG_USER_ONLY) - -void m68k_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index = -1; -} - -static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) -{ -} - -#else +#if !defined(CONFIG_USER_ONLY) static void cf_rte(CPUM68KState *env) { @@ -516,7 +505,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, cpu_loop_exit(cs); } } -#endif bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -538,6 +526,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs = env_cpu(env); From patchwork Sat Sep 11 16:54:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526769 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id t6sm1964798wmj.12.2021.09.11.09.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 13/24] target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:23 +0200 Message-Id: <20210911165434.531552-14-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.h | 2 ++ target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 13 ++----------- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..40401c33b72 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -355,8 +355,10 @@ struct MicroBlazeCPU { }; +#ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); +#endif /* !CONFIG_USER_ONLY */ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72d8f2a0daa..15db277925f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -365,10 +365,10 @@ static const struct SysemuCPUOps mb_sysemu_ops = { static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, - .cpu_exec_interrupt = mb_cpu_exec_interrupt, .tlb_fill = mb_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = mb_cpu_exec_interrupt, .do_interrupt = mb_cpu_do_interrupt, .do_transaction_failed = mb_cpu_transaction_failed, .do_unaligned_access = mb_cpu_do_unaligned_access, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 20dbd673136..dd2aecd1d58 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -26,16 +26,6 @@ #if defined(CONFIG_USER_ONLY) -void mb_cpu_do_interrupt(CPUState *cs) -{ - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - CPUMBState *env = &cpu->env; - - cs->exception_index = -1; - env->res_addr = RES_ADDR_NONE; - env->regs[14] = env->pc; -} - bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -271,7 +261,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, return paddr; } -#endif bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -289,6 +278,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) From patchwork Sat Sep 11 16:54:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526760 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id h11sm2582477wrx.9.2021.09.11.09.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 14/24] target/mips: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:24 +0200 Message-Id: <20210911165434.531552-15-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/tcg-internal.h | 5 +++-- target/mips/cpu.c | 2 +- target/mips/tcg/exception.c | 18 ------------------ target/mips/tcg/sysemu/tlb_helper.c | 18 ++++++++++++++++++ target/mips/tcg/user/tlb_helper.c | 5 ----- 5 files changed, 22 insertions(+), 26 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219e..c7a77ddccdd 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -18,8 +18,6 @@ void mips_tcg_init(void); void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -41,6 +39,9 @@ static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, #if !defined(CONFIG_USER_ONLY) +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); + void mmu_init(CPUMIPSState *env, const mips_def_t *def); void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d426918291a..00e0c55d0e4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -539,10 +539,10 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, - .cpu_exec_interrupt = mips_cpu_exec_interrupt, .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 4fb8b00711d..7b3026b105b 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -86,24 +86,6 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_RESET] = "reset", [EXCP_SRESET] = "soft reset", diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index a150a014ec1..73254d19298 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -1339,6 +1339,24 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; } +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs = env_cpu(env); diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c index b835144b820..210c6d529ef 100644 --- a/target/mips/tcg/user/tlb_helper.c +++ b/target/mips/tcg/user/tlb_helper.c @@ -57,8 +57,3 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, raise_mmu_exception(env, address, access_type); do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } - -void mips_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index = EXCP_NONE; -} From patchwork Sat Sep 11 16:54:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526770 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id r129sm1979396wmr.7.2021.09.11.09.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 15/24] target/nios2: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:25 +0200 Message-Id: <20210911165434.531552-16-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 5e37defef80..947bb09bc1e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -127,6 +127,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) ncc->parent_realize(dev, errp); } +#ifndef CONFIG_USER_ONLY static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu = NIOS2_CPU(cs); @@ -140,7 +141,7 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } - +#endif /* !CONFIG_USER_ONLY */ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -219,10 +220,10 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, - .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .tlb_fill = nios2_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .do_interrupt = nios2_cpu_do_interrupt, .do_unaligned_access = nios2_cpu_do_unaligned_access, #endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526774 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FbiVsXj3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6K3h02LYz9sRf for ; Sun, 12 Sep 2021 03:09:36 +1000 (AEST) Received: from localhost ([::1]:40230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6VR-0001Ny-Pf for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 13:09:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6IJ-0007wh-07 for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:59 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:41808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6IH-0002yG-Ea for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:55:58 -0400 Received: by mail-wr1-x436.google.com with SMTP id w29so6731689wra.8 for ; Sat, 11 Sep 2021 09:55:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SlXQUNKS3c3ZKazmS/+w3RMtDhurrxUzxhSxeew26+k=; b=FbiVsXj3FAZx5ZjncQN9iEIfsVeLqeBuwOPoqI6UQ63fHO+/83LFAhS7XD3vY+Brzw Yqa0kWbTn545ks2TCE47BkEDx+3Kb3sVS4u/F6e4iZmu8Ez8h10W5Mjf3bx73dKDyhhm 16mWBuKeqNAFz6UCKmRBTDjjXYq/eQZ3PJX19S45DSQp71m218kuT3pdHVZvWGc7eGV/ XMUB9V5ujtfiBgDPgioFwIavDkZEFJ+wYRTvVKGk8YlZhslcngjh8YRqSq7gyZd/fo76 Wno12siEhYPLD3bpDAtPs9FlhcO9kGC926wkUbeUXViecJeJDvKLH+pevpAokEF5F04u z+Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SlXQUNKS3c3ZKazmS/+w3RMtDhurrxUzxhSxeew26+k=; b=B5GzVTPW4XoChu/G32tUZ6JPtKQzSaa7ryA0b6uLp+jpoIPXovioBn7yOzAzwLpXj2 n3SW39kuTqvmC23h3+cbcPrM0g9sQvpRy/ByscKGgtEvs7WSo3KZtbtXl050Lux4hgWw awzIlmI5hLWZ6UkChwjghTNyP/7WmrauNkW+TNpXE22iRKNoRGhJqFlJtZw17ez/fbNC ojKJM5pZkDK7VueUXQKWnUTP+gfKMGA1hEDeLua6DdOFbF9SDpoXeelUGZ1ZD31tzBm7 hiwvH0QFskFwKo1FIaFfS1F857aApSFNq510qMkr+mGP67shB7lsabbWHbwhInrLTZeg zvEw== X-Gm-Message-State: AOAM5314/hsHrP9/4xCdBnqLMGnc/rkyRTBjdL+eMq/a6QOhSGooSCTs U/p9QKhKPtEXaCD8AF8HdtKBW73Kmiw= X-Google-Smtp-Source: ABdhPJxK+oCZiehRlNPyQF2hLSkfA1CxPBnch9PQF5ryk0EIJOTHvHhl0uHXcZyP//yh8kc+sLuN2g== X-Received: by 2002:a5d:48c5:: with SMTP id p5mr3745013wrs.303.1631379355868; Sat, 11 Sep 2021 09:55:55 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id z19sm2369237wma.0.2021.09.11.09.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:55:55 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 16/24] target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:26 +0200 Message-Id: <20210911165434.531552-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu.h | 5 +++-- target/openrisc/cpu.c | 2 +- target/openrisc/interrupt.c | 2 -- target/openrisc/meson.build | 6 ++++-- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..be6df81a810 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -312,8 +312,6 @@ struct OpenRISCCPU { void cpu_openrisc_list(void); -void openrisc_cpu_do_interrupt(CPUState *cpu); -bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -331,6 +329,9 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *info); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; +void openrisc_cpu_do_interrupt(CPUState *cpu); +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index bd34e429ecb..27cb04152f9 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -186,10 +186,10 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, - .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .tlb_fill = openrisc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .do_interrupt = openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3eab771dcda..19223e3f25b 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -28,7 +28,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; int exception = cs->exception_index; @@ -96,7 +95,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } -#endif cs->exception_index = -1; } diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index 9774a583065..e445dec4a00 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -9,7 +9,6 @@ 'exception_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'interrupt.c', 'interrupt_helper.c', 'mmu.c', 'sys_helper.c', @@ -17,7 +16,10 @@ )) openrisc_softmmu_ss = ss.source_set() -openrisc_softmmu_ss.add(files('machine.c')) +openrisc_softmmu_ss.add(files( + 'interrupt.c', + 'machine.c', +)) target_arch += {'openrisc': openrisc_ss} target_softmmu_arch += {'openrisc': openrisc_softmmu_ss} From patchwork Sat Sep 11 16:54:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id v10sm2192763wrg.15.2021.09.11.09.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 17/24] target/ppc: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:27 +0200 Message-Id: <20210911165434.531552-18-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Acked-by: David Gibson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/cpu.h | 4 ++-- target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 21 +++------------------ 3 files changed, 6 insertions(+), 21 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 500205229c0..362e7c4c5c7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1254,8 +1254,6 @@ DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass, PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR) #endif /* CONFIG_USER_ONLY */ -void ppc_cpu_do_interrupt(CPUState *cpu); -bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -1271,6 +1269,8 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY +void ppc_cpu_do_interrupt(CPUState *cpu); +bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_do_system_reset(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ad7abc6041a..6aad01d1d3a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -9014,10 +9014,10 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, - .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .do_interrupt = ppc_cpu_do_interrupt, .cpu_exec_enter = ppc_cpu_exec_enter, .cpu_exec_exit = ppc_cpu_exec_exit, diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7b6ac16eef7..d7e32ee107e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -40,24 +40,8 @@ /*****************************************************************************/ /* Exception processing */ -#if defined(CONFIG_USER_ONLY) -void ppc_cpu_do_interrupt(CPUState *cs) -{ - PowerPCCPU *cpu = POWERPC_CPU(cs); - CPUPPCState *env = &cpu->env; +#if !defined(CONFIG_USER_ONLY) - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; -} - -static void ppc_hw_interrupt(CPUPPCState *env) -{ - CPUState *cs = env_cpu(env); - - cs->exception_index = POWERPC_EXCP_NONE; - env->error_code = 0; -} -#else /* defined(CONFIG_USER_ONLY) */ static inline void dump_syscall(CPUPPCState *env) { qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 @@ -1113,7 +1097,6 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) powerpc_set_excp_state(cpu, vector, msr); } -#endif /* !CONFIG_USER_ONLY */ bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -1130,6 +1113,8 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + #if defined(DEBUG_OP) static void cpu_dump_rfi(target_ulong RA, target_ulong msr) { From patchwork Sat Sep 11 16:54:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id j17sm2113722wrh.67.2021.09.11.09.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 18/24] target/riscv: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:28 +0200 Message-Id: <20210911165434.531552-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Bin Meng , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 5 ----- 3 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00b..e735e53e26c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -334,7 +334,6 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); @@ -362,6 +361,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579c..13575c14085 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -644,10 +644,10 @@ static const struct SysemuCPUOps riscv_sysemu_ops = { static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, .do_unaligned_access = riscv_cpu_do_unaligned_access, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f4..701858d670c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,11 +75,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) return RISCV_EXCP_NONE; /* indicates no pending interrupt */ } } -#endif bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { -#if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_HARD) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; @@ -90,12 +88,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return true; } } -#endif return false; } -#if !defined(CONFIG_USER_ONLY) - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { From patchwork Sat Sep 11 16:54:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526771 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Jj3pZJub; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id q128sm2415301wma.27.2021.09.11.09.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 19/24] target/sh4: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:29 +0200 Message-Id: <20210911165434.531552-20-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h | 4 ++-- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 9 ++------- 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c43440822..017a7702140 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,8 +204,6 @@ struct SuperHCPU { }; -void superh_cpu_do_interrupt(CPUState *cpu); -bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -223,6 +221,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void sh4_cpu_list(void); #if !defined(CONFIG_USER_ONLY) +void superh_cpu_do_interrupt(CPUState *cpu); +bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 83269229421..2047742d03c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -236,10 +236,10 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, - .cpu_exec_interrupt = superh_cpu_exec_interrupt, .tlb_fill = superh_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = superh_cpu_exec_interrupt, .do_interrupt = superh_cpu_do_interrupt, .do_unaligned_access = superh_cpu_do_unaligned_access, .io_recompile_replay_branch = superh_io_recompile_replay_branch, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 2d622081e85..53cb9c3b631 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -45,11 +45,6 @@ #if defined(CONFIG_USER_ONLY) -void superh_cpu_do_interrupt(CPUState *cs) -{ - cs->exception_index = -1; -} - int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) { /* For user mode, only U0 area is cacheable. */ @@ -784,8 +779,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) return 0; } -#endif - bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -803,6 +796,8 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) From patchwork Sat Sep 11 16:54:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526768 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id s14sm1913896wmc.25.2021.09.11.09.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 20/24] target/sparc: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:30 +0200 Message-Id: <20210911165434.531552-21-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index da6b30ec747..5a8a4ce7506 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -77,6 +77,7 @@ static void sparc_cpu_reset(DeviceState *dev) env->cache_control = 0; } +#ifndef CONFIG_USER_ONLY static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { if (interrupt_request & CPU_INTERRUPT_HARD) { @@ -96,6 +97,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } +#endif /* !CONFIG_USER_ONLY */ static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -863,10 +865,10 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, - .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .tlb_fill = sparc_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = sparc_cpu_exec_interrupt, .do_interrupt = sparc_cpu_do_interrupt, .do_transaction_failed = sparc_cpu_do_transaction_failed, .do_unaligned_access = sparc_cpu_do_unaligned_access, From patchwork Sat Sep 11 16:54:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526772 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=WjS0v/rx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H6K1G5Hpdz9sX3 for ; Sun, 12 Sep 2021 03:07:30 +1000 (AEST) Received: from localhost ([::1]:33648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mP6TQ-0005Kd-Ey for incoming@patchwork.ozlabs.org; Sat, 11 Sep 2021 13:07:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mP6Ii-0000Zg-8B for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:56:24 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:40522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mP6Ig-0003ER-Gg for qemu-devel@nongnu.org; Sat, 11 Sep 2021 12:56:23 -0400 Received: by mail-wr1-x433.google.com with SMTP id q26so7485355wrc.7 for ; Sat, 11 Sep 2021 09:56:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LgdMlt85/dxzemJRBccypcQeoOnrjCkyjoaKtxyctHU=; b=WjS0v/rxBHXUPYr5wth/E07YrNDAdjzyOoN4SIkxY89P7Rql/I2031v/UsWXEpSBdO D3Nwzd4B0HOrcFgIxf6TlVWczAuw6ewV0Xd6MO7bQfxJeVtyocs0ia8Rh9D1xbRsLHw1 MFDaDIvW3Ypmk2VtvDw+czWR0HJc8PW6gAPO1L8s5eg3IrMMt8bHC6X6jEng6oLHbtmf PUvSxgut89KyQqWdgfCPAXrnPOfVU7YERIvAkwu09Zu57wghO7ipwq+UUfYB4i3bIBGt /EUi/BNvFnvBBg05nQoDZudUmU1OcqbSjnOJTjC+3AMbyqgaN3MKF90+X1Dbx9abLkJp d9ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LgdMlt85/dxzemJRBccypcQeoOnrjCkyjoaKtxyctHU=; b=kO14j0zCyQsvYuTP7ohFKYmvS43NtTbcEF2Yyp61aUBpW9PuXJevV03qqUTZoCf43+ gFz8qqqAHOUzpvmQtaZCOss7tE2DKAj+NWiHnHGuFGkezstWhHlShKk/4bNyaijrdrbr sNxXDQsz5h2iqwdkyIK5jf306uWrJY41y/G9IO68Q3jU+dtGafvOOG1dTwaFhRSupUJG CR3JG3MRxszipBUT000ghnwHW7F/yBVixy9HdmweDN2VLkxEfvltotaKTFULc10xOfmK rIBe9s467GBiVkAXXaGU+FTQiUoSTfKgz8KPP0BDQwYwKiTHPYygk3b2iotaqlW4Sj+d 7rvw== X-Gm-Message-State: AOAM530VQFPBRPxzM273EIaJyjyCKV4LQc0HyC28EJYC/sCW2y1jj2U2 zcvYq6lRolyHst6Y5RQ0nciILWgNc/E= X-Google-Smtp-Source: ABdhPJywD5PAv6XlZ8uXz9X/9boNg/g3aBR9udAqB8ATQ4FClYXNJ05s4ZY3yNtGfuf+WWV5c5QSww== X-Received: by 2002:adf:dd01:: with SMTP id a1mr1956926wrm.132.1631379380999; Sat, 11 Sep 2021 09:56:20 -0700 (PDT) Received: from x1w.. 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id n1sm2087494wrp.49.2021.09.11.09.56.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 21/24] target/rx: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:31 +0200 Message-Id: <20210911165434.531552-22-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.h | 2 ++ target/rx/cpu.c | 2 +- target/rx/helper.c | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..faa3606f52f 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -124,8 +124,10 @@ typedef RXCPU ArchCPU; #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); +#ifndef CONFIG_USER_ONLY void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); +#endif /* !CONFIG_USER_ONLY */ void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 96cc96e514f..25a4aa2976d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -186,10 +186,10 @@ static const struct SysemuCPUOps rx_sysemu_ops = { static const struct TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, - .cpu_exec_interrupt = rx_cpu_exec_interrupt, .tlb_fill = rx_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = rx_cpu_exec_interrupt, .do_interrupt = rx_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/rx/helper.c b/target/rx/helper.c index db6b07e3890..f34945e7e2c 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -40,6 +40,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) env->psw_c = FIELD_EX32(psw, PSW, C); } +#ifndef CONFIG_USER_ONLY + #define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { @@ -142,6 +144,8 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) return false; } +#endif /* !CONFIG_USER_ONLY */ + hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { return addr; From patchwork Sat Sep 11 16:54:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id i5sm2142844wrc.86.2021.09.11.09.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 22/24] target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu Date: Sat, 11 Sep 2021 18:54:32 +0200 Message-Id: <20210911165434.531552-23-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Restrict cpu_exec_interrupt() and its callees to sysemu. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 4 ++-- target/xtensa/cpu.c | 2 +- target/xtensa/exc_helper.c | 7 ++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 1e0cb1535ca..cbb720e7cca 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -566,14 +566,14 @@ struct XtensaCPU { bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); -#ifndef CONFIG_USER_ONLY void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); -#endif /* !CONFIG_USER_ONLY */ +#endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 58ec3a08622..c1cbd03595e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -192,11 +192,11 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, - .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .tlb_fill = xtensa_cpu_tlb_fill, .debug_excp_handler = xtensa_breakpoint_handler, #ifndef CONFIG_USER_ONLY + .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, .do_unaligned_access = xtensa_cpu_do_unaligned_access, diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 10e75ab070d..9bc7f50d355 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -255,11 +255,6 @@ void xtensa_cpu_do_interrupt(CPUState *cs) } check_interrupts(env); } -#else -void xtensa_cpu_do_interrupt(CPUState *cs) -{ -} -#endif bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -270,3 +265,5 @@ bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return false; } + +#endif /* !CONFIG_USER_ONLY */ From patchwork Sat Sep 11 16:54:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526773 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=e+qje1cu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id g9sm2082333wmg.21.2021.09.11.09.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:30 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 23/24] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu Date: Sat, 11 Sep 2021 18:54:33 +0200 Message-Id: <20210911165434.531552-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code. Move its declaration to restrict it to system emulation. Extend the code guarded. Restrict the static inlined need_replay_interrupt() method to avoid a "defined but not used" warning. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/tcg-cpu-ops.h | 4 ++-- accel/tcg/cpu-exec.c | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 6c7ab9600ba..55123cb4d22 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -35,8 +35,6 @@ struct TCGCPUOps { void (*cpu_exec_enter)(CPUState *cpu); /** @cpu_exec_exit: Callback for cpu_exec cleanup */ void (*cpu_exec_exit)(CPUState *cpu); - /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * @@ -68,6 +66,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_SOFTMMU + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2838177e7f0..75dbc1e4e33 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -685,6 +685,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) return false; } +#ifndef CONFIG_USER_ONLY /* * CPU_INTERRUPT_POLL is a virtual event which gets converted into a * "real" interrupt event later. It does not need to be recorded for @@ -698,12 +699,11 @@ static inline bool need_replay_interrupt(int interrupt_request) return true; #endif } +#endif /* !CONFIG_USER_ONLY */ static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { - CPUClass *cc = CPU_GET_CLASS(cpu); - /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or @@ -725,6 +725,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } +#if !defined(CONFIG_USER_ONLY) if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) { /* Do nothing */ } else if (interrupt_request & CPU_INTERRUPT_HALT) { @@ -753,12 +754,14 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qemu_mutex_unlock_iothread(); return true; } -#endif +#endif /* !TARGET_I386 */ /* The target hook has 3 exit conditions: False when the interrupt isn't processed, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { + CPUClass *cc = CPU_GET_CLASS(cpu); + if (cc->tcg_ops->cpu_exec_interrupt && cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { @@ -777,6 +780,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request = cpu->interrupt_request; } +#endif /* !CONFIG_USER_ONLY */ if (interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as From patchwork Sat Sep 11 16:54:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1526776 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=FC9yc79m; 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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id l3sm1977278wms.4.2021.09.11.09.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 09:56:36 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 24/24] user: Remove cpu_get_pic_interrupt() stubs Date: Sat, 11 Sep 2021 18:54:34 +0200 Message-Id: <20210911165434.531552-25-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210911165434.531552-1-f4bug@amsat.org> References: <20210911165434.531552-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Warner Losh Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" cpu_get_pic_interrupt() is now unreachable from user-mode, delete the unnecessary stubs. Reviewed-by: Warner Losh Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 2 +- bsd-user/i386/target_arch_cpu.c | 5 ----- bsd-user/x86_64/target_arch_cpu.c | 5 ----- linux-user/main.c | 7 ------- 4 files changed, 1 insertion(+), 18 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c241bc183d2..c7cc65e92d5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1832,9 +1832,9 @@ int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); +#ifndef CONFIG_USER_ONLY int cpu_get_pic_interrupt(CPUX86State *s); -#ifndef CONFIG_USER_ONLY /* MSDOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); void fpu_check_raise_ferr_irq(CPUX86State *s); diff --git a/bsd-user/i386/target_arch_cpu.c b/bsd-user/i386/target_arch_cpu.c index 71998e5ba56..d349e452997 100644 --- a/bsd-user/i386/target_arch_cpu.c +++ b/bsd-user/i386/target_arch_cpu.c @@ -33,11 +33,6 @@ uint64_t cpu_get_tsc(CPUX86State *env) return cpu_get_host_ticks(); } -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} - void bsd_i386_write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags) { diff --git a/bsd-user/x86_64/target_arch_cpu.c b/bsd-user/x86_64/target_arch_cpu.c index db822e54c66..be7bd107200 100644 --- a/bsd-user/x86_64/target_arch_cpu.c +++ b/bsd-user/x86_64/target_arch_cpu.c @@ -33,11 +33,6 @@ uint64_t cpu_get_tsc(CPUX86State *env) return cpu_get_host_ticks(); } -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} - void bsd_x86_64_write_dt(void *ptr, unsigned long addr, unsigned long limit, int flags) { diff --git a/linux-user/main.c b/linux-user/main.c index a6094563b6b..45bde4598d5 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -120,13 +120,6 @@ const char *qemu_uname_release; by remapping the process stack directly at the right place */ unsigned long guest_stack_size = 8 * 1024 * 1024UL; -#if defined(TARGET_I386) -int cpu_get_pic_interrupt(CPUX86State *env) -{ - return -1; -} -#endif - /***********************************************************/ /* Helper routines for implementing atomic operations. */