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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: From: Andrea Zanotti Added support for P8P Parallel Phase Change Memory. Added memory information (page size and sector size) as per data- sheet information, after typos corrections. Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:52a listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [andreazanottifo[at]gmail.com] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Andrea Zanotti Added support for P8P Parallel Phase Change Memory. Added memory information (page size and sector size) as per data- sheet information, after typos corrections. At page 37, paragraph 'SPI Memory Organization', it is written down that the memory is organized as: * 16.772.216 bytes (typo here, there 16.777.216 bytes) * 128 sectors of 128 Kbytes each (correct) * 131.072 pages of 64 bytes each (typo here, as the total would be 64Mbit, but the total memory is actually 128Mbit, correct value is 262.144 pages) Patch tested against the aforementioned PCM memory. No known regressions inserted, as the patch only adds the possibility to recognize said PCM memory inside the common spi-nor driver. Signed-off-by: Andrea Zanotti --- drivers/mtd/spi-nor/micron-st.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index c224e59820a1..c78331451082 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -128,6 +128,7 @@ static const struct flash_info micron_parts[] = { { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { "np8p128ax60", {0x89, 0xda, 0x18}, 3, 128 * 1024, 128, 64, 0, 0 }, }; static const struct flash_info st_parts[] = {