From patchwork Fri Aug 20 16:00:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1519097 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=f2vbrT3j; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GrmfZ2GHPz9sXV for ; Sat, 21 Aug 2021 02:04:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237925AbhHTQEs (ORCPT ); Fri, 20 Aug 2021 12:04:48 -0400 Received: from mail.kernel.org ([198.145.29.99]:43964 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234754AbhHTQC3 (ORCPT ); Fri, 20 Aug 2021 12:02:29 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5EA7061279; Fri, 20 Aug 2021 16:01:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629475311; bh=Yz4EIOxD0zxgcfNz/zM6CTVGtACZ7WoqmNizOWQhqmo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f2vbrT3jkKY17nmu1ZEqsEwl+1Ef2ir5VNEID6wyODHcHbzaaC+Wrarse1UbKD6d4 T7mZJG4yuJbsSx23h295fh9QfLslzywaIvf9F6YWWcfROUzybb04Hl6yxPXR4bPjVq h7qgddTEQ7h5CKzWqeXi7JU+88LPdLztIiyC1Hnhupv+iQNzFfK0G3BiLNscaVIkJx mOK0e+XtVZ5DUnIn1LfBBrpTY0qT61iN5oOMGo6XQijbxavtkGE0Pn1TqLcQcvffWW 1J4f8GKvKXN11WQTcv23uKmtQxF0sZXxweWtRQ3haYOBnfVNs3tJjTvwXvXby+zV5u VS/HiZlDXZyyw== Received: by pali.im (Postfix) id 80CBFB8A; Fri, 20 Aug 2021 18:01:49 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Rob Herring , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Marek_Beh=C3=BAn?= , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/3] dt-bindings: Add 'slot-power-limit' PCIe port property Date: Fri, 20 Aug 2021 18:00:21 +0200 Message-Id: <20210820160023.3243-2-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210820160023.3243-1-pali@kernel.org> References: <20210820160023.3243-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This property specifies slot power limit in mW unit. It is form-factor and board specific value and must be initialized by hardware. Some PCIe controllers delegates this work to software to allow hardware flexibility and therefore this property basically specifies what should host bridge programs into PCIe Slot Capabilities registers. Property needs to be specified in mW unit, and not in special format defined by Slot Capabilities (which encodes scaling factor or different unit). Host drivers should convert value from mW unit to their format. Signed-off-by: Pali Rohár --- Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 6a8f2874a24d..e67d5db21514 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -32,6 +32,12 @@ driver implementation may support the following properties: root port to downstream device and host bridge drivers can do programming which depends on CLKREQ signal existence. For example, programming root port not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. +- slot-power-limit: + If present this property specifies slot power limit in mW unit. Host drivers + can parse this slot power limit and use it for programming Root Port or host + bridge, or for composing and sending PCIe Set_Slot_Power_Limit message + through the Root Port or host bridge when transitioning PCIe link from a + non-DL_Up Status to a DL_Up Status. PCI-PCI Bridge properties ------------------------- From patchwork Fri Aug 20 16:00:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1519099 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=cg8AXYyf; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Grmh35qxkz9sWq for ; Sat, 21 Aug 2021 02:05:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233801AbhHTQGP (ORCPT ); Fri, 20 Aug 2021 12:06:15 -0400 Received: from mail.kernel.org ([198.145.29.99]:43998 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbhHTQCa (ORCPT ); Fri, 20 Aug 2021 12:02:30 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 895B561354; Fri, 20 Aug 2021 16:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629475312; bh=78IR/EQoyvmDQWCnnDOdjLShYpeojXRJBTg83Xksn9E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cg8AXYyfBSV2w8XZXtZFhZqDVzBiH1OnG5Eb5QxXbTIK8B+vulV0W4eoXHYjFXPAi ConeToGdxlsPwS4GxGRlOVb0/HiFIHq9l4OdiJt2Bw57tVz94aB5S1Qxej1l4EVuI1 ClG7XdQ9JQicU+Ckv3XCkzVUhHNGvI2t98yvhOEzAOcO5745kzr9YgLaxqsUmKzHSq D0t770ByxB6Bc7UHaKOaZLVppSo+VbwcXQwvr5yT9mYSxa5fgONGOcAgkkalD0WghY zUAki5NDYD4cJa2OiNjntXi/pXrlGB1a/6jcx0UVPKIIwEk29Kln1dTsQY5JnCbiY9 8fykkY9bvXC3A== Received: by pali.im (Postfix) id AC2C6B98; Fri, 20 Aug 2021 18:01:50 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Rob Herring , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Marek_Beh=C3=BAn?= , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/3] PCI: aardvark: Add support for sending Set_Slot_Power_Limit message Date: Fri, 20 Aug 2021 18:00:22 +0200 Message-Id: <20210820160023.3243-3-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210820160023.3243-1-pali@kernel.org> References: <20210820160023.3243-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to PCIe Base specification 3.0, when transitioning from a non-DL_Up Status to a DL_Up Status, the Port must initiate the transmission of a Set_Slot_Power_Limit Message to the other component on the Link to convey the value programmed in the Slot Power Limit Scale and Value fields of the Slot Capabilities register. This Transmission is optional if the Slot Capabilities register has not yet been initialized. As PCIe Root Bridge is emulated by kernel emulate readback of Slot Power Limit Scale and Value bits in Slot Capabilities register. Also send that Set_Slot_Power_Limit message via Message Generation Control Register in Link Up handler when link changes from down to up state and slot power limit value was defined. Slot power limit value is read from DT property 'slot-power-limit' which value is in mW unit. When this DT property is not specified then it is treated as "Slot Capabilities register has not yet been initialized". Signed-off-by: Pali Rohár --- .../devicetree/bindings/pci/aardvark-pci.txt | 2 + drivers/pci/controller/pci-aardvark.c | 66 ++++++++++++++++++- 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 2b8ca920a7fa..bb658f261db0 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -20,6 +20,7 @@ contain the following properties: define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered - phys: the PCIe PHY handle + - slot-power-limit: see pci.txt - max-link-speed: see pci.txt - reset-gpios: see pci.txt @@ -52,6 +53,7 @@ Example: <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; phys = <&comphy1 0>; + slot-power-limit: <10000>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c index f94898f6072f..cf704c199c15 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -166,6 +166,11 @@ #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) #define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208) #define DIS_ORD_CHK BIT(30) +#define PME_MSG_GEN_CTRL (LMI_BASE_ADDR + 0x220) +#define SEND_SET_SLOT_POWER_LIMIT BIT(13) +#define SEND_PME_TURN_OFF BIT(14) +#define SLOT_POWER_LIMIT_DATA_SHIFT 16 +#define SLOT_POWER_LIMIT_DATA_MASK GENMASK(25, 16) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -267,6 +272,7 @@ static bool advk_pcie_link_up(struct advk_pcie *pcie) { u32 val, ltssm_state; u16 slotsta, slotctl; + u32 slotpwr; bool link_up; val = advk_readl(pcie, CFG_REG); @@ -277,7 +283,25 @@ static bool advk_pcie_link_up(struct advk_pcie *pcie) pcie->link_up = true; slotsta = le16_to_cpu(pcie->bridge.pcie_conf.slotsta); slotctl = le16_to_cpu(pcie->bridge.pcie_conf.slotctl); + slotpwr = (le32_to_cpu(pcie->bridge.pcie_conf.slotcap) & + (PCI_EXP_SLTCAP_SPLV | PCI_EXP_SLTCAP_SPLS)) >> 7; pcie->bridge.pcie_conf.slotsta = cpu_to_le16(slotsta | PCI_EXP_SLTSTA_DLLSC); + if (!(slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE) && slotpwr) { + /* + * According to PCIe Base specification 3.0, when transitioning from a + * non-DL_Up Status to a DL_Up Status, the Port must initiate the + * transmission of a Set_Slot_Power_Limit Message to the other component + * on the Link to convey the value programmed in the Slot Power Limit + * Scale and Value fields of the Slot Capabilities register. This + * Transmission is optional if the Slot Capabilities register has not + * yet been initialized. + */ + val = advk_readl(pcie, PME_MSG_GEN_CTRL); + val &= ~SLOT_POWER_LIMIT_DATA_MASK; + val |= slotpwr << SLOT_POWER_LIMIT_DATA_SHIFT; + val |= SEND_SET_SLOT_POWER_LIMIT; + advk_writel(pcie, val, PME_MSG_GEN_CTRL); + } if ((slotctl & PCI_EXP_SLTCTL_DLLSCE) && (slotctl & PCI_EXP_SLTCTL_HPIE)) mod_timer(&pcie->link_up_irq_timer, jiffies + 1); } @@ -956,6 +980,9 @@ static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) { struct pci_bridge_emul *bridge = &pcie->bridge; + struct device *dev = &pcie->pdev->dev; + u8 slot_power_limit_scale, slot_power_limit_value; + u32 slot_power_limit; int ret; bridge->conf.vendor = @@ -988,6 +1015,40 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) /* Indicates supports for Completion Retry Status */ bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); + if (of_property_read_u32(dev->of_node, "slot-power-limit", &slot_power_limit)) + slot_power_limit = 0; + + if (slot_power_limit) + dev_info(dev, "Slot power limit %u.%uW\n", slot_power_limit / 1000, + (slot_power_limit / 100) % 10); + + /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ + if (slot_power_limit == 0) { + slot_power_limit_scale = 0; + slot_power_limit_value = 0x00; + } else if (slot_power_limit <= 255) { + slot_power_limit_scale = 3; + slot_power_limit_value = slot_power_limit; + } else if (slot_power_limit <= 255*10) { + slot_power_limit_scale = 2; + slot_power_limit_value = slot_power_limit / 10; + } else if (slot_power_limit <= 255*100) { + slot_power_limit_scale = 1; + slot_power_limit_value = slot_power_limit / 100; + } else if (slot_power_limit <= 239*1000) { + slot_power_limit_scale = 0; + slot_power_limit_value = slot_power_limit / 1000; + } else if (slot_power_limit <= 250*1000) { + slot_power_limit_scale = 0; + slot_power_limit_value = 0xF0; + } else if (slot_power_limit <= 275*1000) { + slot_power_limit_scale = 0; + slot_power_limit_value = 0xF1; + } else { + slot_power_limit_scale = 0; + slot_power_limit_value = 0xF2; + } + /* * Mark bridge as Hot-Plug Capable to allow delivering Data Link Layer * State Changed interrupt. No Command Completed Support is set because @@ -996,7 +1057,10 @@ static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) * bit permanently as there is no support for unplugging PCIe card from * the slot. Assume that PCIe card is always connected in slot. */ - bridge->pcie_conf.slotcap = cpu_to_le32(PCI_EXP_SLTCAP_NCCS | PCI_EXP_SLTCAP_HPC); + bridge->pcie_conf.slotcap = cpu_to_le32(PCI_EXP_SLTCAP_NCCS | + PCI_EXP_SLTCAP_HPC | + slot_power_limit_value << 7 | + slot_power_limit_scale << 15); bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); return 0; From patchwork Fri Aug 20 16:00:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pali_Roh=C3=A1r?= X-Patchwork-Id: 1519098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=UCrloWHJ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Grmff72Qzz9sXV for ; Sat, 21 Aug 2021 02:04:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234436AbhHTQE5 (ORCPT ); Fri, 20 Aug 2021 12:04:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:43980 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234797AbhHTQCa (ORCPT ); Fri, 20 Aug 2021 12:02:30 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 359376125F; Fri, 20 Aug 2021 16:01:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629475312; bh=E0spK2WvLv0kR6hFChEuyMy0Zl7nye/F5istWij8HSY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UCrloWHJSOMX1LJD7jHHyA9GepGsK+T3wFE+RRSHNJaZyFRQ8B0Oy/PjSJLJXgbdV w6MotSpZt5Bm6PNrMtbAY/q7a4HTT6U/7fe6N778Y0ZO7vH1pfIZMOvSAjhq46DNjP i16X4uHrU/z8EP3BIwvjt0Crg0UeRPPckFxI6RjeWjQ6s9VK7Z86BkMMLhOXKgvp4L iwaH8/EZkIyecDDceDPowGhxW1A2mjGrcwA5rSISfOSN8NOnS+Ul3isWwuYijJBuOm sQmLrAVs8uGYWk1PpRdx1eJBl+wsWoYd7iV7xjM6RAhCNy4jGYYaENzWXxjxL8S08R O9cm8dS55A+jA== Received: by pali.im (Postfix) id EC4F17C5; Fri, 20 Aug 2021 18:01:51 +0200 (CEST) From: =?utf-8?q?Pali_Roh=C3=A1r?= To: Rob Herring , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Marek_Beh=C3=BAn?= , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/3] arm64: dts: armada-3720-turris-mox: Define slot-power-limit for PCIe Date: Fri, 20 Aug 2021 18:00:23 +0200 Message-Id: <20210820160023.3243-4-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210820160023.3243-1-pali@kernel.org> References: <20210820160023.3243-1-pali@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCIe Slot Power Limit on Turris Mox is 10W. Signed-off-by: Pali Rohár --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 86b3025f174b..1db928dff9ec 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -134,6 +134,7 @@ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + slot-power-limit = <10000>; /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and