From patchwork Fri Aug 6 03:32:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1514171 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=QUXdHp6i; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ggrf32DDRz9sPf for ; Fri, 6 Aug 2021 13:32:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6366B383B41F for ; Fri, 6 Aug 2021 03:32:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6366B383B41F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1628220775; bh=cQYtxOgAfc8y/POC0bMtVsfy3o1WkXu8+Xd7dcD0WOM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=QUXdHp6iuCu2a8NqVLKi5IPyWyY+Ze67Iktek3vI4wF8UDudiDHn18s9l81WjVhU3 pZLJjv61eA/7LKL6e/duEs1AktQgiISyUMeBe8E9MfVvgMJ/VOdUa7DJ2J4UFALqR7 pWyrpfmNop/JW+N91+qNSiDC+npOTKJEqRVnTGF8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 3B906383B41F for ; Fri, 6 Aug 2021 03:32:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3B906383B41F X-IronPort-AV: E=McAfee;i="6200,9189,10067"; a="201485482" X-IronPort-AV: E=Sophos;i="5.84,299,1620716400"; d="scan'208";a="201485482" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2021 20:32:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,299,1620716400"; d="scan'208";a="669241169" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga006.fm.intel.com with ESMTP; 05 Aug 2021 20:32:30 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 1763WSVl031145; Thu, 5 Aug 2021 20:32:29 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Make sure we're playing with integral modes before call extract_integral_bit_field. Date: Fri, 6 Aug 2021 11:32:28 +0800 Message-Id: <20210806033228.3270579-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Cc: richard.sandiford@arm.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi: --- OK, I think sth is amiss here upthread. insv/extv do look like they are designed to work on integer modes (but docs do not say anything about this here). In fact the caller of extract_bit_field_using_extv is named extract_integral_bit_field. Of course nothing seems to check what kind of modes we're dealing with, but we're for example happily doing expand_shift in 'mode'. In the extract_integral_bit_field call 'mode' is some integer mode and op0 is HFmode? From the above I get it's the other way around? In that case we should wrap the call to extract_integral_bit_field, extracting in an integer mode with the same size as 'mode' and then converting the result as (subreg:HF (reg:HI ...)). --- This is a separate patch as a follow up of upper comments. gcc/ChangeLog: * expmed.c (extract_bit_field_1): Wrap the call to extract_integral_bit_field, extracting in an integer mode with the same size as 'tmode' and then converting the result as (subreg:tmode (reg:imode)). gcc/testsuite/ChangeLog: * gcc.target/i386/float16-5.c: New test. --- gcc/expmed.c | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/float16-5.c | 12 ++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/float16-5.c diff --git a/gcc/expmed.c b/gcc/expmed.c index 3143f38e057..72790693ef0 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -1850,6 +1850,25 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, op0_mode = opt_scalar_int_mode (); } + /* Make sure we are playing with integral modes. Pun with subregs + if we aren't. When tmode is HFmode, op0 is SImode, there will be ICE + in extract_integral_bit_field. */ + if (int_mode_for_mode (tmode).exists (&imode) + && imode != tmode + && imode != GET_MODE (op0)) + { + rtx ret = extract_integral_bit_field (op0, op0_mode, + bitsize.to_constant (), + bitnum.to_constant (), unsignedp, + NULL, imode, imode, + reverse, fallback_p); + gcc_assert (ret); + + if (!REG_P (ret)) + ret = force_reg (imode, ret); + return gen_lowpart_SUBREG (tmode, ret); + } + /* It's possible we'll need to handle other cases here for polynomial bitnum and bitsize. */ diff --git a/gcc/testsuite/gcc.target/i386/float16-5.c b/gcc/testsuite/gcc.target/i386/float16-5.c new file mode 100644 index 00000000000..ebc0af1490b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/float16-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +_Float16 +foo (int a) +{ + union { + int a; + _Float16 b; + }c; + c.a = a; + return c.b; +}